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[AArch64] Add ARMv8.3 PACGA instruction
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
6f2750fe 3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
40#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 41#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 42#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 43#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
44#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
45#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 46#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 47#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 48#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 49#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 50#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 51#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 52#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 53#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 54#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 55#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
a06ea964
NC		 56
57/* Architectures are the sum of the base and extensions. */
58#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
59 AARCH64_FEATURE_FP \
60 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 61#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
62 AARCH64_FEATURE_CRC \
250aafa4 63 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 64 | AARCH64_FEATURE_LSE \
65 | AARCH64_FEATURE_PAN \
66 | AARCH64_FEATURE_LOR \
67 | AARCH64_FEATURE_RDMA)
1924ff75 68#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 69 AARCH64_FEATURE_V8_2 \
87018195 70 | AARCH64_FEATURE_F16 \
1924ff75
SN		 71 | AARCH64_FEATURE_RAS)
72#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
73 AARCH64_FEATURE_V8_3)
88f0ea34 74
a06ea964
NC		 75#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
76#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
77
78/* CPU-specific features. */
79typedef unsigned long aarch64_feature_set;
80
93d8990c
SN		 81#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
82 ((~(CPU) & (FEAT)) == 0)
83
84#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 85 (((CPU) & (FEAT)) != 0)
86
93d8990c
SN		 87#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
88 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
89
a06ea964
NC		 90#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
91 do \
92 { \
93 (TARG) = (F1) | (F2); \
94 } \
95 while (0)
96
97#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
98 do \
99 { \
100 (TARG) = (F1) &~ (F2); \
101 } \
102 while (0)
103
104#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
105
a06ea964
NC		 106enum aarch64_operand_class
107{
108 AARCH64_OPND_CLASS_NIL,
109 AARCH64_OPND_CLASS_INT_REG,
110 AARCH64_OPND_CLASS_MODIFIED_REG,
111 AARCH64_OPND_CLASS_FP_REG,
112 AARCH64_OPND_CLASS_SIMD_REG,
113 AARCH64_OPND_CLASS_SIMD_ELEMENT,
114 AARCH64_OPND_CLASS_SISD_REG,
115 AARCH64_OPND_CLASS_SIMD_REGLIST,
116 AARCH64_OPND_CLASS_CP_REG,
f11ad6bc
RS		 117 AARCH64_OPND_CLASS_SVE_REG,
118 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 119 AARCH64_OPND_CLASS_ADDRESS,
120 AARCH64_OPND_CLASS_IMMEDIATE,
121 AARCH64_OPND_CLASS_SYSTEM,
68a64283 122 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 123};
124
125/* Operand code that helps both parsing and coding.
126 Keep AARCH64_OPERANDS synced. */
127
128enum aarch64_opnd
129{
130 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
131
132 AARCH64_OPND_Rd, /* Integer register as destination. */
133 AARCH64_OPND_Rn, /* Integer register as source. */
134 AARCH64_OPND_Rm, /* Integer register as source. */
135 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
136 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
137 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
138 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
139 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
140
141 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
142 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 143 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 144 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 145 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
146 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
147
148 AARCH64_OPND_Fd, /* Floating-point Fd. */
149 AARCH64_OPND_Fn, /* Floating-point Fn. */
150 AARCH64_OPND_Fm, /* Floating-point Fm. */
151 AARCH64_OPND_Fa, /* Floating-point Fa. */
152 AARCH64_OPND_Ft, /* Floating-point Ft. */
153 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
154
155 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
156 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
157 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
158
159 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
160 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
161 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
162 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
163 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
164 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
165 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
166 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
167 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
168 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
169 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
170 structure to all lanes. */
171 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
172
173 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
174 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
175
176 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
177 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
178 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
179 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
180 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
181 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
182 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
183 (no encoding). */
184 AARCH64_OPND_IMM0, /* Immediate for #0. */
185 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
186 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
187 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
188 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
189 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
190 AARCH64_OPND_IMM, /* Immediate. */
191 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
192 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
193 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
194 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
195 AARCH64_OPND_BIT_NUM, /* Immediate. */
196 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
197 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 198 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 199 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
200 each condition flag. */
201
202 AARCH64_OPND_LIMM, /* Logical Immediate. */
203 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
204 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
205 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
206 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
207
208 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 209 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 210
211 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
212 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
213 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
214 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
215 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
216
217 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
218 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
219 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
220 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
221 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
222 negative or unaligned and there is
223 no writeback allowed. This operand code
224 is only used to support the programmer-
225 friendly feature of using LDR/STR as the
226 the mnemonic name for LDUR/STUR instructions
227 wherever there is no ambiguity. */
228 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
229 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
230 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
231
232 AARCH64_OPND_SYSREG, /* System register operand. */
233 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
234 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
235 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
236 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
237 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
238 AARCH64_OPND_BARRIER, /* Barrier operand. */
239 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
240 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 241 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
f11ad6bc 242
98907a70
RS		 243 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
244 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
245 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
246 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
247 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
248 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 249 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
250 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
251 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
252 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
253 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
254 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
255 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
256 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
257 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
258 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
259 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
260 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
261 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
262 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
263 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
264 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
265 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
266 Bit 14 controls S/U choice. */
267 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
268 Bit 22 controls S/U choice. */
269 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
270 Bit 14 controls S/U choice. */
271 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
272 Bit 22 controls S/U choice. */
273 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
274 Bit 14 controls S/U choice. */
275 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
276 Bit 22 controls S/U choice. */
277 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
278 Bit 14 controls S/U choice. */
279 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
280 Bit 22 controls S/U choice. */
281 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
282 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
283 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
284 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
285 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
286 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
287 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 288 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
289 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 290 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
291 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
292 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
293 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
e950b345
RS		 294 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
295 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
296 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 297 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 298 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 299 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 300 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
301 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
302 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
303 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
304 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
305 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
306 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
307 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 308 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
309 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 310 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
311 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
312 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
313 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
314 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
315 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
316 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
317 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
318 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
319 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
320 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
321 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 322 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
323 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
324 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
325 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 326 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
327 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
328 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
329 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
330 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
331 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
332 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
333 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
334 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
335 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
a06ea964
NC		 336};
337
338/* Qualifier constrains an operand. It either specifies a variant of an
339 operand type or limits values available to an operand type.
340
341 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
342
343enum aarch64_opnd_qualifier
344{
345 /* Indicating no further qualification on an operand. */
346 AARCH64_OPND_QLF_NIL,
347
348 /* Qualifying an operand which is a general purpose (integer) register;
349 indicating the operand data size or a specific register. */
350 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
351 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
352 AARCH64_OPND_QLF_WSP, /* WSP. */
353 AARCH64_OPND_QLF_SP, /* SP. */
354
355 /* Qualifying an operand which is a floating-point register, a SIMD
356 vector element or a SIMD vector element list; indicating operand data
357 size or the size of each SIMD vector element in the case of a SIMD
358 vector element list.
359 These qualifiers are also used to qualify an address operand to
360 indicate the size of data element a load/store instruction is
361 accessing.
362 They are also used for the immediate shift operand in e.g. SSHR. Such
363 a use is only for the ease of operand encoding/decoding and qualifier
364 sequence matching; such a use should not be applied widely; use the value
365 constraint qualifiers for immediate operands wherever possible. */
366 AARCH64_OPND_QLF_S_B,
367 AARCH64_OPND_QLF_S_H,
368 AARCH64_OPND_QLF_S_S,
369 AARCH64_OPND_QLF_S_D,
370 AARCH64_OPND_QLF_S_Q,
371
372 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
373 register list; indicating register shape.
374 They are also used for the immediate shift operand in e.g. SSHR. Such
375 a use is only for the ease of operand encoding/decoding and qualifier
376 sequence matching; such a use should not be applied widely; use the value
377 constraint qualifiers for immediate operands wherever possible. */
378 AARCH64_OPND_QLF_V_8B,
379 AARCH64_OPND_QLF_V_16B,
3067d3b9 380 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 381 AARCH64_OPND_QLF_V_4H,
382 AARCH64_OPND_QLF_V_8H,
383 AARCH64_OPND_QLF_V_2S,
384 AARCH64_OPND_QLF_V_4S,
385 AARCH64_OPND_QLF_V_1D,
386 AARCH64_OPND_QLF_V_2D,
387 AARCH64_OPND_QLF_V_1Q,
388
d50c751e
RS		 389 AARCH64_OPND_QLF_P_Z,
390 AARCH64_OPND_QLF_P_M,
391
a06ea964
NC		 392 /* Constraint on value. */
393 AARCH64_OPND_QLF_imm_0_7,
394 AARCH64_OPND_QLF_imm_0_15,
395 AARCH64_OPND_QLF_imm_0_31,
396 AARCH64_OPND_QLF_imm_0_63,
397 AARCH64_OPND_QLF_imm_1_32,
398 AARCH64_OPND_QLF_imm_1_64,
399
400 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
401 or shift-ones. */
402 AARCH64_OPND_QLF_LSL,
403 AARCH64_OPND_QLF_MSL,
404
405 /* Special qualifier helping retrieve qualifier information during the
406 decoding time (currently not in use). */
407 AARCH64_OPND_QLF_RETRIEVE,
408};
409\f
410/* Instruction class. */
411
412enum aarch64_insn_class
413{
414 addsub_carry,
415 addsub_ext,
416 addsub_imm,
417 addsub_shift,
418 asimdall,
419 asimddiff,
420 asimdelem,
421 asimdext,
422 asimdimm,
423 asimdins,
424 asimdmisc,
425 asimdperm,
426 asimdsame,
427 asimdshf,
428 asimdtbl,
429 asisddiff,
430 asisdelem,
431 asisdlse,
432 asisdlsep,
433 asisdlso,
434 asisdlsop,
435 asisdmisc,
436 asisdone,
437 asisdpair,
438 asisdsame,
439 asisdshf,
440 bitfield,
441 branch_imm,
442 branch_reg,
443 compbranch,
444 condbranch,
445 condcmp_imm,
446 condcmp_reg,
447 condsel,
448 cryptoaes,
449 cryptosha2,
450 cryptosha3,
451 dp_1src,
452 dp_2src,
453 dp_3src,
454 exception,
455 extract,
456 float2fix,
457 float2int,
458 floatccmp,
459 floatcmp,
460 floatdp1,
461 floatdp2,
462 floatdp3,
463 floatimm,
464 floatsel,
465 ldst_immpost,
466 ldst_immpre,
467 ldst_imm9, /* immpost or immpre */
468 ldst_pos,
469 ldst_regoff,
470 ldst_unpriv,
471 ldst_unscaled,
472 ldstexcl,
473 ldstnapair_offs,
474 ldstpair_off,
475 ldstpair_indexed,
476 loadlit,
477 log_imm,
478 log_shift,
ee804238 479 lse_atomic,
a06ea964
NC		 480 movewide,
481 pcreladdr,
482 ic_system,
116b6019
RS		 483 sve_cpy,
484 sve_index,
485 sve_limm,
486 sve_misc,
487 sve_movprfx,
488 sve_pred_zm,
489 sve_shift_pred,
490 sve_shift_unpred,
491 sve_size_bhs,
492 sve_size_bhsd,
493 sve_size_hsd,
494 sve_size_sd,
a06ea964
NC		 495 testbranch,
496};
497
498/* Opcode enumerators. */
499
500enum aarch64_op
501{
502 OP_NIL,
503 OP_STRB_POS,
504 OP_LDRB_POS,
505 OP_LDRSB_POS,
506 OP_STRH_POS,
507 OP_LDRH_POS,
508 OP_LDRSH_POS,
509 OP_STR_POS,
510 OP_LDR_POS,
511 OP_STRF_POS,
512 OP_LDRF_POS,
513 OP_LDRSW_POS,
514 OP_PRFM_POS,
515
516 OP_STURB,
517 OP_LDURB,
518 OP_LDURSB,
519 OP_STURH,
520 OP_LDURH,
521 OP_LDURSH,
522 OP_STUR,
523 OP_LDUR,
524 OP_STURV,
525 OP_LDURV,
526 OP_LDURSW,
527 OP_PRFUM,
528
529 OP_LDR_LIT,
530 OP_LDRV_LIT,
531 OP_LDRSW_LIT,
532 OP_PRFM_LIT,
533
534 OP_ADD,
535 OP_B,
536 OP_BL,
537
538 OP_MOVN,
539 OP_MOVZ,
540 OP_MOVK,
541
542 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
543 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
544 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
545
546 OP_MOV_V, /* MOV alias for moving vector register. */
547
548 OP_ASR_IMM,
549 OP_LSR_IMM,
550 OP_LSL_IMM,
551
552 OP_BIC,
553
554 OP_UBFX,
555 OP_BFXIL,
556 OP_SBFX,
557 OP_SBFIZ,
558 OP_BFI,
d685192a 559 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 560 OP_UBFIZ,
561 OP_UXTB,
562 OP_UXTH,
563 OP_UXTW,
564
a06ea964
NC		 565 OP_CINC,
566 OP_CINV,
567 OP_CNEG,
568 OP_CSET,
569 OP_CSETM,
570
571 OP_FCVT,
572 OP_FCVTN,
573 OP_FCVTN2,
574 OP_FCVTL,
575 OP_FCVTL2,
576 OP_FCVTXN_S, /* Scalar version. */
577
578 OP_ROR_IMM,
579
e30181a5
YZ		 580 OP_SXTL,
581 OP_SXTL2,
582 OP_UXTL,
583 OP_UXTL2,
584
c0890d26
RS		 585 OP_MOV_P_P,
586 OP_MOV_Z_P_Z,
587 OP_MOV_Z_V,
588 OP_MOV_Z_Z,
589 OP_MOV_Z_Zi,
590 OP_MOVM_P_P_P,
591 OP_MOVS_P_P,
592 OP_MOVZS_P_P_P,
593 OP_MOVZ_P_P_P,
594 OP_NOTS_P_P_P_Z,
595 OP_NOT_P_P_P_Z,
596
a06ea964
NC		 597 OP_TOTAL_NUM, /* Pseudo. */
598};
599
600/* Maximum number of operands an instruction can have. */
601#define AARCH64_MAX_OPND_NUM 6
602/* Maximum number of qualifier sequences an instruction can have. */
603#define AARCH64_MAX_QLF_SEQ_NUM 10
604/* Operand qualifier typedef; optimized for the size. */
605typedef unsigned char aarch64_opnd_qualifier_t;
606/* Operand qualifier sequence typedef. */
607typedef aarch64_opnd_qualifier_t \
608 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
609
610/* FIXME: improve the efficiency. */
611static inline bfd_boolean
612empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
613{
614 int i;
615 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
616 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
617 return FALSE;
618 return TRUE;
619}
620
621/* This structure holds information for a particular opcode. */
622
623struct aarch64_opcode
624{
625 /* The name of the mnemonic. */
626 const char *name;
627
628 /* The opcode itself. Those bits which will be filled in with
629 operands are zeroes. */
630 aarch64_insn opcode;
631
632 /* The opcode mask. This is used by the disassembler. This is a
633 mask containing ones indicating those bits which must match the
634 opcode field, and zeroes indicating those bits which need not
635 match (and are presumably filled in by operands). */
636 aarch64_insn mask;
637
638 /* Instruction class. */
639 enum aarch64_insn_class iclass;
640
641 /* Enumerator identifier. */
642 enum aarch64_op op;
643
644 /* Which architecture variant provides this instruction. */
645 const aarch64_feature_set *avariant;
646
647 /* An array of operand codes. Each code is an index into the
648 operand table. They appear in the order which the operands must
649 appear in assembly code, and are terminated by a zero. */
650 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
651
652 /* A list of operand qualifier code sequence. Each operand qualifier
653 code qualifies the corresponding operand code. Each operand
654 qualifier sequence specifies a valid opcode variant and related
655 constraint on operands. */
656 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
657
658 /* Flags providing information about this instruction */
659 uint32_t flags;
4bd13cde 660
0c608d6b
RS		 661 /* If nonzero, this operand and operand 0 are both registers and
662 are required to have the same register number. */
663 unsigned char tied_operand;
664
4bd13cde
NC		 665 /* If non-NULL, a function to verify that a given instruction is valid. */
666 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
a06ea964
NC		 667};
668
669typedef struct aarch64_opcode aarch64_opcode;
670
671/* Table describing all the AArch64 opcodes. */
672extern aarch64_opcode aarch64_opcode_table[];
673
674/* Opcode flags. */
675#define F_ALIAS (1 << 0)
676#define F_HAS_ALIAS (1 << 1)
677/* Disassembly preference priority 1-3 (the larger the higher). If nothing
678 is specified, it is the priority 0 by default, i.e. the lowest priority. */
679#define F_P1 (1 << 2)
680#define F_P2 (2 << 2)
681#define F_P3 (3 << 2)
682/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
683#define F_COND (1 << 4)
684/* Instruction has the field of 'sf'. */
685#define F_SF (1 << 5)
686/* Instruction has the field of 'size:Q'. */
687#define F_SIZEQ (1 << 6)
688/* Floating-point instruction has the field of 'type'. */
689#define F_FPTYPE (1 << 7)
690/* AdvSIMD scalar instruction has the field of 'size'. */
691#define F_SSIZE (1 << 8)
692/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
693#define F_T (1 << 9)
694/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
695#define F_GPRSIZE_IN_Q (1 << 10)
696/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
697#define F_LDS_SIZE (1 << 11)
698/* Optional operand; assume maximum of 1 operand can be optional. */
699#define F_OPD0_OPT (1 << 12)
700#define F_OPD1_OPT (2 << 12)
701#define F_OPD2_OPT (3 << 12)
702#define F_OPD3_OPT (4 << 12)
703#define F_OPD4_OPT (5 << 12)
704/* Default value for the optional operand when omitted from the assembly. */
705#define F_DEFAULT(X) (((X) & 0x1f) << 15)
706/* Instruction that is an alias of another instruction needs to be
707 encoded/decoded by converting it to/from the real form, followed by
708 the encoding/decoding according to the rules of the real opcode.
709 This compares to the direct coding using the alias's information.
710 N.B. this flag requires F_ALIAS to be used together. */
711#define F_CONV (1 << 20)
712/* Use together with F_ALIAS to indicate an alias opcode is a programmer
713 friendly pseudo instruction available only in the assembly code (thus will
714 not show up in the disassembly). */
715#define F_PSEUDO (1 << 21)
716/* Instruction has miscellaneous encoding/decoding rules. */
717#define F_MISC (1 << 22)
718/* Instruction has the field of 'N'; used in conjunction with F_SF. */
719#define F_N (1 << 23)
720/* Opcode dependent field. */
721#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 722/* Instruction has the field of 'sz'. */
723#define F_LSE_SZ (1 << 27)
4989adac
RS		 724/* Require an exact qualifier match, even for NIL qualifiers. */
725#define F_STRICT (1ULL << 28)
726/* Next bit is 29. */
a06ea964
NC		 727
728static inline bfd_boolean
729alias_opcode_p (const aarch64_opcode *opcode)
730{
731 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
732}
733
734static inline bfd_boolean
735opcode_has_alias (const aarch64_opcode *opcode)
736{
737 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
738}
739
740/* Priority for disassembling preference. */
741static inline int
742opcode_priority (const aarch64_opcode *opcode)
743{
744 return (opcode->flags >> 2) & 0x3;
745}
746
747static inline bfd_boolean
748pseudo_opcode_p (const aarch64_opcode *opcode)
749{
750 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
751}
752
753static inline bfd_boolean
754optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
755{
756 return (((opcode->flags >> 12) & 0x7) == idx + 1)
757 ? TRUE : FALSE;
758}
759
760static inline aarch64_insn
761get_optional_operand_default_value (const aarch64_opcode *opcode)
762{
763 return (opcode->flags >> 15) & 0x1f;
764}
765
766static inline unsigned int
767get_opcode_dependent_value (const aarch64_opcode *opcode)
768{
769 return (opcode->flags >> 24) & 0x7;
770}
771
772static inline bfd_boolean
773opcode_has_special_coder (const aarch64_opcode *opcode)
774{
ee804238 775 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 776 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
777 : FALSE;
778}
779\f
780struct aarch64_name_value_pair
781{
782 const char * name;
783 aarch64_insn value;
784};
785
786extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 787extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
788extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 789extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 790
49eec193
YZ		 791typedef struct
792{
793 const char * name;
794 aarch64_insn value;
795 uint32_t flags;
796} aarch64_sys_reg;
797
798extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 799extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 800extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 801extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
802 const aarch64_sys_reg *);
803extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
804 const aarch64_sys_reg *);
49eec193 805
a06ea964
NC		 806typedef struct
807{
875880c6 808 const char *name;
a06ea964 809 uint32_t value;
ea2deeec 810 uint32_t flags ;
a06ea964
NC		 811} aarch64_sys_ins_reg;
812
ea2deeec 813extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 814extern bfd_boolean
815aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
816 const aarch64_sys_ins_reg *);
ea2deeec 817
a06ea964
NC		 818extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
819extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
820extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
821extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
822
823/* Shift/extending operator kinds.
824 N.B. order is important; keep aarch64_operand_modifiers synced. */
825enum aarch64_modifier_kind
826{
827 AARCH64_MOD_NONE,
828 AARCH64_MOD_MSL,
829 AARCH64_MOD_ROR,
830 AARCH64_MOD_ASR,
831 AARCH64_MOD_LSR,
832 AARCH64_MOD_LSL,
833 AARCH64_MOD_UXTB,
834 AARCH64_MOD_UXTH,
835 AARCH64_MOD_UXTW,
836 AARCH64_MOD_UXTX,
837 AARCH64_MOD_SXTB,
838 AARCH64_MOD_SXTH,
839 AARCH64_MOD_SXTW,
840 AARCH64_MOD_SXTX,
2442d846 841 AARCH64_MOD_MUL,
98907a70 842 AARCH64_MOD_MUL_VL,
a06ea964
NC		 843};
844
845bfd_boolean
846aarch64_extend_operator_p (enum aarch64_modifier_kind);
847
848enum aarch64_modifier_kind
849aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
850/* Condition. */
851
852typedef struct
853{
854 /* A list of names with the first one as the disassembly preference;
855 terminated by NULL if fewer than 3. */
bb7eff52 856 const char *names[4];
a06ea964
NC		 857 aarch64_insn value;
858} aarch64_cond;
859
860extern const aarch64_cond aarch64_conds[16];
861
862const aarch64_cond* get_cond_from_value (aarch64_insn value);
863const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
864\f
865/* Structure representing an operand. */
866
867struct aarch64_opnd_info
868{
869 enum aarch64_opnd type;
870 aarch64_opnd_qualifier_t qualifier;
871 int idx;
872
873 union
874 {
875 struct
876 {
877 unsigned regno;
878 } reg;
879 struct
880 {
dab26bf4
RS		 881 unsigned int regno;
882 int64_t index;
a06ea964
NC		 883 } reglane;
884 /* e.g. LVn. */
885 struct
886 {
887 unsigned first_regno : 5;
888 unsigned num_regs : 3;
889 /* 1 if it is a list of reg element. */
890 unsigned has_index : 1;
891 /* Lane index; valid only when has_index is 1. */
dab26bf4 892 int64_t index;
a06ea964
NC		 893 } reglist;
894 /* e.g. immediate or pc relative address offset. */
895 struct
896 {
897 int64_t value;
898 unsigned is_fp : 1;
899 } imm;
900 /* e.g. address in STR (register offset). */
901 struct
902 {
903 unsigned base_regno;
904 struct
905 {
906 union
907 {
908 int imm;
909 unsigned regno;
910 };
911 unsigned is_reg;
912 } offset;
913 unsigned pcrel : 1; /* PC-relative. */
914 unsigned writeback : 1;
915 unsigned preind : 1; /* Pre-indexed. */
916 unsigned postind : 1; /* Post-indexed. */
917 } addr;
918 const aarch64_cond *cond;
919 /* The encoding of the system register. */
920 aarch64_insn sysreg;
921 /* The encoding of the PSTATE field. */
922 aarch64_insn pstatefield;
923 const aarch64_sys_ins_reg *sysins_op;
924 const struct aarch64_name_value_pair *barrier;
9ed608f9 925 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 926 const struct aarch64_name_value_pair *prfop;
927 };
928
929 /* Operand shifter; in use when the operand is a register offset address,
930 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
931 struct
932 {
933 enum aarch64_modifier_kind kind;
a06ea964
NC		 934 unsigned operator_present: 1; /* Only valid during encoding. */
935 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
936 unsigned amount_present: 1;
2442d846 937 int64_t amount;
a06ea964
NC		 938 } shifter;
939
940 unsigned skip:1; /* Operand is not completed if there is a fixup needed
941 to be done on it. In some (but not all) of these
942 cases, we need to tell libopcodes to skip the
943 constraint checking and the encoding for this
944 operand, so that the libopcodes can pick up the
945 right opcode before the operand is fixed-up. This
946 flag should only be used during the
947 assembling/encoding. */
948 unsigned present:1; /* Whether this operand is present in the assembly
949 line; not used during the disassembly. */
950};
951
952typedef struct aarch64_opnd_info aarch64_opnd_info;
953
954/* Structure representing an instruction.
955
956 It is used during both the assembling and disassembling. The assembler
957 fills an aarch64_inst after a successful parsing and then passes it to the
958 encoding routine to do the encoding. During the disassembling, the
959 disassembler calls the decoding routine to decode a binary instruction; on a
960 successful return, such a structure will be filled with information of the
961 instruction; then the disassembler uses the information to print out the
962 instruction. */
963
964struct aarch64_inst
965{
966 /* The value of the binary instruction. */
967 aarch64_insn value;
968
969 /* Corresponding opcode entry. */
970 const aarch64_opcode *opcode;
971
972 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
973 const aarch64_cond *cond;
974
975 /* Operands information. */
976 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
977};
978
979typedef struct aarch64_inst aarch64_inst;
980\f
981/* Diagnosis related declaration and interface. */
982
983/* Operand error kind enumerators.
984
985 AARCH64_OPDE_RECOVERABLE
986 Less severe error found during the parsing, very possibly because that
987 GAS has picked up a wrong instruction template for the parsing.
988
989 AARCH64_OPDE_SYNTAX_ERROR
990 General syntax error; it can be either a user error, or simply because
991 that GAS is trying a wrong instruction template.
992
993 AARCH64_OPDE_FATAL_SYNTAX_ERROR
994 Definitely a user syntax error.
995
996 AARCH64_OPDE_INVALID_VARIANT
997 No syntax error, but the operands are not a valid combination, e.g.
998 FMOV D0,S0
999
0c608d6b
RS		 1000 AARCH64_OPDE_UNTIED_OPERAND
1001 The asm failed to use the same register for a destination operand
1002 and a tied source operand.
1003
a06ea964
NC		 1004 AARCH64_OPDE_OUT_OF_RANGE
1005 Error about some immediate value out of a valid range.
1006
1007 AARCH64_OPDE_UNALIGNED
1008 Error about some immediate value not properly aligned (i.e. not being a
1009 multiple times of a certain value).
1010
1011 AARCH64_OPDE_REG_LIST
1012 Error about the register list operand having unexpected number of
1013 registers.
1014
1015 AARCH64_OPDE_OTHER_ERROR
1016 Error of the highest severity and used for any severe issue that does not
1017 fall into any of the above categories.
1018
1019 The enumerators are only interesting to GAS. They are declared here (in
1020 libopcodes) because that some errors are detected (and then notified to GAS)
1021 by libopcodes (rather than by GAS solely).
1022
1023 The first three errors are only deteced by GAS while the
1024 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1025 only libopcodes has the information about the valid variants of each
1026 instruction.
1027
1028 The enumerators have an increasing severity. This is helpful when there are
1029 multiple instruction templates available for a given mnemonic name (e.g.
1030 FMOV); this mechanism will help choose the most suitable template from which
1031 the generated diagnostics can most closely describe the issues, if any. */
1032
1033enum aarch64_operand_error_kind
1034{
1035 AARCH64_OPDE_NIL,
1036 AARCH64_OPDE_RECOVERABLE,
1037 AARCH64_OPDE_SYNTAX_ERROR,
1038 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1039 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1040 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1041 AARCH64_OPDE_OUT_OF_RANGE,
1042 AARCH64_OPDE_UNALIGNED,
1043 AARCH64_OPDE_REG_LIST,
1044 AARCH64_OPDE_OTHER_ERROR
1045};
1046
1047/* N.B. GAS assumes that this structure work well with shallow copy. */
1048struct aarch64_operand_error
1049{
1050 enum aarch64_operand_error_kind kind;
1051 int index;
1052 const char *error;
1053 int data[3]; /* Some data for extra information. */
1054};
1055
1056typedef struct aarch64_operand_error aarch64_operand_error;
1057
1058/* Encoding entrypoint. */
1059
1060extern int
1061aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1062 aarch64_insn *, aarch64_opnd_qualifier_t *,
1063 aarch64_operand_error *);
1064
1065extern const aarch64_opcode *
1066aarch64_replace_opcode (struct aarch64_inst *,
1067 const aarch64_opcode *);
1068
1069/* Given the opcode enumerator OP, return the pointer to the corresponding
1070 opcode entry. */
1071
1072extern const aarch64_opcode *
1073aarch64_get_opcode (enum aarch64_op);
1074
1075/* Generate the string representation of an operand. */
1076extern void
1077aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1078 const aarch64_opnd_info *, int, int *, bfd_vma *);
1079
1080/* Miscellaneous interface. */
1081
1082extern int
1083aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1084
1085extern aarch64_opnd_qualifier_t
1086aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1087 const aarch64_opnd_qualifier_t, int);
1088
1089extern int
1090aarch64_num_of_operands (const aarch64_opcode *);
1091
1092extern int
1093aarch64_stack_pointer_p (const aarch64_opnd_info *);
1094
e141d84e
YQ		 1095extern int
1096aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1097
36f4aab1 1098extern int
43cdf5ae 1099aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
36f4aab1 1100
a06ea964
NC		 1101/* Given an operand qualifier, return the expected data element size
1102 of a qualified operand. */
1103extern unsigned char
1104aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1105
1106extern enum aarch64_operand_class
1107aarch64_get_operand_class (enum aarch64_opnd);
1108
1109extern const char *
1110aarch64_get_operand_name (enum aarch64_opnd);
1111
1112extern const char *
1113aarch64_get_operand_desc (enum aarch64_opnd);
1114
e950b345
RS		 1115extern bfd_boolean
1116aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1117
a06ea964
NC		 1118#ifdef DEBUG_AARCH64
1119extern int debug_dump;
1120
1121extern void
1122aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1123
1124#define DEBUG_TRACE(M, ...) \
1125 { \
1126 if (debug_dump) \
1127 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1128 }
1129
1130#define DEBUG_TRACE_IF(C, M, ...) \
1131 { \
1132 if (debug_dump && (C)) \
1133 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1134 }
1135#else /* !DEBUG_AARCH64 */
1136#define DEBUG_TRACE(M, ...) ;
1137#define DEBUG_TRACE_IF(C, M, ...) ;
1138#endif /* DEBUG_AARCH64 */
1139
245d2e3f
RS		 1140extern const char *const aarch64_sve_pattern_array[32];
1141extern const char *const aarch64_sve_prfop_array[16];
1142
d3e12b29
YQ		 1143#ifdef __cplusplus
1144}
1145#endif
1146
a06ea964 1147#endif /* OPCODE_AARCH64_H */
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