[deliverable/binutils-gdb.git] / include / opcode / arc.h

/* Opcode table for the ARC.
   Copyright 1994-2015 Free Software Foundation, Inc.

   Contributed by Claudiu Zissulescu (claziss@synopsys.com)

   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   the GNU Binutils.

   GAS/GDB is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GAS/GDB is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS or GDB; see the file COPYING3.  If not, write to
   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#ifndef OPCODE_ARC_H
#define OPCODE_ARC_H

#define MAX_INSN_ARGS	     6
#define MAX_INSN_FLGS	     3

/* Instruction Class.  */
typedef enum
  {
    ARITH,
    AUXREG,
    BRANCH,
    CONTROL,
    DSP,
    FLOAT,
    INVALID,
    JUMP,
    KERNEL,
    LOGICAL,
    MEMORY,
  } insn_class_t;

/* Instruction Subclass.  */
typedef enum
  {
    NONE,
    CVT,
    BTSCN,
    CD1,
    CD2,
    DIV,
    DP,
    MPY1E,
    MPY6E,
    MPY7E,
    MPY8E,
    MPY9E,
    SHFT1,
    SHFT2,
    SWAP,
    SP
  } insn_subclass_t;

/* Flags class.  */
typedef enum
  {
    FNONE,
    CND,  /* Conditional flags.  */
    WBM,  /* Write-back modes.  */
    FLG,  /* F Flag.  */
    SBP,  /* Static branch prediction.  */
    DLY,  /* Delay slot.  */
    DIF,  /* Bypass caches.  */
    SGX,  /* Sign extend modes.  */
    SZM   /* Data size modes.  */
  } flag_class_t;

/* The opcode table is an array of struct arc_opcode.  */
struct arc_opcode
{
  /* The opcode name.  */
  const char *name;

  /* The opcode itself.  Those bits which will be filled in with
     operands are zeroes.  */
  unsigned opcode;

  /* The opcode mask.  This is used by the disassembler.  This is a
     mask containing ones indicating those bits which must match the
     opcode field, and zeroes indicating those bits which need not
     match (and are presumably filled in by operands).  */
  unsigned mask;

  /* One bit flags for the opcode.  These are primarily used to
     indicate specific processors and environments support the
     instructions.  The defined values are listed below.  */
  unsigned cpu;

  /* The instruction class.  This is used by gdb.  */
  insn_class_t class;

  /* The instruction subclass.  */
  insn_subclass_t subclass;

  /* An array of operand codes.  Each code is an index into the
     operand table.  They appear in the order which the operands must
     appear in assembly code, and are terminated by a zero.  */
  unsigned char operands[MAX_INSN_ARGS + 1];

  /* An array of flag codes.  Each code is an index into the flag
     table.  They appear in the order which the flags must appear in
     assembly code, and are terminated by a zero.  */
  unsigned char flags[MAX_INSN_FLGS + 1];
};

/* The table itself is sorted by major opcode number, and is otherwise
   in the order in which the disassembler should consider
   instructions.  */
extern const struct arc_opcode arc_opcodes[];
extern const unsigned arc_num_opcodes;

/* CPU Availability.  */
#define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
#define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
#define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
#define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */

/* CPU extensions.  */
#define ARC_EA       0x0001
#define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
#define ARC_LLOCK    0x0002
#define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
#define ARC_MPY      0x0004
#define ARC_MULT     0x0004

/* Floating point support.  */
#define ARC_DPFP     0x0010
#define ARC_SPFP     0x0020
#define ARC_FPU      0x0030

/* NORM & SWAP.  */
#define ARC_SWAP     0x0100
#define ARC_NORM     0x0200
#define ARC_BSCAN    0x0200

/* A7 specific.  */
#define ARC_UIX      0x1000
#define ARC_TSTAMP   0x1000

/* A6 specific.  */
#define ARC_VBFDW    0x1000
#define ARC_BARREL   0x1000
#define ARC_DSPA     0x1000

/* EM specific.  */
#define ARC_SHIFT    0x1000

/* V2 specific.  */
#define ARC_INTR     0x1000
#define ARC_DIV      0x1000

/* V1 specific.  */
#define ARC_XMAC     0x1000
#define ARC_CRC      0x1000

/* Base architecture -- all cpus.  */
#define ARC_OPCODE_BASE				\
  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700	\
   | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)

/* A macro to check for short instructions.  */
#define ARC_SHORT(mask)				\
  (((mask) & 0xFFFF0000) ? 0 : 1)

/* The operands table is an array of struct arc_operand.  */
struct arc_operand
{
  /* The number of bits in the operand.  */
  unsigned int bits;

  /* How far the operand is left shifted in the instruction.  */
  unsigned int shift;

  /* The default relocation type for this operand.  */
  signed int default_reloc;

  /* One bit syntax flags.  */
  unsigned int flags;

  /* Insertion function.  This is used by the assembler.  To insert an
     operand value into an instruction, check this field.

     If it is NULL, execute
	 i |= (op & ((1 << o->bits) - 1)) << o->shift;
     (i is the instruction which we are filling in, o is a pointer to
     this structure, and op is the opcode value; this assumes twos
     complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction and the operand value.	 It will return the new value
     of the instruction.  If the ERRMSG argument is not NULL, then if
     the operand value is illegal, *ERRMSG will be set to a warning
     string (the operand will be inserted in any case).	 If the
     operand value is legal, *ERRMSG will be unchanged (most operands
     can accept any value).  */
  unsigned (*insert) (unsigned instruction, int op, const char **errmsg);

  /* Extraction function.  This is used by the disassembler.  To
     extract this operand type from an instruction, check this field.

     If it is NULL, compute
	 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
	 if ((o->flags & ARC_OPERAND_SIGNED) != 0
	     && (op & (1 << (o->bits - 1))) != 0)
	   op -= 1 << o->bits;
     (i is the instruction, o is a pointer to this structure, and op
     is the result; this assumes twos complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction value.	 It will return the value of the operand.  If
     the INVALID argument is not NULL, *INVALID will be set to
     TRUE if this operand type can not actually be extracted from
     this operand (i.e., the instruction does not match).  If the
     operand is valid, *INVALID will not be changed.  */
  int (*extract) (unsigned instruction, bfd_boolean *invalid);
};

/* Elements in the table are retrieved by indexing with values from
   the operands field of the arc_opcodes table.  */
extern const struct arc_operand arc_operands[];
extern const unsigned arc_num_operands;
extern const unsigned arc_Toperand;
extern const unsigned arc_NToperand;

/* Values defined for the flags field of a struct arc_operand.  */

/* This operand does not actually exist in the assembler input.  This
   is used to support extended mnemonics, for which two operands fields
   are identical.  The assembler should call the insert function with
   any op value.  The disassembler should call the extract function,
   ignore the return value, and check the value placed in the invalid
   argument.  */
#define ARC_OPERAND_FAKE	0x0001

/* This operand names an integer register.  */
#define ARC_OPERAND_IR		0x0002

/* This operand takes signed values.  */
#define ARC_OPERAND_SIGNED	0x0004

/* This operand takes unsigned values.  This exists primarily so that
   a flags value of 0 can be treated as end-of-arguments.  */
#define ARC_OPERAND_UNSIGNED	0x0008

/* This operand takes long immediate values.  */
#define ARC_OPERAND_LIMM	0x0010

/* This operand is identical like the previous one.  */
#define ARC_OPERAND_DUPLICATE   0x0020

/* This operand is PC relative.  Used for internal relocs.  */
#define ARC_OPERAND_PCREL       0x0040

/* This operand is truncated.  The truncation is done accordingly to
   operand alignment attribute.  */
#define ARC_OPERAND_TRUNCATE    0x0080

/* This operand is 16bit aligned.  */
#define ARC_OPERAND_ALIGNED16   0x0100

/* This operand is 32bit aligned.  */
#define ARC_OPERAND_ALIGNED32   0x0200

/* This operand can be ignored by matching process if it is not
   present.  */
#define ARC_OPERAND_IGNORE      0x0400

/* Don't check the range when matching.	 */
#define ARC_OPERAND_NCHK	0x0800

/* Mark the braket possition.  */
#define ARC_OPERAND_BRAKET      0x1000

/* Mask for selecting the type for typecheck purposes.  */
#define ARC_OPERAND_TYPECHECK_MASK		\
  (ARC_OPERAND_IR |				\
   ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | 	\
   ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)

/* The flags structure.  */
struct arc_flag_operand
{
  /* The flag name.  */
  const char *name;

  /* The flag code.  */
  unsigned code;

  /* The number of bits in the operand.  */
  unsigned int bits;

  /* How far the operand is left shifted in the instruction.  */
  unsigned int shift;

  /* Available for disassembler.  */
  unsigned char favail;
};

/* The flag operands table.  */
extern const struct arc_flag_operand arc_flag_operands[];
extern const unsigned arc_num_flag_operands;

/* The flag's class structure.  */
struct arc_flag_class
{
  /* Flag class.  */
  flag_class_t class;

  /* List of valid flags (codes).  */
  unsigned flags[256];
};

extern const struct arc_flag_class arc_flag_classes[];

/* Structure for special cases.  */
struct arc_flag_special
{
  /* Name of special case instruction.  */
  const char *name;

  /* List of flags applicable for special case instruction.  */
  unsigned flags[32];
};

extern const struct arc_flag_special arc_flag_special_cases[];
extern const unsigned arc_num_flag_special;

/* Relocation equivalence structure.  */
struct arc_reloc_equiv_tab
{
  const char * name;	   /* String to lookup.  */
  const char * mnemonic;   /* Extra matching condition.  */
  unsigned     flags[32];  /* Extra matching condition.  */
  signed int   oldreloc;   /* Old relocation.  */
  signed int   newreloc;   /* New relocation.  */
};

extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
extern const unsigned arc_num_equiv_tab;

/* Structure for operand operations for pseudo/alias instructions.  */
struct arc_operand_operation
{
  /* The index for operand from operand array.  */
  unsigned operand_idx;

  /* Defines if it needs the operand inserted by the assembler or
     whether this operand comes from the pseudo instruction's
     operands.  */
  unsigned char needs_insert;

  /* Count we have to add to the operand.  Use negative number to
     subtract from the operand.  Also use this number to add to 0 if
     the operand needs to be inserted (i.e. needs_insert == 1).  */
  int count;

  /* Index of the operand to swap with.  To be done AFTER applying
     inc_count.  */
  unsigned swap_operand_idx;
};

/* Structure for pseudo/alias instructions.  */
struct arc_pseudo_insn
{
  /* Mnemonic for pseudo/alias insn.  */
  const char *mnemonic_p;

  /* Mnemonic for real instruction.  */
  const char *mnemonic_r;

  /* Flag that will have to be added (if any).  */
  const char *flag_r;

  /* Amount of operands.  */
  unsigned operand_cnt;

  /* Array of operand operations.  */
  struct arc_operand_operation operand[6];
};

extern const struct arc_pseudo_insn arc_pseudo_insns[];
extern const unsigned arc_num_pseudo_insn;

/* Structure for AUXILIARY registers.  */
struct arc_aux_reg
{
  /* Register address.  */
  int address;

 /* Register name.  */
  const char *name;

  /* Size of the string.  */
  size_t length;
};

extern const struct arc_aux_reg arc_aux_regs[];
extern const unsigned arc_num_aux_regs;

#endif /* OPCODE_ARC_H */
Commit	Line	Data
252b5132	1	/* Opcode table for the ARC.
886a2506 NC	2	Copyright 1994-2015 Free Software Foundation, Inc.
	3
	4	Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132	5
0d2bcfaf NC	6	This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
0d2bcfaf NC	7	the GNU Binutils.
252b5132	8
0d2bcfaf NC	9	GAS/GDB is free software; you can redistribute it and/or modify
0d2bcfaf NC	10	it under the terms of the GNU General Public License as published by
e4e42b45	11	the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf	12	any later version.
252b5132	13
0d2bcfaf NC	14	GAS/GDB is distributed in the hope that it will be useful,
0d2bcfaf NC	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf NC	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
e4e42b45	20	along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8 NC	21	the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
e172dbf8 NC	22	MA 02110-1301, USA. */
252b5132	23
886a2506 NC	24	#ifndef OPCODE_ARC_H
	25	#define OPCODE_ARC_H
	26
	27	#define MAX_INSN_ARGS 6
	28	#define MAX_INSN_FLGS 3
	29
	30	/* Instruction Class. */
	31	typedef enum
	32	{
	33	ARITH,
	34	AUXREG,
	35	BRANCH,
	36	CONTROL,
	37	DSP,
	38	FLOAT,
	39	INVALID,
	40	JUMP,
	41	KERNEL,
	42	LOGICAL,
	43	MEMORY,
	44	} insn_class_t;
	45
	46	/* Instruction Subclass. */
	47	typedef enum
	48	{
	49	NONE,
	50	CVT,
	51	BTSCN,
	52	CD1,
	53	CD2,
	54	DIV,
	55	DP,
	56	MPY1E,
	57	MPY6E,
	58	MPY7E,
	59	MPY8E,
	60	MPY9E,
	61	SHFT1,
	62	SHFT2,
	63	SWAP,
	64	SP
	65	} insn_subclass_t;
	66
	67	/* Flags class. */
	68	typedef enum
	69	{
	70	FNONE,
	71	CND, /* Conditional flags. */
	72	WBM, /* Write-back modes. */
	73	FLG, /* F Flag. */
	74	SBP, /* Static branch prediction. */
	75	DLY, /* Delay slot. */
	76	DIF, /* Bypass caches. */
	77	SGX, /* Sign extend modes. */
	78	SZM /* Data size modes. */
	79	} flag_class_t;
	80
	81	/* The opcode table is an array of struct arc_opcode. */
	82	struct arc_opcode
	83	{
	84	/* The opcode name. */
	85	const char *name;
	86
	87	/* The opcode itself. Those bits which will be filled in with
88	operands are zeroes. */
89	unsigned opcode;
90
91	/* The opcode mask. This is used by the disassembler. This is a
92	mask containing ones indicating those bits which must match the
93	opcode field, and zeroes indicating those bits which need not
94	match (and are presumably filled in by operands). */
95	unsigned mask;
96
97	/* One bit flags for the opcode. These are primarily used to
98	indicate specific processors and environments support the
99	instructions. The defined values are listed below. */
100	unsigned cpu;
101
102	/* The instruction class. This is used by gdb. */
103	insn_class_t class;
104
105	/* The instruction subclass. */
106	insn_subclass_t subclass;
107
108	/* An array of operand codes. Each code is an index into the
109	operand table. They appear in the order which the operands must
110	appear in assembly code, and are terminated by a zero. */
111	unsigned char operands[MAX_INSN_ARGS + 1];
112
113	/* An array of flag codes. Each code is an index into the flag
114	table. They appear in the order which the flags must appear in
115	assembly code, and are terminated by a zero. */
116	unsigned char flags[MAX_INSN_FLGS + 1];
117	};
252b5132	118
886a2506 NC	119	/* The table itself is sorted by major opcode number, and is otherwise
	120	in the order in which the disassembler should consider
	121	instructions. */
	122	extern const struct arc_opcode arc_opcodes[];
	123	extern const unsigned arc_num_opcodes;
	124
	125	/* CPU Availability. */
	126	#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
	127	#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
	128	#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
	129	#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
	130
	131	/* CPU extensions. */
	132	#define ARC_EA 0x0001
	133	#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
	134	#define ARC_LLOCK 0x0002
	135	#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
	136	#define ARC_MPY 0x0004
	137	#define ARC_MULT 0x0004
	138
	139	/* Floating point support. */
	140	#define ARC_DPFP 0x0010
	141	#define ARC_SPFP 0x0020
	142	#define ARC_FPU 0x0030
	143
	144	/* NORM & SWAP. */
	145	#define ARC_SWAP 0x0100
	146	#define ARC_NORM 0x0200
	147	#define ARC_BSCAN 0x0200
	148
	149	/* A7 specific. */
	150	#define ARC_UIX 0x1000
	151	#define ARC_TSTAMP 0x1000
	152
	153	/* A6 specific. */
	154	#define ARC_VBFDW 0x1000
	155	#define ARC_BARREL 0x1000
	156	#define ARC_DSPA 0x1000
	157
	158	/* EM specific. */
	159	#define ARC_SHIFT 0x1000
	160
	161	/* V2 specific. */
	162	#define ARC_INTR 0x1000
	163	#define ARC_DIV 0x1000
	164
	165	/* V1 specific. */
	166	#define ARC_XMAC 0x1000
	167	#define ARC_CRC 0x1000
	168
	169	/* Base architecture -- all cpus. */
	170	#define ARC_OPCODE_BASE \
	171	(ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \
	172	\| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS)
	173
	174	/* A macro to check for short instructions. */
	175	#define ARC_SHORT(mask) \
	176	(((mask) & 0xFFFF0000) ? 0 : 1)
	177
	178	/* The operands table is an array of struct arc_operand. */
	179	struct arc_operand
	180	{
	181	/* The number of bits in the operand. */
	182	unsigned int bits;
183
184	/* How far the operand is left shifted in the instruction. */
185	unsigned int shift;
186
187	/* The default relocation type for this operand. */
188	signed int default_reloc;
189
190	/* One bit syntax flags. */
191	unsigned int flags;
192
193	/* Insertion function. This is used by the assembler. To insert an
194	operand value into an instruction, check this field.
195
196	If it is NULL, execute
197	i \|= (op & ((1 << o->bits) - 1)) << o->shift;
198	(i is the instruction which we are filling in, o is a pointer to
199	this structure, and op is the opcode value; this assumes twos
200	complement arithmetic).
201
202	If this field is not NULL, then simply call it with the
203	instruction and the operand value. It will return the new value
204	of the instruction. If the ERRMSG argument is not NULL, then if
205	the operand value is illegal, *ERRMSG will be set to a warning
206	string (the operand will be inserted in any case). If the
207	operand value is legal, *ERRMSG will be unchanged (most operands
208	can accept any value). */
209	unsigned (insert) (unsigned instruction, int op, const char *errmsg);
210
211	/* Extraction function. This is used by the disassembler. To
212	extract this operand type from an instruction, check this field.
213
214	If it is NULL, compute
215	op = ((i) >> o->shift) & ((1 << o->bits) - 1);
216	if ((o->flags & ARC_OPERAND_SIGNED) != 0
217	&& (op & (1 << (o->bits - 1))) != 0)
218	op -= 1 << o->bits;
219	(i is the instruction, o is a pointer to this structure, and op
220	is the result; this assumes twos complement arithmetic).
221
222	If this field is not NULL, then simply call it with the
223	instruction value. It will return the value of the operand. If
224	the INVALID argument is not NULL, *INVALID will be set to
225	TRUE if this operand type can not actually be extracted from
226	this operand (i.e., the instruction does not match). If the
227	operand is valid, INVALID will not be changed. /
228	int (extract) (unsigned instruction, bfd_boolean invalid);
229	};
0d2bcfaf	230
886a2506 NC	231	/* Elements in the table are retrieved by indexing with values from
	232	the operands field of the arc_opcodes table. */
	233	extern const struct arc_operand arc_operands[];
	234	extern const unsigned arc_num_operands;
	235	extern const unsigned arc_Toperand;
	236	extern const unsigned arc_NToperand;
252b5132	237
886a2506	238	/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf	239
886a2506 NC	240	/* This operand does not actually exist in the assembler input. This
	241	is used to support extended mnemonics, for which two operands fields
	242	are identical. The assembler should call the insert function with
	243	any op value. The disassembler should call the extract function,
	244	ignore the return value, and check the value placed in the invalid
	245	argument. */
	246	#define ARC_OPERAND_FAKE 0x0001
252b5132	247
886a2506 NC	248	/* This operand names an integer register. */
886a2506 NC	249	#define ARC_OPERAND_IR 0x0002
0d2bcfaf	250
886a2506 NC	251	/* This operand takes signed values. */
886a2506 NC	252	#define ARC_OPERAND_SIGNED 0x0004
252b5132	253
886a2506 NC	254	/* This operand takes unsigned values. This exists primarily so that
	255	a flags value of 0 can be treated as end-of-arguments. */
	256	#define ARC_OPERAND_UNSIGNED 0x0008
252b5132	257
886a2506 NC	258	/* This operand takes long immediate values. */
886a2506 NC	259	#define ARC_OPERAND_LIMM 0x0010
252b5132	260
886a2506 NC	261	/* This operand is identical like the previous one. */
886a2506 NC	262	#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf	263
886a2506 NC	264	/* This operand is PC relative. Used for internal relocs. */
886a2506 NC	265	#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf	266
886a2506 NC	267	/* This operand is truncated. The truncation is done accordingly to
	268	operand alignment attribute. */
	269	#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf	270
886a2506 NC	271	/* This operand is 16bit aligned. */
886a2506 NC	272	#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf	273
886a2506 NC	274	/* This operand is 32bit aligned. */
886a2506 NC	275	#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf	276
886a2506 NC	277	/* This operand can be ignored by matching process if it is not
	278	present. */
	279	#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf	280
886a2506 NC	281	/* Don't check the range when matching. */
886a2506 NC	282	#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf	283
886a2506 NC	284	/* Mark the braket possition. */
886a2506 NC	285	#define ARC_OPERAND_BRAKET 0x1000
252b5132	286
886a2506 NC	287	/* Mask for selecting the type for typecheck purposes. */
	288	#define ARC_OPERAND_TYPECHECK_MASK \
	289	(ARC_OPERAND_IR \| \
	290	ARC_OPERAND_LIMM \| ARC_OPERAND_SIGNED \| \
	291	ARC_OPERAND_UNSIGNED \| ARC_OPERAND_BRAKET)
252b5132	292
886a2506 NC	293	/* The flags structure. */
	294	struct arc_flag_operand
	295	{
	296	/* The flag name. */
	297	const char *name;
0d2bcfaf	298
886a2506 NC	299	/* The flag code. */
886a2506 NC	300	unsigned code;
252b5132	301
886a2506 NC	302	/* The number of bits in the operand. */
886a2506 NC	303	unsigned int bits;
252b5132	304
886a2506 NC	305	/* How far the operand is left shifted in the instruction. */
886a2506 NC	306	unsigned int shift;
252b5132	307
886a2506 NC	308	/* Available for disassembler. */
886a2506 NC	309	unsigned char favail;
84037f8c KD	310	};
84037f8c KD	311
886a2506 NC	312	/* The flag operands table. */
	313	extern const struct arc_flag_operand arc_flag_operands[];
	314	extern const unsigned arc_num_flag_operands;
0d2bcfaf	315
886a2506 NC	316	/* The flag's class structure. */
	317	struct arc_flag_class
	318	{
	319	/* Flag class. */
	320	flag_class_t class;
252b5132	321
886a2506 NC	322	/* List of valid flags (codes). */
	323	unsigned flags[256];
	324	};
252b5132	325
886a2506	326	extern const struct arc_flag_class arc_flag_classes[];
252b5132	327
886a2506 NC	328	/* Structure for special cases. */
	329	struct arc_flag_special
	330	{
	331	/* Name of special case instruction. */
	332	const char *name;
252b5132	333
886a2506 NC	334	/* List of flags applicable for special case instruction. */
	335	unsigned flags[32];
	336	};
252b5132	337
886a2506 NC	338	extern const struct arc_flag_special arc_flag_special_cases[];
	339	extern const unsigned arc_num_flag_special;
	340
	341	/* Relocation equivalence structure. */
	342	struct arc_reloc_equiv_tab
	343	{
	344	const char * name; /* String to lookup. */
	345	const char * mnemonic; /* Extra matching condition. */
24b368f8	346	unsigned flags[32]; /* Extra matching condition. */
886a2506 NC	347	signed int oldreloc; /* Old relocation. */
	348	signed int newreloc; /* New relocation. */
	349	};
252b5132	350
886a2506 NC	351	extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
886a2506 NC	352	extern const unsigned arc_num_equiv_tab;
252b5132	353
886a2506 NC	354	/* Structure for operand operations for pseudo/alias instructions. */
	355	struct arc_operand_operation
	356	{
	357	/* The index for operand from operand array. */
	358	unsigned operand_idx;
252b5132	359
886a2506 NC	360	/* Defines if it needs the operand inserted by the assembler or
	361	whether this operand comes from the pseudo instruction's
	362	operands. */
	363	unsigned char needs_insert;
252b5132	364
886a2506 NC	365	/* Count we have to add to the operand. Use negative number to
	366	subtract from the operand. Also use this number to add to 0 if
	367	the operand needs to be inserted (i.e. needs_insert == 1). */
	368	int count;
252b5132	369
886a2506 NC	370	/* Index of the operand to swap with. To be done AFTER applying
	371	inc_count. */
	372	unsigned swap_operand_idx;
252b5132 RH	373	};
252b5132 RH	374
886a2506 NC	375	/* Structure for pseudo/alias instructions. */
	376	struct arc_pseudo_insn
	377	{
	378	/* Mnemonic for pseudo/alias insn. */
	379	const char *mnemonic_p;
252b5132	380
886a2506 NC	381	/* Mnemonic for real instruction. */
886a2506 NC	382	const char *mnemonic_r;
252b5132	383
886a2506 NC	384	/* Flag that will have to be added (if any). */
886a2506 NC	385	const char *flag_r;
252b5132	386
886a2506 NC	387	/* Amount of operands. */
886a2506 NC	388	unsigned operand_cnt;
252b5132	389
886a2506 NC	390	/* Array of operand operations. */
	391	struct arc_operand_operation operand[6];
	392	};
252b5132	393
886a2506 NC	394	extern const struct arc_pseudo_insn arc_pseudo_insns[];
886a2506 NC	395	extern const unsigned arc_num_pseudo_insn;
252b5132	396
886a2506 NC	397	/* Structure for AUXILIARY registers. */
	398	struct arc_aux_reg
	399	{
	400	/* Register address. */
	401	int address;
252b5132	402
886a2506 NC	403	/* Register name. */
	404	const char *name;
	405
	406	/* Size of the string. */
	407	size_t length;
	408	};
	409
	410	extern const struct arc_aux_reg arc_aux_regs[];
	411	extern const unsigned arc_num_aux_regs;
	412
	413	#endif /* OPCODE_ARC_H */