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[ARC] ISA alignment.
[deliverable/binutils-gdb.git] / include / opcode / arc.h
CommitLineData
252b5132 1/* Opcode table for the ARC.
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132 5
0d2bcfaf
NC		 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
7 the GNU Binutils.
252b5132 8
0d2bcfaf
NC		 9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
e4e42b45 11 the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf 12 any later version.
252b5132 13
0d2bcfaf
NC		 14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf
NC		 17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
e4e42b45 20 along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8
NC		 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
886a2506
NC		 24#ifndef OPCODE_ARC_H
25#define OPCODE_ARC_H
26
6b477896
TS		 27#ifdef __cplusplus
28extern "C" {
29#endif
30
4670103e 31#ifndef MAX_INSN_ARGS
4eb6f892 32#define MAX_INSN_ARGS 16
4670103e
CZ		 33#endif
34
35#ifndef MAX_INSN_FLGS
886a2506 36#define MAX_INSN_FLGS 3
4670103e 37#endif
886a2506
NC		 38
39/* Instruction Class. */
40typedef enum
db18dbab
GM		 41{
42 ACL,
43 ARITH,
44 AUXREG,
45 BITOP,
2b848ebd 46 BITSTREAM,
db18dbab
GM		 47 BMU,
48 BRANCH,
49 CONTROL,
50 DPI,
51 DSP,
52 FLOAT,
53 INVALID,
54 JUMP,
55 KERNEL,
56 LOGICAL,
57 MEMORY,
58 NET,
2b848ebd
CZ		 59 PMU,
60 XY
db18dbab 61} insn_class_t;
886a2506
NC		 62
63/* Instruction Subclass. */
64typedef enum
db18dbab
GM		 65{
66 NONE,
67 CVT,
68 BTSCN,
69 CD1,
70 CD2,
71 COND,
72 DIV,
73 DP,
74 DPA,
75 DPX,
76 MPY1E,
77 MPY6E,
78 MPY7E,
79 MPY8E,
80 MPY9E,
81 NPS400,
82 QUARKSE,
83 SHFT1,
84 SHFT2,
85 SWAP,
86 SP,
87 SPX
88} insn_subclass_t;
886a2506
NC		 89
90/* Flags class. */
91typedef enum
db18dbab
GM		 92{
93 F_CLASS_NONE = 0,
1ae8ab47 94
db18dbab
GM		 95 /* At most one flag from the set of flags can appear in the
96 instruction. */
97 F_CLASS_OPTIONAL = (1 << 0),
1ae8ab47 98
db18dbab
GM		 99 /* Exactly one from from the set of flags must appear in the
100 instruction. */
101 F_CLASS_REQUIRED = (1 << 1),
f36e33da 102
db18dbab
GM		 103 /* The conditional code can be extended over the standard variants
104 via .extCondCode pseudo-op. */
105 F_CLASS_EXTEND = (1 << 2),
d9eca1df 106
db18dbab
GM		 107 /* Condition code flag. */
108 F_CLASS_COND = (1 << 3)
109} flag_class_t;
886a2506
NC		 110
111/* The opcode table is an array of struct arc_opcode. */
112struct arc_opcode
113{
114 /* The opcode name. */
115 const char *name;
116
117 /* The opcode itself. Those bits which will be filled in with
118 operands are zeroes. */
119 unsigned opcode;
120
121 /* The opcode mask. This is used by the disassembler. This is a
122 mask containing ones indicating those bits which must match the
123 opcode field, and zeroes indicating those bits which need not
124 match (and are presumably filled in by operands). */
125 unsigned mask;
126
127 /* One bit flags for the opcode. These are primarily used to
128 indicate specific processors and environments support the
129 instructions. The defined values are listed below. */
130 unsigned cpu;
131
132 /* The instruction class. This is used by gdb. */
c810e0b8 133 insn_class_t insn_class;
886a2506
NC		 134
135 /* The instruction subclass. */
136 insn_subclass_t subclass;
137
138 /* An array of operand codes. Each code is an index into the
139 operand table. They appear in the order which the operands must
140 appear in assembly code, and are terminated by a zero. */
141 unsigned char operands[MAX_INSN_ARGS + 1];
142
143 /* An array of flag codes. Each code is an index into the flag
144 table. They appear in the order which the flags must appear in
145 assembly code, and are terminated by a zero. */
146 unsigned char flags[MAX_INSN_FLGS + 1];
147};
252b5132 148
4eb6f892
AB		 149/* Structure used to describe 48 and 64 bit instructions. */
150struct arc_long_opcode
151{
152 /* The base instruction is either 16 or 32 bits, and is described like a
153 normal instruction. */
154 struct arc_opcode base_opcode;
155
156 /* The template value for the 32-bit LIMM extension. Used by the
157 assembler and disassembler in the same way as the 'opcode' field of
158 'struct arc_opcode'. */
159 unsigned limm_template;
160
161 /* The mask value for the 32-bit LIMM extension. Used by the
162 disassembler just like the 'mask' field in 'struct arc_opcode'. */
163 unsigned limm_mask;
164
165 /* Array of operand codes similar to the 'operands' array in 'struct
166 arc_opcode'. These operands are used to fill in the LIMM value. */
167 unsigned char operands[MAX_INSN_ARGS + 1];
168};
169
170extern const struct arc_long_opcode arc_long_opcodes[];
171extern const unsigned arc_num_long_opcodes;
172
886a2506
NC		 173/* The table itself is sorted by major opcode number, and is otherwise
174 in the order in which the disassembler should consider
175 instructions. */
176extern const struct arc_opcode arc_opcodes[];
886a2506
NC		 177
178/* CPU Availability. */
f36e33da 179#define ARC_OPCODE_NONE 0x0000
886a2506
NC		 180#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
181#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
182#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
183#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
184
f36e33da
CZ		 185/* CPU combi. */
186#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
187 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
188#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
189
886a2506
NC		 190/* CPU extensions. */
191#define ARC_EA 0x0001
192#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
193#define ARC_LLOCK 0x0002
194#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
195#define ARC_MPY 0x0004
196#define ARC_MULT 0x0004
bdd582db 197#define ARC_NPS400 0x0008
886a2506
NC		 198
199/* Floating point support. */
200#define ARC_DPFP 0x0010
201#define ARC_SPFP 0x0020
202#define ARC_FPU 0x0030
8ddf6b2a 203#define ARC_FPUDA 0x0040
886a2506
NC		 204
205/* NORM & SWAP. */
206#define ARC_SWAP 0x0100
207#define ARC_NORM 0x0200
208#define ARC_BSCAN 0x0200
209
210/* A7 specific. */
211#define ARC_UIX 0x1000
212#define ARC_TSTAMP 0x1000
213
214/* A6 specific. */
215#define ARC_VBFDW 0x1000
216#define ARC_BARREL 0x1000
217#define ARC_DSPA 0x1000
218
219/* EM specific. */
220#define ARC_SHIFT 0x1000
221
222/* V2 specific. */
223#define ARC_INTR 0x1000
224#define ARC_DIV 0x1000
225
226/* V1 specific. */
227#define ARC_XMAC 0x1000
228#define ARC_CRC 0x1000
229
886a2506
NC		 230/* A macro to check for short instructions. */
231#define ARC_SHORT(mask) \
232 (((mask) & 0xFFFF0000) ? 0 : 1)
233
234/* The operands table is an array of struct arc_operand. */
235struct arc_operand
236{
237 /* The number of bits in the operand. */
238 unsigned int bits;
239
240 /* How far the operand is left shifted in the instruction. */
241 unsigned int shift;
242
243 /* The default relocation type for this operand. */
244 signed int default_reloc;
245
246 /* One bit syntax flags. */
247 unsigned int flags;
248
249 /* Insertion function. This is used by the assembler. To insert an
250 operand value into an instruction, check this field.
251
252 If it is NULL, execute
253 i |= (op & ((1 << o->bits) - 1)) << o->shift;
254 (i is the instruction which we are filling in, o is a pointer to
255 this structure, and op is the opcode value; this assumes twos
256 complement arithmetic).
257
258 If this field is not NULL, then simply call it with the
259 instruction and the operand value. It will return the new value
260 of the instruction. If the ERRMSG argument is not NULL, then if
261 the operand value is illegal, *ERRMSG will be set to a warning
262 string (the operand will be inserted in any case). If the
263 operand value is legal, *ERRMSG will be unchanged (most operands
264 can accept any value). */
265 unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
266
267 /* Extraction function. This is used by the disassembler. To
268 extract this operand type from an instruction, check this field.
269
270 If it is NULL, compute
271 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
272 if ((o->flags & ARC_OPERAND_SIGNED) != 0
273 && (op & (1 << (o->bits - 1))) != 0)
274 op -= 1 << o->bits;
275 (i is the instruction, o is a pointer to this structure, and op
276 is the result; this assumes twos complement arithmetic).
277
278 If this field is not NULL, then simply call it with the
279 instruction value. It will return the value of the operand. If
280 the INVALID argument is not NULL, *INVALID will be set to
281 TRUE if this operand type can not actually be extracted from
282 this operand (i.e., the instruction does not match). If the
283 operand is valid, *INVALID will not be changed. */
284 int (*extract) (unsigned instruction, bfd_boolean *invalid);
285};
0d2bcfaf 286
886a2506
NC		 287/* Elements in the table are retrieved by indexing with values from
288 the operands field of the arc_opcodes table. */
289extern const struct arc_operand arc_operands[];
290extern const unsigned arc_num_operands;
291extern const unsigned arc_Toperand;
292extern const unsigned arc_NToperand;
252b5132 293
886a2506 294/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf 295
886a2506
NC		 296/* This operand does not actually exist in the assembler input. This
297 is used to support extended mnemonics, for which two operands fields
298 are identical. The assembler should call the insert function with
299 any op value. The disassembler should call the extract function,
300 ignore the return value, and check the value placed in the invalid
301 argument. */
302#define ARC_OPERAND_FAKE 0x0001
252b5132 303
886a2506
NC		 304/* This operand names an integer register. */
305#define ARC_OPERAND_IR 0x0002
0d2bcfaf 306
886a2506
NC		 307/* This operand takes signed values. */
308#define ARC_OPERAND_SIGNED 0x0004
252b5132 309
886a2506
NC		 310/* This operand takes unsigned values. This exists primarily so that
311 a flags value of 0 can be treated as end-of-arguments. */
312#define ARC_OPERAND_UNSIGNED 0x0008
252b5132 313
886a2506
NC		 314/* This operand takes long immediate values. */
315#define ARC_OPERAND_LIMM 0x0010
252b5132 316
886a2506
NC		 317/* This operand is identical like the previous one. */
318#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf 319
886a2506
NC		 320/* This operand is PC relative. Used for internal relocs. */
321#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf 322
886a2506
NC		 323/* This operand is truncated. The truncation is done accordingly to
324 operand alignment attribute. */
325#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf 326
886a2506
NC		 327/* This operand is 16bit aligned. */
328#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf 329
886a2506
NC		 330/* This operand is 32bit aligned. */
331#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf 332
886a2506
NC		 333/* This operand can be ignored by matching process if it is not
334 present. */
335#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf 336
886a2506
NC		 337/* Don't check the range when matching. */
338#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf 339
886a2506
NC		 340/* Mark the braket possition. */
341#define ARC_OPERAND_BRAKET 0x1000
252b5132 342
db18dbab
GM		 343/* Address type operand for NPS400. */
344#define ARC_OPERAND_ADDRTYPE 0x2000
345
346/* Mark the colon position. */
347#define ARC_OPERAND_COLON 0x4000
348
886a2506 349/* Mask for selecting the type for typecheck purposes. */
db18dbab
GM		 350#define ARC_OPERAND_TYPECHECK_MASK \
351 (ARC_OPERAND_IR \
352 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \
353 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \
354 | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
355
356/* Macro to determine if an operand is a fake operand. */
357#define ARC_OPERAND_IS_FAKE(op) \
358 ((operand->flags & ARC_OPERAND_FAKE) \
359 && !((operand->flags & ARC_OPERAND_BRAKET) \
360 || (operand->flags & ARC_OPERAND_COLON)))
252b5132 361
886a2506
NC		 362/* The flags structure. */
363struct arc_flag_operand
364{
365 /* The flag name. */
366 const char *name;
0d2bcfaf 367
886a2506
NC		 368 /* The flag code. */
369 unsigned code;
252b5132 370
886a2506
NC		 371 /* The number of bits in the operand. */
372 unsigned int bits;
252b5132 373
886a2506
NC		 374 /* How far the operand is left shifted in the instruction. */
375 unsigned int shift;
252b5132 376
886a2506
NC		 377 /* Available for disassembler. */
378 unsigned char favail;
84037f8c
KD		 379};
380
886a2506
NC		 381/* The flag operands table. */
382extern const struct arc_flag_operand arc_flag_operands[];
383extern const unsigned arc_num_flag_operands;
0d2bcfaf 384
886a2506
NC		 385/* The flag's class structure. */
386struct arc_flag_class
387{
388 /* Flag class. */
c810e0b8 389 flag_class_t flag_class;
252b5132 390
886a2506
NC		 391 /* List of valid flags (codes). */
392 unsigned flags[256];
393};
252b5132 394
886a2506 395extern const struct arc_flag_class arc_flag_classes[];
252b5132 396
886a2506
NC		 397/* Structure for special cases. */
398struct arc_flag_special
399{
400 /* Name of special case instruction. */
401 const char *name;
252b5132 402
886a2506
NC		 403 /* List of flags applicable for special case instruction. */
404 unsigned flags[32];
405};
252b5132 406
886a2506
NC		 407extern const struct arc_flag_special arc_flag_special_cases[];
408extern const unsigned arc_num_flag_special;
409
410/* Relocation equivalence structure. */
411struct arc_reloc_equiv_tab
412{
413 const char * name; /* String to lookup. */
414 const char * mnemonic; /* Extra matching condition. */
24b368f8 415 unsigned flags[32]; /* Extra matching condition. */
886a2506
NC		 416 signed int oldreloc; /* Old relocation. */
417 signed int newreloc; /* New relocation. */
418};
252b5132 419
886a2506
NC		 420extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
421extern const unsigned arc_num_equiv_tab;
252b5132 422
886a2506
NC		 423/* Structure for operand operations for pseudo/alias instructions. */
424struct arc_operand_operation
425{
426 /* The index for operand from operand array. */
427 unsigned operand_idx;
252b5132 428
886a2506
NC		 429 /* Defines if it needs the operand inserted by the assembler or
430 whether this operand comes from the pseudo instruction's
431 operands. */
432 unsigned char needs_insert;
252b5132 433
886a2506
NC		 434 /* Count we have to add to the operand. Use negative number to
435 subtract from the operand. Also use this number to add to 0 if
436 the operand needs to be inserted (i.e. needs_insert == 1). */
437 int count;
252b5132 438
886a2506
NC		 439 /* Index of the operand to swap with. To be done AFTER applying
440 inc_count. */
441 unsigned swap_operand_idx;
252b5132
RH		 442};
443
886a2506
NC		 444/* Structure for pseudo/alias instructions. */
445struct arc_pseudo_insn
446{
447 /* Mnemonic for pseudo/alias insn. */
448 const char *mnemonic_p;
252b5132 449
886a2506
NC		 450 /* Mnemonic for real instruction. */
451 const char *mnemonic_r;
252b5132 452
886a2506
NC		 453 /* Flag that will have to be added (if any). */
454 const char *flag_r;
252b5132 455
886a2506
NC		 456 /* Amount of operands. */
457 unsigned operand_cnt;
252b5132 458
886a2506
NC		 459 /* Array of operand operations. */
460 struct arc_operand_operation operand[6];
461};
252b5132 462
886a2506
NC		 463extern const struct arc_pseudo_insn arc_pseudo_insns[];
464extern const unsigned arc_num_pseudo_insn;
252b5132 465
886a2506
NC		 466/* Structure for AUXILIARY registers. */
467struct arc_aux_reg
468{
469 /* Register address. */
470 int address;
252b5132 471
f36e33da
CZ		 472 /* One bit flags for the opcode. These are primarily used to
473 indicate specific processors and environments support the
474 instructions. */
475 unsigned cpu;
476
8ddf6b2a
CZ		 477 /* AUX register subclass. */
478 insn_subclass_t subclass;
479
480 /* Register name. */
886a2506
NC		 481 const char *name;
482
483 /* Size of the string. */
484 size_t length;
485};
486
487extern const struct arc_aux_reg arc_aux_regs[];
488extern const unsigned arc_num_aux_regs;
489
4670103e
CZ		 490extern const struct arc_opcode arc_relax_opcodes[];
491extern const unsigned arc_num_relax_opcodes;
492
4b0c052e
AB		 493/* Macro used for generating one class of NPS instructions. */
494#define NPS_CMEM_HIGH_VALUE 0x57f0
495
f2dd8838
CZ		 496/* Macros to help generating regular pattern instructions. */
497#define FIELDA(word) (word & 0x3F)
498#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
499#define FIELDC(word) ((word & 0x3F) << 6)
500#define FIELDF (0x01 << 15)
501#define FIELDQ (0x1F)
502
503#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
504#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
505#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
506
507#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
508#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
509#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
510#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
511#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
512#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
513#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
514#define INSN3OP_0LL(MOP,SOP) \
515 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
516#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
517#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
518#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
519#define INSN3OP_0LU(MOP,SOP) \
520 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
521#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
522#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
523#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
524#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
525#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
526#define INSN3OP_C0LL(MOP,SOP) \
527 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
528#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
529#define INSN3OP_C0LU(MOP,SOP) \
530 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
531
532#define MINSN3OP_ABC (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
533#define MINSN3OP_ALC (~(FIELDF | FIELDA (63) | FIELDC (63)))
534#define MINSN3OP_ABL (~(FIELDF | FIELDA (63) | FIELDB (63)))
535#define MINSN3OP_ALL (~(FIELDF | FIELDA (63)))
536#define MINSN3OP_0BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
537#define MINSN3OP_0LC (~(FIELDF | FIELDC (63)))
538#define MINSN3OP_0BL (~(FIELDF | FIELDB (63)))
539#define MINSN3OP_0LL (~(FIELDF))
540#define MINSN3OP_ABU (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
541#define MINSN3OP_ALU (~(FIELDF | FIELDA (63) | FIELDC (63)))
542#define MINSN3OP_0BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
543#define MINSN3OP_0LU (~(FIELDF | FIELDC (63)))
544#define MINSN3OP_BBS (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
545#define MINSN3OP_0LS (~(FIELDF | FIELDA (63) | FIELDC (63)))
546#define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
547#define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
548#define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
549#define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
550#define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
551#define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
552
553#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
554#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
555#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
556#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
557#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
558#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
559
560#define MINSN2OP_BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
561#define MINSN2OP_BL (~(FIELDF | FIELDB (63)))
562#define MINSN2OP_0C (~(FIELDF | FIELDC (63)))
563#define MINSN2OP_0L (~(FIELDF))
564#define MINSN2OP_BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
565#define MINSN2OP_0U (~(FIELDF | FIELDC (63)))
566
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CZ		 567/* Various constants used when defining an extension instruction. */
568#define ARC_SYNTAX_3OP (1 << 0)
569#define ARC_SYNTAX_2OP (1 << 1)
945e0f82
CZ		 570#define ARC_SYNTAX_1OP (1 << 2)
571#define ARC_SYNTAX_NOP (1 << 3)
572#define ARC_SYNTAX_MASK (0x0F)
573
574#define ARC_OP1_MUST_BE_IMM (1 << 0)
575#define ARC_OP1_IMM_IMPLIED (1 << 1)
b99747ae
CZ		 576
577#define ARC_SUFFIX_NONE (1 << 0)
578#define ARC_SUFFIX_COND (1 << 1)
579#define ARC_SUFFIX_FLAG (1 << 2)
580
f36e33da
CZ		 581#define ARC_REGISTER_READONLY (1 << 0)
582#define ARC_REGISTER_WRITEONLY (1 << 1)
583#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
b99747ae
CZ		 584
585/* Constants needed to initialize extension instructions. */
586extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
587extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
588extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
589extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
590
591extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
592extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
593extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
594extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
595extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
596extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
597extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
598extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
599extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
600extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
601extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
602extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
603
604extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
605extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
606extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
607
608extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
609extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
610extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
611
612extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
613extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
614extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
615extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
616extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
617extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
618
619extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
620extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
621extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
622extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
623
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CZ		 624extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
625extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
626extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
627
db18dbab
GM		 628/* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
629 Instruction Set Reference Manual v2.4 for a description of address types. */
630
631typedef enum
632{
633 /* Addresses in memory. */
634
635 /* Buffer descriptor. */
636 ARC_NPS400_ADDRTYPE_BD,
637
638 /* Job identifier. */
639 ARC_NPS400_ADDRTYPE_JID,
640
641 /* Linked Buffer Descriptor. */
642 ARC_NPS400_ADDRTYPE_LBD,
643
644 /* Multicast Buffer Descriptor. */
645 ARC_NPS400_ADDRTYPE_MBD,
646
647 /* Summarized Address. */
648 ARC_NPS400_ADDRTYPE_SD,
649
650 /* SMEM Security Context Local Memory. */
651 ARC_NPS400_ADDRTYPE_SM,
652
653 /* Extended Address. */
654 ARC_NPS400_ADDRTYPE_XA,
655
656 /* Extended Summarized Address. */
657 ARC_NPS400_ADDRTYPE_XD,
658
659 /* CMEM offset addresses. */
660
661 /* On-demand Counter Descriptor. */
662 ARC_NPS400_ADDRTYPE_CD,
663
664 /* CMEM Buffer Descriptor. */
665 ARC_NPS400_ADDRTYPE_CBD,
666
667 /* CMEM Job Identifier. */
668 ARC_NPS400_ADDRTYPE_CJID,
669
670 /* CMEM Linked Buffer Descriptor. */
671 ARC_NPS400_ADDRTYPE_CLBD,
672
673 /* CMEM Offset. */
674 ARC_NPS400_ADDRTYPE_CM,
675
676 /* CMEM Summarized Address. */
677 ARC_NPS400_ADDRTYPE_CSD,
678
679 /* CMEM Extended Address. */
680 ARC_NPS400_ADDRTYPE_CXA,
681
682 /* CMEM Extended Summarized Address. */
683 ARC_NPS400_ADDRTYPE_CXD
684
685} arc_nps_address_type;
686
687#define ARC_NUM_ADDRTYPES 16
688
6b477896
TS		 689#ifdef __cplusplus
690}
691#endif
692
886a2506 693#endif /* OPCODE_ARC_H */
GDB Binutils - Deliverables
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