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[ARC] Rename "class" named attributes.
[deliverable/binutils-gdb.git] / include / opcode / arc.h
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252b5132 1/* Opcode table for the ARC.
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132 5
0d2bcfaf
NC		 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
7 the GNU Binutils.
252b5132 8
0d2bcfaf
NC		 9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
e4e42b45 11 the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf 12 any later version.
252b5132 13
0d2bcfaf
NC		 14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf
NC		 17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
e4e42b45 20 along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8
NC		 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
886a2506
NC		 24#ifndef OPCODE_ARC_H
25#define OPCODE_ARC_H
26
4670103e 27#ifndef MAX_INSN_ARGS
537aefaf 28#define MAX_INSN_ARGS 8
4670103e
CZ		 29#endif
30
31#ifndef MAX_INSN_FLGS
886a2506 32#define MAX_INSN_FLGS 3
4670103e 33#endif
886a2506
NC		 34
35/* Instruction Class. */
36typedef enum
37 {
38 ARITH,
39 AUXREG,
40 BRANCH,
41 CONTROL,
42 DSP,
43 FLOAT,
44 INVALID,
45 JUMP,
46 KERNEL,
47 LOGICAL,
48 MEMORY,
e23e8ebe 49 BITOP,
c8f785f2
AB		 50 NET,
51 ACL,
886a2506
NC		 52 } insn_class_t;
53
54/* Instruction Subclass. */
55typedef enum
56 {
57 NONE,
58 CVT,
59 BTSCN,
60 CD1,
61 CD2,
62 DIV,
63 DP,
8ddf6b2a
CZ		 64 DPA,
65 DPX,
886a2506
NC		 66 MPY1E,
67 MPY6E,
68 MPY7E,
69 MPY8E,
70 MPY9E,
f2dd8838 71 QUARKSE,
886a2506
NC		 72 SHFT1,
73 SHFT2,
74 SWAP,
8ddf6b2a
CZ		 75 SP,
76 SPX
886a2506
NC		 77 } insn_subclass_t;
78
79/* Flags class. */
80typedef enum
81 {
f36e33da 82 F_CLASS_NONE = 0,
1ae8ab47
AB		 83
84 /* At most one flag from the set of flags can appear in the
85 instruction. */
f36e33da 86 F_CLASS_OPTIONAL = (1 << 0),
1ae8ab47
AB		 87
88 /* Exactly one from from the set of flags must appear in the
89 instruction. */
f36e33da
CZ		 90 F_CLASS_REQUIRED = (1 << 1),
91
92 /* The conditional code can be extended over the standard variants
93 via .extCondCode pseudo-op. */
94 F_CLASS_EXTEND = (1 << 2)
886a2506
NC		 95 } flag_class_t;
96
97/* The opcode table is an array of struct arc_opcode. */
98struct arc_opcode
99{
100 /* The opcode name. */
101 const char *name;
102
103 /* The opcode itself. Those bits which will be filled in with
104 operands are zeroes. */
105 unsigned opcode;
106
107 /* The opcode mask. This is used by the disassembler. This is a
108 mask containing ones indicating those bits which must match the
109 opcode field, and zeroes indicating those bits which need not
110 match (and are presumably filled in by operands). */
111 unsigned mask;
112
113 /* One bit flags for the opcode. These are primarily used to
114 indicate specific processors and environments support the
115 instructions. The defined values are listed below. */
116 unsigned cpu;
117
118 /* The instruction class. This is used by gdb. */
c810e0b8 119 insn_class_t insn_class;
886a2506
NC		 120
121 /* The instruction subclass. */
122 insn_subclass_t subclass;
123
124 /* An array of operand codes. Each code is an index into the
125 operand table. They appear in the order which the operands must
126 appear in assembly code, and are terminated by a zero. */
127 unsigned char operands[MAX_INSN_ARGS + 1];
128
129 /* An array of flag codes. Each code is an index into the flag
130 table. They appear in the order which the flags must appear in
131 assembly code, and are terminated by a zero. */
132 unsigned char flags[MAX_INSN_FLGS + 1];
133};
252b5132 134
886a2506
NC		 135/* The table itself is sorted by major opcode number, and is otherwise
136 in the order in which the disassembler should consider
137 instructions. */
138extern const struct arc_opcode arc_opcodes[];
886a2506
NC		 139
140/* CPU Availability. */
f36e33da 141#define ARC_OPCODE_NONE 0x0000
886a2506
NC		 142#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
143#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
144#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
145#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
8699fc3e 146#define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */
886a2506 147
f36e33da
CZ		 148/* CPU combi. */
149#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
150 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
151#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
152
886a2506
NC		 153/* CPU extensions. */
154#define ARC_EA 0x0001
155#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
156#define ARC_LLOCK 0x0002
157#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
158#define ARC_MPY 0x0004
159#define ARC_MULT 0x0004
160
161/* Floating point support. */
162#define ARC_DPFP 0x0010
163#define ARC_SPFP 0x0020
164#define ARC_FPU 0x0030
8ddf6b2a 165#define ARC_FPUDA 0x0040
886a2506
NC		 166
167/* NORM & SWAP. */
168#define ARC_SWAP 0x0100
169#define ARC_NORM 0x0200
170#define ARC_BSCAN 0x0200
171
172/* A7 specific. */
173#define ARC_UIX 0x1000
174#define ARC_TSTAMP 0x1000
175
176/* A6 specific. */
177#define ARC_VBFDW 0x1000
178#define ARC_BARREL 0x1000
179#define ARC_DSPA 0x1000
180
181/* EM specific. */
182#define ARC_SHIFT 0x1000
183
184/* V2 specific. */
185#define ARC_INTR 0x1000
186#define ARC_DIV 0x1000
187
188/* V1 specific. */
189#define ARC_XMAC 0x1000
190#define ARC_CRC 0x1000
191
886a2506
NC		 192/* A macro to check for short instructions. */
193#define ARC_SHORT(mask) \
194 (((mask) & 0xFFFF0000) ? 0 : 1)
195
196/* The operands table is an array of struct arc_operand. */
197struct arc_operand
198{
199 /* The number of bits in the operand. */
200 unsigned int bits;
201
202 /* How far the operand is left shifted in the instruction. */
203 unsigned int shift;
204
205 /* The default relocation type for this operand. */
206 signed int default_reloc;
207
208 /* One bit syntax flags. */
209 unsigned int flags;
210
211 /* Insertion function. This is used by the assembler. To insert an
212 operand value into an instruction, check this field.
213
214 If it is NULL, execute
215 i |= (op & ((1 << o->bits) - 1)) << o->shift;
216 (i is the instruction which we are filling in, o is a pointer to
217 this structure, and op is the opcode value; this assumes twos
218 complement arithmetic).
219
220 If this field is not NULL, then simply call it with the
221 instruction and the operand value. It will return the new value
222 of the instruction. If the ERRMSG argument is not NULL, then if
223 the operand value is illegal, *ERRMSG will be set to a warning
224 string (the operand will be inserted in any case). If the
225 operand value is legal, *ERRMSG will be unchanged (most operands
226 can accept any value). */
227 unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
228
229 /* Extraction function. This is used by the disassembler. To
230 extract this operand type from an instruction, check this field.
231
232 If it is NULL, compute
233 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
234 if ((o->flags & ARC_OPERAND_SIGNED) != 0
235 && (op & (1 << (o->bits - 1))) != 0)
236 op -= 1 << o->bits;
237 (i is the instruction, o is a pointer to this structure, and op
238 is the result; this assumes twos complement arithmetic).
239
240 If this field is not NULL, then simply call it with the
241 instruction value. It will return the value of the operand. If
242 the INVALID argument is not NULL, *INVALID will be set to
243 TRUE if this operand type can not actually be extracted from
244 this operand (i.e., the instruction does not match). If the
245 operand is valid, *INVALID will not be changed. */
246 int (*extract) (unsigned instruction, bfd_boolean *invalid);
247};
0d2bcfaf 248
886a2506
NC		 249/* Elements in the table are retrieved by indexing with values from
250 the operands field of the arc_opcodes table. */
251extern const struct arc_operand arc_operands[];
252extern const unsigned arc_num_operands;
253extern const unsigned arc_Toperand;
254extern const unsigned arc_NToperand;
252b5132 255
886a2506 256/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf 257
886a2506
NC		 258/* This operand does not actually exist in the assembler input. This
259 is used to support extended mnemonics, for which two operands fields
260 are identical. The assembler should call the insert function with
261 any op value. The disassembler should call the extract function,
262 ignore the return value, and check the value placed in the invalid
263 argument. */
264#define ARC_OPERAND_FAKE 0x0001
252b5132 265
886a2506
NC		 266/* This operand names an integer register. */
267#define ARC_OPERAND_IR 0x0002
0d2bcfaf 268
886a2506
NC		 269/* This operand takes signed values. */
270#define ARC_OPERAND_SIGNED 0x0004
252b5132 271
886a2506
NC		 272/* This operand takes unsigned values. This exists primarily so that
273 a flags value of 0 can be treated as end-of-arguments. */
274#define ARC_OPERAND_UNSIGNED 0x0008
252b5132 275
886a2506
NC		 276/* This operand takes long immediate values. */
277#define ARC_OPERAND_LIMM 0x0010
252b5132 278
886a2506
NC		 279/* This operand is identical like the previous one. */
280#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf 281
886a2506
NC		 282/* This operand is PC relative. Used for internal relocs. */
283#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf 284
886a2506
NC		 285/* This operand is truncated. The truncation is done accordingly to
286 operand alignment attribute. */
287#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf 288
886a2506
NC		 289/* This operand is 16bit aligned. */
290#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf 291
886a2506
NC		 292/* This operand is 32bit aligned. */
293#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf 294
886a2506
NC		 295/* This operand can be ignored by matching process if it is not
296 present. */
297#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf 298
886a2506
NC		 299/* Don't check the range when matching. */
300#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf 301
886a2506
NC		 302/* Mark the braket possition. */
303#define ARC_OPERAND_BRAKET 0x1000
252b5132 304
886a2506
NC		 305/* Mask for selecting the type for typecheck purposes. */
306#define ARC_OPERAND_TYPECHECK_MASK \
307 (ARC_OPERAND_IR | \
308 ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | \
309 ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
252b5132 310
886a2506
NC		 311/* The flags structure. */
312struct arc_flag_operand
313{
314 /* The flag name. */
315 const char *name;
0d2bcfaf 316
886a2506
NC		 317 /* The flag code. */
318 unsigned code;
252b5132 319
886a2506
NC		 320 /* The number of bits in the operand. */
321 unsigned int bits;
252b5132 322
886a2506
NC		 323 /* How far the operand is left shifted in the instruction. */
324 unsigned int shift;
252b5132 325
886a2506
NC		 326 /* Available for disassembler. */
327 unsigned char favail;
84037f8c
KD		 328};
329
886a2506
NC		 330/* The flag operands table. */
331extern const struct arc_flag_operand arc_flag_operands[];
332extern const unsigned arc_num_flag_operands;
0d2bcfaf 333
886a2506
NC		 334/* The flag's class structure. */
335struct arc_flag_class
336{
337 /* Flag class. */
c810e0b8 338 flag_class_t flag_class;
252b5132 339
886a2506
NC		 340 /* List of valid flags (codes). */
341 unsigned flags[256];
342};
252b5132 343
886a2506 344extern const struct arc_flag_class arc_flag_classes[];
252b5132 345
886a2506
NC		 346/* Structure for special cases. */
347struct arc_flag_special
348{
349 /* Name of special case instruction. */
350 const char *name;
252b5132 351
886a2506
NC		 352 /* List of flags applicable for special case instruction. */
353 unsigned flags[32];
354};
252b5132 355
886a2506
NC		 356extern const struct arc_flag_special arc_flag_special_cases[];
357extern const unsigned arc_num_flag_special;
358
359/* Relocation equivalence structure. */
360struct arc_reloc_equiv_tab
361{
362 const char * name; /* String to lookup. */
363 const char * mnemonic; /* Extra matching condition. */
24b368f8 364 unsigned flags[32]; /* Extra matching condition. */
886a2506
NC		 365 signed int oldreloc; /* Old relocation. */
366 signed int newreloc; /* New relocation. */
367};
252b5132 368
886a2506
NC		 369extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
370extern const unsigned arc_num_equiv_tab;
252b5132 371
886a2506
NC		 372/* Structure for operand operations for pseudo/alias instructions. */
373struct arc_operand_operation
374{
375 /* The index for operand from operand array. */
376 unsigned operand_idx;
252b5132 377
886a2506
NC		 378 /* Defines if it needs the operand inserted by the assembler or
379 whether this operand comes from the pseudo instruction's
380 operands. */
381 unsigned char needs_insert;
252b5132 382
886a2506
NC		 383 /* Count we have to add to the operand. Use negative number to
384 subtract from the operand. Also use this number to add to 0 if
385 the operand needs to be inserted (i.e. needs_insert == 1). */
386 int count;
252b5132 387
886a2506
NC		 388 /* Index of the operand to swap with. To be done AFTER applying
389 inc_count. */
390 unsigned swap_operand_idx;
252b5132
RH		 391};
392
886a2506
NC		 393/* Structure for pseudo/alias instructions. */
394struct arc_pseudo_insn
395{
396 /* Mnemonic for pseudo/alias insn. */
397 const char *mnemonic_p;
252b5132 398
886a2506
NC		 399 /* Mnemonic for real instruction. */
400 const char *mnemonic_r;
252b5132 401
886a2506
NC		 402 /* Flag that will have to be added (if any). */
403 const char *flag_r;
252b5132 404
886a2506
NC		 405 /* Amount of operands. */
406 unsigned operand_cnt;
252b5132 407
886a2506
NC		 408 /* Array of operand operations. */
409 struct arc_operand_operation operand[6];
410};
252b5132 411
886a2506
NC		 412extern const struct arc_pseudo_insn arc_pseudo_insns[];
413extern const unsigned arc_num_pseudo_insn;
252b5132 414
886a2506
NC		 415/* Structure for AUXILIARY registers. */
416struct arc_aux_reg
417{
418 /* Register address. */
419 int address;
252b5132 420
f36e33da
CZ		 421 /* One bit flags for the opcode. These are primarily used to
422 indicate specific processors and environments support the
423 instructions. */
424 unsigned cpu;
425
8ddf6b2a
CZ		 426 /* AUX register subclass. */
427 insn_subclass_t subclass;
428
429 /* Register name. */
886a2506
NC		 430 const char *name;
431
432 /* Size of the string. */
433 size_t length;
434};
435
436extern const struct arc_aux_reg arc_aux_regs[];
437extern const unsigned arc_num_aux_regs;
438
4670103e
CZ		 439extern const struct arc_opcode arc_relax_opcodes[];
440extern const unsigned arc_num_relax_opcodes;
441
4b0c052e
AB		 442/* Macro used for generating one class of NPS instructions. */
443#define NPS_CMEM_HIGH_VALUE 0x57f0
444
f2dd8838
CZ		 445/* Macros to help generating regular pattern instructions. */
446#define FIELDA(word) (word & 0x3F)
447#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
448#define FIELDC(word) ((word & 0x3F) << 6)
449#define FIELDF (0x01 << 15)
450#define FIELDQ (0x1F)
451
452#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
453#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
454#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
455
456#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
457#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
458#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
459#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
460#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
461#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
462#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
463#define INSN3OP_0LL(MOP,SOP) \
464 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
465#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
466#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
467#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
468#define INSN3OP_0LU(MOP,SOP) \
469 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
470#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
471#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
472#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
473#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
474#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
475#define INSN3OP_C0LL(MOP,SOP) \
476 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
477#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
478#define INSN3OP_C0LU(MOP,SOP) \
479 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
480
481#define MINSN3OP_ABC (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
482#define MINSN3OP_ALC (~(FIELDF | FIELDA (63) | FIELDC (63)))
483#define MINSN3OP_ABL (~(FIELDF | FIELDA (63) | FIELDB (63)))
484#define MINSN3OP_ALL (~(FIELDF | FIELDA (63)))
485#define MINSN3OP_0BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
486#define MINSN3OP_0LC (~(FIELDF | FIELDC (63)))
487#define MINSN3OP_0BL (~(FIELDF | FIELDB (63)))
488#define MINSN3OP_0LL (~(FIELDF))
489#define MINSN3OP_ABU (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
490#define MINSN3OP_ALU (~(FIELDF | FIELDA (63) | FIELDC (63)))
491#define MINSN3OP_0BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
492#define MINSN3OP_0LU (~(FIELDF | FIELDC (63)))
493#define MINSN3OP_BBS (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
494#define MINSN3OP_0LS (~(FIELDF | FIELDA (63) | FIELDC (63)))
495#define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
496#define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
497#define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
498#define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
499#define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
500#define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
501
502#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
503#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
504#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
505#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
506#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
507#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
508
509#define MINSN2OP_BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
510#define MINSN2OP_BL (~(FIELDF | FIELDB (63)))
511#define MINSN2OP_0C (~(FIELDF | FIELDC (63)))
512#define MINSN2OP_0L (~(FIELDF))
513#define MINSN2OP_BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
514#define MINSN2OP_0U (~(FIELDF | FIELDC (63)))
515
b99747ae
CZ		 516/* Various constants used when defining an extension instruction. */
517#define ARC_SYNTAX_3OP (1 << 0)
518#define ARC_SYNTAX_2OP (1 << 1)
945e0f82
CZ		 519#define ARC_SYNTAX_1OP (1 << 2)
520#define ARC_SYNTAX_NOP (1 << 3)
521#define ARC_SYNTAX_MASK (0x0F)
522
523#define ARC_OP1_MUST_BE_IMM (1 << 0)
524#define ARC_OP1_IMM_IMPLIED (1 << 1)
b99747ae
CZ		 525
526#define ARC_SUFFIX_NONE (1 << 0)
527#define ARC_SUFFIX_COND (1 << 1)
528#define ARC_SUFFIX_FLAG (1 << 2)
529
f36e33da
CZ		 530#define ARC_REGISTER_READONLY (1 << 0)
531#define ARC_REGISTER_WRITEONLY (1 << 1)
532#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
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CZ		 533
534/* Constants needed to initialize extension instructions. */
535extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
536extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
537extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
538extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
539
540extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
541extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
542extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
543extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
544extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
545extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
546extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
547extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
548extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
549extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
550extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
551extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
552
553extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
554extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
555extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
556
557extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
558extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
559extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
560
561extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
562extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
563extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
564extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
565extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
566extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
567
568extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
569extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
570extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
571extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
572
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CZ		 573extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
574extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
575extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
576
886a2506 577#endif /* OPCODE_ARC_H */
GDB Binutils - Deliverables
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