[deliverable/binutils-gdb.git] / include / opcode / riscv.h

/* riscv.h.  RISC-V opcode list for GDB, the GNU debugger.
   Copyright (C) 2011-2018 Free Software Foundation, Inc.
   Contributed by Andrew Waterman

   This file is part of GDB, GAS, and the GNU binutils.

   GDB, GAS, and the GNU binutils are free software; you can redistribute
   them and/or modify them under the terms of the GNU General Public
   License as published by the Free Software Foundation; either version
   3, or (at your option) any later version.

   GDB, GAS, and the GNU binutils are distributed in the hope that they
   will be useful, but WITHOUT ANY WARRANTY; without even the implied
   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
   the GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; see the file COPYING3. If not,
   see <http://www.gnu.org/licenses/>.  */

#ifndef _RISCV_H_
#define _RISCV_H_

#include "riscv-opc.h"
#include <stdlib.h>
#include <stdint.h>

typedef uint64_t insn_t;

static inline unsigned int riscv_insn_length (insn_t insn)
{
  if ((insn & 0x3) != 0x3) /* RVC.  */
    return 2;
  if ((insn & 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space.  */
    return 4;
  if ((insn & 0x3f) == 0x1f) /* 48-bit extensions.  */
    return 6;
  if ((insn & 0x7f) == 0x3f) /* 64-bit extensions.  */
    return 8;
  /* Longer instructions not supported at the moment.  */
  return 2;
}

static const char * const riscv_rm[8] =
{
  "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
};

static const char * const riscv_pred_succ[16] =
{
  0,   "w",  "r",  "rw",  "o",  "ow",  "or",  "orw",
  "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
};

#define RVC_JUMP_BITS 11
#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)

#define RVC_BRANCH_BITS 8
#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)

#define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))
#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))

#define EXTRACT_ITYPE_IMM(x) \
  (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
#define EXTRACT_STYPE_IMM(x) \
  (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
#define EXTRACT_SBTYPE_IMM(x) \
  ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
#define EXTRACT_UTYPE_IMM(x) \
  ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
#define EXTRACT_UJTYPE_IMM(x) \
  ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
#define EXTRACT_RVC_IMM(x) \
  (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
#define EXTRACT_RVC_LUI_IMM(x) \
  (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS)
#define EXTRACT_RVC_SIMM3(x) \
  (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2))
#define EXTRACT_RVC_UIMM8(x) \
  (RV_X(x, 5, 8))
#define EXTRACT_RVC_ADDI4SPN_IMM(x) \
  ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
#define EXTRACT_RVC_ADDI16SP_IMM(x) \
  ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
#define EXTRACT_RVC_LW_IMM(x) \
  ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
#define EXTRACT_RVC_LD_IMM(x) \
  ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
#define EXTRACT_RVC_LWSP_IMM(x) \
  ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
#define EXTRACT_RVC_LDSP_IMM(x) \
  ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
#define EXTRACT_RVC_SWSP_IMM(x) \
  ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
#define EXTRACT_RVC_SDSP_IMM(x) \
  ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
#define EXTRACT_RVC_B_IMM(x) \
  ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
#define EXTRACT_RVC_J_IMM(x) \
  ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))

#define ENCODE_ITYPE_IMM(x) \
  (RV_X(x, 0, 12) << 20)
#define ENCODE_STYPE_IMM(x) \
  ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
#define ENCODE_SBTYPE_IMM(x) \
  ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
#define ENCODE_UTYPE_IMM(x) \
  (RV_X(x, 12, 20) << 12)
#define ENCODE_UJTYPE_IMM(x) \
  ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
#define ENCODE_RVC_IMM(x) \
  ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
#define ENCODE_RVC_LUI_IMM(x) \
  ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS)
#define ENCODE_RVC_SIMM3(x) \
  (RV_X(x, 0, 3) << 10)
#define ENCODE_RVC_UIMM8(x) \
  (RV_X(x, 0, 8) << 5)
#define ENCODE_RVC_ADDI4SPN_IMM(x) \
  ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
#define ENCODE_RVC_ADDI16SP_IMM(x) \
  ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
#define ENCODE_RVC_LW_IMM(x) \
  ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
#define ENCODE_RVC_LD_IMM(x) \
  ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
#define ENCODE_RVC_LWSP_IMM(x) \
  ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
#define ENCODE_RVC_LDSP_IMM(x) \
  ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
#define ENCODE_RVC_SWSP_IMM(x) \
  ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
#define ENCODE_RVC_SDSP_IMM(x) \
  ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
#define ENCODE_RVC_B_IMM(x) \
  ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
#define ENCODE_RVC_J_IMM(x) \
  ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))

#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
#define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
#define VALID_RVC_UIMM8(x) (EXTRACT_RVC_UIMM8(ENCODE_RVC_UIMM8(x)) == (x))
#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
#define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x))
#define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x))
#define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x))
#define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x))
#define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x))
#define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
#define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
#define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))

#define RISCV_RTYPE(insn, rd, rs1, rs2) \
  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
#define RISCV_ITYPE(insn, rd, rs1, imm) \
  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
#define RISCV_STYPE(insn, rs1, rs2, imm) \
  ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
#define RISCV_SBTYPE(insn, rs1, rs2, target) \
  ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target))
#define RISCV_UTYPE(insn, rd, bigimm) \
  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
#define RISCV_UJTYPE(insn, rd, target) \
  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target))

#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
#define RVC_NOP MATCH_C_ADDI

#define RISCV_CONST_HIGH_PART(VALUE) \
  (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))

#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
#define RISCV_JUMP_ALIGN_BITS 1
#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)

#define RISCV_IMM_BITS 12
#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
#define RISCV_RVC_IMM_REACH (1LL << 6)
#define RISCV_BRANCH_BITS RISCV_IMM_BITS
#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)

/* RV fields.  */

#define OP_MASK_OP		0x7f
#define OP_SH_OP		0
#define OP_MASK_RS2		0x1f
#define OP_SH_RS2		20
#define OP_MASK_RS1		0x1f
#define OP_SH_RS1		15
#define OP_MASK_RS3		0x1f
#define OP_SH_RS3		27
#define OP_MASK_RD		0x1f
#define OP_SH_RD		7
#define OP_MASK_SHAMT		0x3f
#define OP_SH_SHAMT		20
#define OP_MASK_SHAMTW		0x1f
#define OP_SH_SHAMTW		20
#define OP_MASK_RM		0x7
#define OP_SH_RM		12
#define OP_MASK_PRED		0xf
#define OP_SH_PRED		24
#define OP_MASK_SUCC		0xf
#define OP_SH_SUCC		20
#define OP_MASK_AQ		0x1
#define OP_SH_AQ		26
#define OP_MASK_RL		0x1
#define OP_SH_RL		25

#define OP_MASK_CUSTOM_IMM	0x7f
#define OP_SH_CUSTOM_IMM	25
#define OP_MASK_CSR		0xfff
#define OP_SH_CSR		20

#define OP_MASK_FUNCT3         0x7
#define OP_SH_FUNCT3           12
#define OP_MASK_FUNCT7         0x7f
#define OP_SH_FUNCT7           25
#define OP_MASK_FUNCT2         0x3
#define OP_SH_FUNCT2           25

/* RVC fields.  */

#define OP_MASK_OP2            0x3
#define OP_SH_OP2              0

#define OP_MASK_CRS2 0x1f
#define OP_SH_CRS2 2
#define OP_MASK_CRS1S 0x7
#define OP_SH_CRS1S 7
#define OP_MASK_CRS2S 0x7
#define OP_SH_CRS2S 2

#define OP_MASK_CFUNCT4                0xf
#define OP_SH_CFUNCT4          12
#define OP_MASK_CFUNCT3                0x7
#define OP_SH_CFUNCT3          13

/* ABI names for selected x-registers.  */

#define X_RA 1
#define X_SP 2
#define X_GP 3
#define X_TP 4
#define X_T0 5
#define X_T1 6
#define X_T2 7
#define X_T3 28

#define NGPR 32
#define NFPR 32

/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
   VALUE << SHIFT.  VALUE is evaluated exactly once.  */
#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
  (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
	      | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))

/* Extract bits MASK << SHIFT from STRUCT and shift them right
   SHIFT places.  */
#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
  (((STRUCT) >> (SHIFT)) & (MASK))

/* Extract the operand given by FIELD from integer INSN.  */
#define EXTRACT_OPERAND(FIELD, INSN) \
  EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)

/* This structure holds information for a particular instruction.  */

struct riscv_opcode
{
  /* The name of the instruction.  */
  const char *name;
  /* The ISA subset name (I, M, A, F, D, Xextension).  */
  const char *subset;
  /* A string describing the arguments for this instruction.  */
  const char *args;
  /* The basic opcode for the instruction.  When assembling, this
     opcode is modified by the arguments to produce the actual opcode
     that is used.  If pinfo is INSN_MACRO, then this is 0.  */
  insn_t match;
  /* If pinfo is not INSN_MACRO, then this is a bit mask for the
     relevant portions of the opcode when disassembling.  If the
     actual opcode anded with the match field equals the opcode field,
     then we have found the correct instruction.  If pinfo is
     INSN_MACRO, then this field is the macro identifier.  */
  insn_t mask;
  /* A function to determine if a word corresponds to this instruction.
     Usually, this computes ((word & mask) == match).  */
  int (*match_func) (const struct riscv_opcode *op, insn_t word);
  /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
     of bits describing the instruction, notably any relevant hazard
     information.  */
  unsigned long pinfo;
};

/* Instruction is a simple alias (e.g. "mv" for "addi").  */
#define	INSN_ALIAS		0x00000001
/* Instruction is actually a macro.  It should be ignored by the
   disassembler, and requires special treatment by the assembler.  */
#define INSN_MACRO		0xffffffff

/* This is a list of macro expanded instructions.

   _I appended means immediate
   _A appended means address
   _AB appended means address with base register
   _D appended means 64 bit floating point constant
   _S appended means 32 bit floating point constant.  */

enum
{
  M_LA,
  M_LLA,
  M_LA_TLS_GD,
  M_LA_TLS_IE,
  M_LB,
  M_LBU,
  M_LH,
  M_LHU,
  M_LW,
  M_LWU,
  M_LD,
  M_SB,
  M_SH,
  M_SW,
  M_SD,
  M_FLW,
  M_FLD,
  M_FLQ,
  M_FSW,
  M_FSD,
  M_FSQ,
  M_CALL,
  M_J,
  M_LI,
  M_NUM_MACROS
};


extern const char * const riscv_gpr_names_numeric[NGPR];
extern const char * const riscv_gpr_names_abi[NGPR];
extern const char * const riscv_fpr_names_numeric[NFPR];
extern const char * const riscv_fpr_names_abi[NFPR];

extern const struct riscv_opcode riscv_opcodes[];
extern const struct riscv_opcode riscv_insn_types[];

#endif /* _RISCV_H_ */
Commit	Line	Data
e23eba97	1	/* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
219d1afa	2	Copyright (C) 2011-2018 Free Software Foundation, Inc.
e23eba97 NC	3	Contributed by Andrew Waterman
	4
	5	This file is part of GDB, GAS, and the GNU binutils.
	6
	7	GDB, GAS, and the GNU binutils are free software; you can redistribute
	8	them and/or modify them under the terms of the GNU General Public
	9	License as published by the Free Software Foundation; either version
	10	3, or (at your option) any later version.
	11
	12	GDB, GAS, and the GNU binutils are distributed in the hope that they
	13	will be useful, but WITHOUT ANY WARRANTY; without even the implied
	14	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	15	the GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; see the file COPYING3. If not,
	19	see <http://www.gnu.org/licenses/>. */
	20
	21	#ifndef _RISCV_H_
	22	#define _RISCV_H_
	23
	24	#include "riscv-opc.h"
	25	#include <stdlib.h>
	26	#include <stdint.h>
	27
	28	typedef uint64_t insn_t;
	29
	30	static inline unsigned int riscv_insn_length (insn_t insn)
	31	{
	32	if ((insn & 0x3) != 0x3) /* RVC. */
	33	return 2;
	34	if ((insn & 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space. */
	35	return 4;
	36	if ((insn & 0x3f) == 0x1f) /* 48-bit extensions. */
	37	return 6;
	38	if ((insn & 0x7f) == 0x3f) /* 64-bit extensions. */
	39	return 8;
	40	/* Longer instructions not supported at the moment. */
	41	return 2;
	42	}
	43
	44	static const char * const riscv_rm[8] =
	45	{
	46	"rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
	47	};
	48
	49	static const char * const riscv_pred_succ[16] =
	50	{
	51	0, "w", "r", "rw", "o", "ow", "or", "orw",
	52	"i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
	53	};
	54
	55	#define RVC_JUMP_BITS 11
	56	#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
	57
	58	#define RVC_BRANCH_BITS 8
	59	#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
	60
	61	#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
	62	#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
	63
	64	#define EXTRACT_ITYPE_IMM(x) \
	65	(RV_X(x, 20, 12) \| (RV_IMM_SIGN(x) << 12))
	66	#define EXTRACT_STYPE_IMM(x) \
67	(RV_X(x, 7, 5) \| (RV_X(x, 25, 7) << 5) \| (RV_IMM_SIGN(x) << 12))
68	#define EXTRACT_SBTYPE_IMM(x) \
69	((RV_X(x, 8, 4) << 1) \| (RV_X(x, 25, 6) << 5) \| (RV_X(x, 7, 1) << 11) \| (RV_IMM_SIGN(x) << 12))
70	#define EXTRACT_UTYPE_IMM(x) \
71	((RV_X(x, 12, 20) << 12) \| (RV_IMM_SIGN(x) << 32))
72	#define EXTRACT_UJTYPE_IMM(x) \
73	((RV_X(x, 21, 10) << 1) \| (RV_X(x, 20, 1) << 11) \| (RV_X(x, 12, 8) << 12) \| (RV_IMM_SIGN(x) << 20))
74	#define EXTRACT_RVC_IMM(x) \
75	(RV_X(x, 2, 5) \| (-RV_X(x, 12, 1) << 5))
76	#define EXTRACT_RVC_LUI_IMM(x) \
77	(EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS)
78	#define EXTRACT_RVC_SIMM3(x) \
79	(RV_X(x, 10, 2) \| (-RV_X(x, 12, 1) << 2))
0e35537d JW	80	#define EXTRACT_RVC_UIMM8(x) \
0e35537d JW	81	(RV_X(x, 5, 8))
e23eba97 NC	82	#define EXTRACT_RVC_ADDI4SPN_IMM(x) \
	83	((RV_X(x, 6, 1) << 2) \| (RV_X(x, 5, 1) << 3) \| (RV_X(x, 11, 2) << 4) \| (RV_X(x, 7, 4) << 6))
	84	#define EXTRACT_RVC_ADDI16SP_IMM(x) \
	85	((RV_X(x, 6, 1) << 4) \| (RV_X(x, 2, 1) << 5) \| (RV_X(x, 5, 1) << 6) \| (RV_X(x, 3, 2) << 7) \| (-RV_X(x, 12, 1) << 9))
	86	#define EXTRACT_RVC_LW_IMM(x) \
	87	((RV_X(x, 6, 1) << 2) \| (RV_X(x, 10, 3) << 3) \| (RV_X(x, 5, 1) << 6))
	88	#define EXTRACT_RVC_LD_IMM(x) \
	89	((RV_X(x, 10, 3) << 3) \| (RV_X(x, 5, 2) << 6))
	90	#define EXTRACT_RVC_LWSP_IMM(x) \
	91	((RV_X(x, 4, 3) << 2) \| (RV_X(x, 12, 1) << 5) \| (RV_X(x, 2, 2) << 6))
	92	#define EXTRACT_RVC_LDSP_IMM(x) \
	93	((RV_X(x, 5, 2) << 3) \| (RV_X(x, 12, 1) << 5) \| (RV_X(x, 2, 3) << 6))
	94	#define EXTRACT_RVC_SWSP_IMM(x) \
	95	((RV_X(x, 9, 4) << 2) \| (RV_X(x, 7, 2) << 6))
	96	#define EXTRACT_RVC_SDSP_IMM(x) \
	97	((RV_X(x, 10, 3) << 3) \| (RV_X(x, 7, 3) << 6))
	98	#define EXTRACT_RVC_B_IMM(x) \
	99	((RV_X(x, 3, 2) << 1) \| (RV_X(x, 10, 2) << 3) \| (RV_X(x, 2, 1) << 5) \| (RV_X(x, 5, 2) << 6) \| (-RV_X(x, 12, 1) << 8))
	100	#define EXTRACT_RVC_J_IMM(x) \
	101	((RV_X(x, 3, 3) << 1) \| (RV_X(x, 11, 1) << 4) \| (RV_X(x, 2, 1) << 5) \| (RV_X(x, 7, 1) << 6) \| (RV_X(x, 6, 1) << 7) \| (RV_X(x, 9, 2) << 8) \| (RV_X(x, 8, 1) << 10) \| (-RV_X(x, 12, 1) << 11))
	102
	103	#define ENCODE_ITYPE_IMM(x) \
	104	(RV_X(x, 0, 12) << 20)
	105	#define ENCODE_STYPE_IMM(x) \
	106	((RV_X(x, 0, 5) << 7) \| (RV_X(x, 5, 7) << 25))
	107	#define ENCODE_SBTYPE_IMM(x) \
	108	((RV_X(x, 1, 4) << 8) \| (RV_X(x, 5, 6) << 25) \| (RV_X(x, 11, 1) << 7) \| (RV_X(x, 12, 1) << 31))
	109	#define ENCODE_UTYPE_IMM(x) \
	110	(RV_X(x, 12, 20) << 12)
	111	#define ENCODE_UJTYPE_IMM(x) \
	112	((RV_X(x, 1, 10) << 21) \| (RV_X(x, 11, 1) << 20) \| (RV_X(x, 12, 8) << 12) \| (RV_X(x, 20, 1) << 31))
	113	#define ENCODE_RVC_IMM(x) \
	114	((RV_X(x, 0, 5) << 2) \| (RV_X(x, 5, 1) << 12))
	115	#define ENCODE_RVC_LUI_IMM(x) \
	116	ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS)
	117	#define ENCODE_RVC_SIMM3(x) \
	118	(RV_X(x, 0, 3) << 10)
0e35537d JW	119	#define ENCODE_RVC_UIMM8(x) \
0e35537d JW	120	(RV_X(x, 0, 8) << 5)
e23eba97 NC	121	#define ENCODE_RVC_ADDI4SPN_IMM(x) \
	122	((RV_X(x, 2, 1) << 6) \| (RV_X(x, 3, 1) << 5) \| (RV_X(x, 4, 2) << 11) \| (RV_X(x, 6, 4) << 7))
	123	#define ENCODE_RVC_ADDI16SP_IMM(x) \
	124	((RV_X(x, 4, 1) << 6) \| (RV_X(x, 5, 1) << 2) \| (RV_X(x, 6, 1) << 5) \| (RV_X(x, 7, 2) << 3) \| (RV_X(x, 9, 1) << 12))
	125	#define ENCODE_RVC_LW_IMM(x) \
	126	((RV_X(x, 2, 1) << 6) \| (RV_X(x, 3, 3) << 10) \| (RV_X(x, 6, 1) << 5))
	127	#define ENCODE_RVC_LD_IMM(x) \
	128	((RV_X(x, 3, 3) << 10) \| (RV_X(x, 6, 2) << 5))
	129	#define ENCODE_RVC_LWSP_IMM(x) \
	130	((RV_X(x, 2, 3) << 4) \| (RV_X(x, 5, 1) << 12) \| (RV_X(x, 6, 2) << 2))
	131	#define ENCODE_RVC_LDSP_IMM(x) \
	132	((RV_X(x, 3, 2) << 5) \| (RV_X(x, 5, 1) << 12) \| (RV_X(x, 6, 3) << 2))
	133	#define ENCODE_RVC_SWSP_IMM(x) \
	134	((RV_X(x, 2, 4) << 9) \| (RV_X(x, 6, 2) << 7))
	135	#define ENCODE_RVC_SDSP_IMM(x) \
	136	((RV_X(x, 3, 3) << 10) \| (RV_X(x, 6, 3) << 7))
	137	#define ENCODE_RVC_B_IMM(x) \
	138	((RV_X(x, 1, 2) << 3) \| (RV_X(x, 3, 2) << 10) \| (RV_X(x, 5, 1) << 2) \| (RV_X(x, 6, 2) << 5) \| (RV_X(x, 8, 1) << 12))
	139	#define ENCODE_RVC_J_IMM(x) \
	140	((RV_X(x, 1, 3) << 3) \| (RV_X(x, 4, 1) << 11) \| (RV_X(x, 5, 1) << 2) \| (RV_X(x, 6, 1) << 7) \| (RV_X(x, 7, 1) << 6) \| (RV_X(x, 8, 2) << 9) \| (RV_X(x, 10, 1) << 8) \| (RV_X(x, 11, 1) << 12))
	141
	142	#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
	143	#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
	144	#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
	145	#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
	146	#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
	147	#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
3342be5d	148	#define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
e23eba97	149	#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
0e35537d	150	#define VALID_RVC_UIMM8(x) (EXTRACT_RVC_UIMM8(ENCODE_RVC_UIMM8(x)) == (x))
e23eba97 NC	151	#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
	152	#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
	153	#define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x))
	154	#define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x))
	155	#define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x))
	156	#define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x))
	157	#define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x))
	158	#define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
	159	#define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
	160	#define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
	161
	162	#define RISCV_RTYPE(insn, rd, rs1, rs2) \
	163	((MATCH_ ## insn) \| ((rd) << OP_SH_RD) \| ((rs1) << OP_SH_RS1) \| ((rs2) << OP_SH_RS2))
	164	#define RISCV_ITYPE(insn, rd, rs1, imm) \
	165	((MATCH_ ## insn) \| ((rd) << OP_SH_RD) \| ((rs1) << OP_SH_RS1) \| ENCODE_ITYPE_IMM(imm))
	166	#define RISCV_STYPE(insn, rs1, rs2, imm) \
	167	((MATCH_ ## insn) \| ((rs1) << OP_SH_RS1) \| ((rs2) << OP_SH_RS2) \| ENCODE_STYPE_IMM(imm))
	168	#define RISCV_SBTYPE(insn, rs1, rs2, target) \
	169	((MATCH_ ## insn) \| ((rs1) << OP_SH_RS1) \| ((rs2) << OP_SH_RS2) \| ENCODE_SBTYPE_IMM(target))
	170	#define RISCV_UTYPE(insn, rd, bigimm) \
	171	((MATCH_ ## insn) \| ((rd) << OP_SH_RD) \| ENCODE_UTYPE_IMM(bigimm))
	172	#define RISCV_UJTYPE(insn, rd, target) \
	173	((MATCH_ ## insn) \| ((rd) << OP_SH_RD) \| ENCODE_UJTYPE_IMM(target))
	174
	175	#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
	176	#define RVC_NOP MATCH_C_ADDI
	177
	178	#define RISCV_CONST_HIGH_PART(VALUE) \
	179	(((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
	180	#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
	181	#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
	182	#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
	183
	184	#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
	185	#define RISCV_JUMP_ALIGN_BITS 1
	186	#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
	187	#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
	188
	189	#define RISCV_IMM_BITS 12
	190	#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
	191	#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
	192	#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
	193	#define RISCV_RVC_IMM_REACH (1LL << 6)
	194	#define RISCV_BRANCH_BITS RISCV_IMM_BITS
	195	#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
	196	#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
	197	#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
	198
	199	/* RV fields. */
	200
	201	#define OP_MASK_OP 0x7f
	202	#define OP_SH_OP 0
	203	#define OP_MASK_RS2 0x1f
	204	#define OP_SH_RS2 20
	205	#define OP_MASK_RS1 0x1f
	206	#define OP_SH_RS1 15
	207	#define OP_MASK_RS3 0x1f
	208	#define OP_SH_RS3 27
	209	#define OP_MASK_RD 0x1f
	210	#define OP_SH_RD 7
	211	#define OP_MASK_SHAMT 0x3f
	212	#define OP_SH_SHAMT 20
	213	#define OP_MASK_SHAMTW 0x1f
	214	#define OP_SH_SHAMTW 20
215	#define OP_MASK_RM 0x7
216	#define OP_SH_RM 12
217	#define OP_MASK_PRED 0xf
218	#define OP_SH_PRED 24
219	#define OP_MASK_SUCC 0xf
220	#define OP_SH_SUCC 20
221	#define OP_MASK_AQ 0x1
222	#define OP_SH_AQ 26
223	#define OP_MASK_RL 0x1
224	#define OP_SH_RL 25
225
226	#define OP_MASK_CUSTOM_IMM 0x7f
227	#define OP_SH_CUSTOM_IMM 25
228	#define OP_MASK_CSR 0xfff
229	#define OP_SH_CSR 20
230
0e35537d JW	231	#define OP_MASK_FUNCT3 0x7
	232	#define OP_SH_FUNCT3 12
	233	#define OP_MASK_FUNCT7 0x7f
	234	#define OP_SH_FUNCT7 25
	235	#define OP_MASK_FUNCT2 0x3
	236	#define OP_SH_FUNCT2 25
	237
e23eba97 NC	238	/* RVC fields. */
e23eba97 NC	239
0e35537d JW	240	#define OP_MASK_OP2 0x3
	241	#define OP_SH_OP2 0
	242
e23eba97 NC	243	#define OP_MASK_CRS2 0x1f
	244	#define OP_SH_CRS2 2
	245	#define OP_MASK_CRS1S 0x7
	246	#define OP_SH_CRS1S 7
	247	#define OP_MASK_CRS2S 0x7
	248	#define OP_SH_CRS2S 2
	249
0e35537d JW	250	#define OP_MASK_CFUNCT4 0xf
	251	#define OP_SH_CFUNCT4 12
	252	#define OP_MASK_CFUNCT3 0x7
	253	#define OP_SH_CFUNCT3 13
	254
e23eba97 NC	255	/* ABI names for selected x-registers. */
	256
	257	#define X_RA 1
	258	#define X_SP 2
	259	#define X_GP 3
	260	#define X_TP 4
	261	#define X_T0 5
	262	#define X_T1 6
	263	#define X_T2 7
	264	#define X_T3 28
	265
	266	#define NGPR 32
	267	#define NFPR 32
	268
	269	/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
	270	VALUE << SHIFT. VALUE is evaluated exactly once. */
	271	#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
	272	(STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
	273	\| ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
	274
	275	/* Extract bits MASK << SHIFT from STRUCT and shift them right
	276	SHIFT places. */
	277	#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
	278	(((STRUCT) >> (SHIFT)) & (MASK))
	279
	280	/* Extract the operand given by FIELD from integer INSN. */
	281	#define EXTRACT_OPERAND(FIELD, INSN) \
	282	EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
	283
	284	/* This structure holds information for a particular instruction. */
	285
	286	struct riscv_opcode
	287	{
	288	/* The name of the instruction. */
	289	const char *name;
	290	/* The ISA subset name (I, M, A, F, D, Xextension). */
	291	const char *subset;
	292	/* A string describing the arguments for this instruction. */
	293	const char *args;
	294	/* The basic opcode for the instruction. When assembling, this
	295	opcode is modified by the arguments to produce the actual opcode
	296	that is used. If pinfo is INSN_MACRO, then this is 0. */
	297	insn_t match;
	298	/* If pinfo is not INSN_MACRO, then this is a bit mask for the
	299	relevant portions of the opcode when disassembling. If the
	300	actual opcode anded with the match field equals the opcode field,
	301	then we have found the correct instruction. If pinfo is
	302	INSN_MACRO, then this field is the macro identifier. */
	303	insn_t mask;
	304	/* A function to determine if a word corresponds to this instruction.
	305	Usually, this computes ((word & mask) == match). */
	306	int (match_func) (const struct riscv_opcode op, insn_t word);
	307	/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
	308	of bits describing the instruction, notably any relevant hazard
	309	information. */
	310	unsigned long pinfo;
	311	};
	312
	313	/* Instruction is a simple alias (e.g. "mv" for "addi"). */
	314	#define INSN_ALIAS 0x00000001
	315	/* Instruction is actually a macro. It should be ignored by the
	316	disassembler, and requires special treatment by the assembler. */
	317	#define INSN_MACRO 0xffffffff
	318
319	/* This is a list of macro expanded instructions.
320
321	_I appended means immediate
322	_A appended means address
323	_AB appended means address with base register
324	_D appended means 64 bit floating point constant
325	_S appended means 32 bit floating point constant. */
326
327	enum
328	{
329	M_LA,
330	M_LLA,
331	M_LA_TLS_GD,
332	M_LA_TLS_IE,
333	M_LB,
334	M_LBU,
335	M_LH,
336	M_LHU,
337	M_LW,
338	M_LWU,
339	M_LD,
340	M_SB,
341	M_SH,
342	M_SW,
343	M_SD,
344	M_FLW,
345	M_FLD,
cc917fd9	346	M_FLQ,
e23eba97 NC	347	M_FSW,
e23eba97 NC	348	M_FSD,
cc917fd9	349	M_FSQ,
e23eba97 NC	350	M_CALL,
	351	M_J,
	352	M_LI,
	353	M_NUM_MACROS
	354	};
	355
	356
	357	extern const char * const riscv_gpr_names_numeric[NGPR];
	358	extern const char * const riscv_gpr_names_abi[NGPR];
	359	extern const char * const riscv_fpr_names_numeric[NFPR];
	360	extern const char * const riscv_fpr_names_abi[NFPR];
	361
	362	extern const struct riscv_opcode riscv_opcodes[];
0e35537d	363	extern const struct riscv_opcode riscv_insn_types[];
e23eba97 NC	364
e23eba97 NC	365	#endif /* _RISCV_H_ */