[deliverable/linux.git] / include / video / imx-ipu-v3.h

/*
 * Copyright 2005-2009 Freescale Semiconductor, Inc.
 *
 * The code contained herein is licensed under the GNU Lesser General
 * Public License.  You may obtain a copy of the GNU Lesser General
 * Public License Version 2.1 or later at the following locations:
 *
 * http://www.opensource.org/licenses/lgpl-license.html
 * http://www.gnu.org/copyleft/lgpl.html
 */

#ifndef __DRM_IPU_H__
#define __DRM_IPU_H__

#include <linux/types.h>
#include <linux/videodev2.h>
#include <linux/bitmap.h>
#include <linux/fb.h>
#include <linux/of.h>
#include <media/v4l2-mediabus.h>
#include <video/videomode.h>

struct ipu_soc;

enum ipuv3_type {
	IPUV3EX,
	IPUV3M,
	IPUV3H,
};

#define IPU_PIX_FMT_GBR24	v4l2_fourcc('G', 'B', 'R', '3')

/*
 * Bitfield of Display Interface signal polarities.
 */
struct ipu_di_signal_cfg {
	unsigned data_pol:1;	/* true = inverted */
	unsigned clk_pol:1;	/* true = rising edge */
	unsigned enable_pol:1;

	struct videomode mode;

	u32 bus_format;
	u32 v_to_h_sync;

#define IPU_DI_CLKMODE_SYNC	(1 << 0)
#define IPU_DI_CLKMODE_EXT	(1 << 1)
	unsigned long clkflags;

	u8 hsync_pin;
	u8 vsync_pin;
};

/*
 * Enumeration of CSI destinations
 */
enum ipu_csi_dest {
	IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
	IPU_CSI_DEST_IC,	/* to Image Converter */
	IPU_CSI_DEST_VDIC,  /* to VDIC */
};

/*
 * Enumeration of IPU rotation modes
 */
enum ipu_rotate_mode {
	IPU_ROTATE_NONE = 0,
	IPU_ROTATE_VERT_FLIP,
	IPU_ROTATE_HORIZ_FLIP,
	IPU_ROTATE_180,
	IPU_ROTATE_90_RIGHT,
	IPU_ROTATE_90_RIGHT_VFLIP,
	IPU_ROTATE_90_RIGHT_HFLIP,
	IPU_ROTATE_90_LEFT,
};

enum ipu_color_space {
	IPUV3_COLORSPACE_RGB,
	IPUV3_COLORSPACE_YUV,
	IPUV3_COLORSPACE_UNKNOWN,
};

struct ipuv3_channel;

enum ipu_channel_irq {
	IPU_IRQ_EOF = 0,
	IPU_IRQ_NFACK = 64,
	IPU_IRQ_NFB4EOF = 128,
	IPU_IRQ_EOS = 192,
};

/*
 * Enumeration of IDMAC channels
 */
#define IPUV3_CHANNEL_CSI0			 0
#define IPUV3_CHANNEL_CSI1			 1
#define IPUV3_CHANNEL_CSI2			 2
#define IPUV3_CHANNEL_CSI3			 3
#define IPUV3_CHANNEL_VDI_MEM_IC_VF		 5
#define IPUV3_CHANNEL_MEM_VDI_PREV		 8
#define IPUV3_CHANNEL_MEM_VDI_CUR		 9
#define IPUV3_CHANNEL_MEM_VDI_NEXT		10
#define IPUV3_CHANNEL_MEM_IC_PP			11
#define IPUV3_CHANNEL_MEM_IC_PRP_VF		12
#define IPUV3_CHANNEL_VDI_MEM_RECENT		13
#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF		14
#define IPUV3_CHANNEL_G_MEM_IC_PP		15
#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA	17
#define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA		18
#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA	19
#define IPUV3_CHANNEL_IC_PRP_ENC_MEM		20
#define IPUV3_CHANNEL_IC_PRP_VF_MEM		21
#define IPUV3_CHANNEL_IC_PP_MEM			22
#define IPUV3_CHANNEL_MEM_BG_SYNC		23
#define IPUV3_CHANNEL_MEM_BG_ASYNC		24
#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB	25
#define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB	26
#define IPUV3_CHANNEL_MEM_FG_SYNC		27
#define IPUV3_CHANNEL_MEM_DC_SYNC		28
#define IPUV3_CHANNEL_MEM_FG_ASYNC		29
#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA		31
#define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA	33
#define IPUV3_CHANNEL_DC_MEM_READ		40
#define IPUV3_CHANNEL_MEM_DC_ASYNC		41
#define IPUV3_CHANNEL_MEM_DC_COMMAND		42
#define IPUV3_CHANNEL_MEM_DC_COMMAND2		43
#define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK	44
#define IPUV3_CHANNEL_MEM_ROT_ENC		45
#define IPUV3_CHANNEL_MEM_ROT_VF		46
#define IPUV3_CHANNEL_MEM_ROT_PP		47
#define IPUV3_CHANNEL_ROT_ENC_MEM		48
#define IPUV3_CHANNEL_ROT_VF_MEM		49
#define IPUV3_CHANNEL_ROT_PP_MEM		50
#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA		51
#define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA	52

int ipu_map_irq(struct ipu_soc *ipu, int irq);
int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
		enum ipu_channel_irq irq);

#define IPU_IRQ_DP_SF_START		(448 + 2)
#define IPU_IRQ_DP_SF_END		(448 + 3)
#define IPU_IRQ_BG_SF_END		IPU_IRQ_DP_SF_END,
#define IPU_IRQ_DC_FC_0			(448 + 8)
#define IPU_IRQ_DC_FC_1			(448 + 9)
#define IPU_IRQ_DC_FC_2			(448 + 10)
#define IPU_IRQ_DC_FC_3			(448 + 11)
#define IPU_IRQ_DC_FC_4			(448 + 12)
#define IPU_IRQ_DC_FC_6			(448 + 13)
#define IPU_IRQ_VSYNC_PRE_0		(448 + 14)
#define IPU_IRQ_VSYNC_PRE_1		(448 + 15)

/*
 * IPU Common functions
 */
int ipu_get_num(struct ipu_soc *ipu);
void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
void ipu_dump(struct ipu_soc *ipu);

/*
 * IPU Image DMA Controller (idmac) functions
 */
struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
void ipu_idmac_put(struct ipuv3_channel *);

int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);

void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
		bool doublebuffer);
int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);

/*
 * IPU Channel Parameter Memory (cpmem) functions
 */
struct ipu_rgb {
	struct fb_bitfield      red;
	struct fb_bitfield      green;
	struct fb_bitfield      blue;
	struct fb_bitfield      transp;
	int                     bits_per_pixel;
};

struct ipu_image {
	struct v4l2_pix_format pix;
	struct v4l2_rect rect;
	dma_addr_t phys0;
	dma_addr_t phys1;
};

void ipu_cpmem_zero(struct ipuv3_channel *ch);
void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
			    enum ipu_rotate_mode rot);
int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
			     const struct ipu_rgb *rgb);
int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
				   unsigned int uv_stride,
				   unsigned int u_offset,
				   unsigned int v_offset);
void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
			      u32 pixel_format, int stride, int height);
int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
void ipu_cpmem_dump(struct ipuv3_channel *ch);

/*
 * IPU Display Controller (dc) functions
 */
struct ipu_dc;
struct ipu_di;
struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
void ipu_dc_put(struct ipu_dc *dc);
int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
		u32 pixel_fmt, u32 width);
void ipu_dc_enable(struct ipu_soc *ipu);
void ipu_dc_enable_channel(struct ipu_dc *dc);
void ipu_dc_disable_channel(struct ipu_dc *dc);
void ipu_dc_disable(struct ipu_soc *ipu);

/*
 * IPU Display Interface (di) functions
 */
struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
void ipu_di_put(struct ipu_di *);
int ipu_di_disable(struct ipu_di *);
int ipu_di_enable(struct ipu_di *);
int ipu_di_get_num(struct ipu_di *);
int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);

/*
 * IPU Display Multi FIFO Controller (dmfc) functions
 */
struct dmfc_channel;
int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
void ipu_dmfc_put(struct dmfc_channel *dmfc);

/*
 * IPU Display Processor (dp) functions
 */
#define IPU_DP_FLOW_SYNC_BG	0
#define IPU_DP_FLOW_SYNC_FG	1
#define IPU_DP_FLOW_ASYNC0_BG	2
#define IPU_DP_FLOW_ASYNC0_FG	3
#define IPU_DP_FLOW_ASYNC1_BG	4
#define IPU_DP_FLOW_ASYNC1_FG	5

struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
void ipu_dp_put(struct ipu_dp *);
int ipu_dp_enable(struct ipu_soc *ipu);
int ipu_dp_enable_channel(struct ipu_dp *dp);
void ipu_dp_disable_channel(struct ipu_dp *dp);
void ipu_dp_disable(struct ipu_soc *ipu);
int ipu_dp_setup_channel(struct ipu_dp *dp,
		enum ipu_color_space in, enum ipu_color_space out);
int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
		bool bg_chan);

/*
 * IPU CMOS Sensor Interface (csi) functions
 */
struct ipu_csi;
int ipu_csi_init_interface(struct ipu_csi *csi,
			   struct v4l2_mbus_config *mbus_cfg,
			   struct v4l2_mbus_framefmt *mbus_fmt);
bool ipu_csi_is_interlaced(struct ipu_csi *csi);
void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
				u32 r_value, u32 g_value, u32 b_value,
				u32 pix_clk);
int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
			      struct v4l2_mbus_framefmt *mbus_fmt);
int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
			  u32 max_ratio, u32 id);
int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
int ipu_csi_enable(struct ipu_csi *csi);
int ipu_csi_disable(struct ipu_csi *csi);
struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
void ipu_csi_put(struct ipu_csi *csi);
void ipu_csi_dump(struct ipu_csi *csi);

/*
 * IPU Image Converter (ic) functions
 */
enum ipu_ic_task {
	IC_TASK_ENCODER,
	IC_TASK_VIEWFINDER,
	IC_TASK_POST_PROCESSOR,
	IC_NUM_TASKS,
};

struct ipu_ic;
int ipu_ic_task_init(struct ipu_ic *ic,
		     int in_width, int in_height,
		     int out_width, int out_height,
		     enum ipu_color_space in_cs,
		     enum ipu_color_space out_cs);
int ipu_ic_task_graphics_init(struct ipu_ic *ic,
			      enum ipu_color_space in_g_cs,
			      bool galpha_en, u32 galpha,
			      bool colorkey_en, u32 colorkey);
void ipu_ic_task_enable(struct ipu_ic *ic);
void ipu_ic_task_disable(struct ipu_ic *ic);
int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
			  u32 width, u32 height, int burst_size,
			  enum ipu_rotate_mode rot);
int ipu_ic_enable(struct ipu_ic *ic);
int ipu_ic_disable(struct ipu_ic *ic);
struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
void ipu_ic_put(struct ipu_ic *ic);
void ipu_ic_dump(struct ipu_ic *ic);

/*
 * IPU Sensor Multiple FIFO Controller (SMFC) functions
 */
struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
void ipu_smfc_put(struct ipu_smfc *smfc);
int ipu_smfc_enable(struct ipu_smfc *smfc);
int ipu_smfc_disable(struct ipu_smfc *smfc);
int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);

enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
bool ipu_pixelformat_is_planar(u32 pixelformat);
int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
			    bool hflip, bool vflip);
int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
			    bool hflip, bool vflip);

struct ipu_client_platformdata {
	int csi;
	int di;
	int dc;
	int dp;
	int dma[2];
	struct device_node *of_node;
};

#endif /* __DRM_IPU_H__ */
Commit	Line	Data
aecfbdb1 SH	1	/*
	2	* Copyright 2005-2009 Freescale Semiconductor, Inc.
	3	*
	4	* The code contained herein is licensed under the GNU Lesser General
	5	* Public License. You may obtain a copy of the GNU Lesser General
	6	* Public License Version 2.1 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/lgpl-license.html
	9	* http://www.gnu.org/copyleft/lgpl.html
	10	*/
	11
	12	#ifndef __DRM_IPU_H__
	13	#define __DRM_IPU_H__
	14
	15	#include <linux/types.h>
	16	#include <linux/videodev2.h>
	17	#include <linux/bitmap.h>
	18	#include <linux/fb.h>
310944d1	19	#include <linux/of.h>
2ffd48f2	20	#include <media/v4l2-mediabus.h>
6541d710	21	#include <video/videomode.h>
aecfbdb1 SH	22
	23	struct ipu_soc;
	24
	25	enum ipuv3_type {
	26	IPUV3EX,
	27	IPUV3M,
	28	IPUV3H,
	29	};
	30
7f4392aa PZ	31	#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
7f4392aa PZ	32
aecfbdb1 SH	33	/*
	34	* Bitfield of Display Interface signal polarities.
	35	*/
	36	struct ipu_di_signal_cfg {
aecfbdb1 SH	37	unsigned data_pol:1; /* true = inverted */
	38	unsigned clk_pol:1; /* true = rising edge */
	39	unsigned enable_pol:1;
aecfbdb1	40
b6835a71 SL	41	struct videomode mode;
b6835a71 SL	42
2872c807	43	u32 bus_format;
aecfbdb1	44	u32 v_to_h_sync;
b6835a71	45
aecfbdb1 SH	46	#define IPU_DI_CLKMODE_SYNC (1 << 0)
	47	#define IPU_DI_CLKMODE_EXT (1 << 1)
	48	unsigned long clkflags;
2ea42608 PZ	49
	50	u8 hsync_pin;
	51	u8 vsync_pin;
aecfbdb1 SH	52	};
aecfbdb1 SH	53
2ffd48f2 SL	54	/*
	55	* Enumeration of CSI destinations
	56	*/
	57	enum ipu_csi_dest {
	58	IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
	59	IPU_CSI_DEST_IC, /* to Image Converter */
	60	IPU_CSI_DEST_VDIC, /* to VDIC */
	61	};
	62
1aa8ea0d SL	63	/*
	64	* Enumeration of IPU rotation modes
	65	*/
	66	enum ipu_rotate_mode {
	67	IPU_ROTATE_NONE = 0,
	68	IPU_ROTATE_VERT_FLIP,
	69	IPU_ROTATE_HORIZ_FLIP,
	70	IPU_ROTATE_180,
	71	IPU_ROTATE_90_RIGHT,
	72	IPU_ROTATE_90_RIGHT_VFLIP,
	73	IPU_ROTATE_90_RIGHT_HFLIP,
	74	IPU_ROTATE_90_LEFT,
	75	};
	76
aecfbdb1 SH	77	enum ipu_color_space {
	78	IPUV3_COLORSPACE_RGB,
	79	IPUV3_COLORSPACE_YUV,
	80	IPUV3_COLORSPACE_UNKNOWN,
	81	};
	82
	83	struct ipuv3_channel;
	84
	85	enum ipu_channel_irq {
	86	IPU_IRQ_EOF = 0,
	87	IPU_IRQ_NFACK = 64,
	88	IPU_IRQ_NFB4EOF = 128,
	89	IPU_IRQ_EOS = 192,
	90	};
	91
a4cd8f22 SL	92	/*
	93	* Enumeration of IDMAC channels
	94	*/
	95	#define IPUV3_CHANNEL_CSI0 0
	96	#define IPUV3_CHANNEL_CSI1 1
	97	#define IPUV3_CHANNEL_CSI2 2
	98	#define IPUV3_CHANNEL_CSI3 3
	99	#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
97afc25c SL	100	#define IPUV3_CHANNEL_MEM_VDI_PREV 8
	101	#define IPUV3_CHANNEL_MEM_VDI_CUR 9
	102	#define IPUV3_CHANNEL_MEM_VDI_NEXT 10
a4cd8f22 SL	103	#define IPUV3_CHANNEL_MEM_IC_PP 11
a4cd8f22 SL	104	#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
bc0a3387	105	#define IPUV3_CHANNEL_VDI_MEM_RECENT 13
a4cd8f22 SL	106	#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
a4cd8f22 SL	107	#define IPUV3_CHANNEL_G_MEM_IC_PP 15
bc0a3387 PZ	108	#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17
	109	#define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA 18
	110	#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19
a4cd8f22 SL	111	#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
	112	#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
	113	#define IPUV3_CHANNEL_IC_PP_MEM 22
	114	#define IPUV3_CHANNEL_MEM_BG_SYNC 23
	115	#define IPUV3_CHANNEL_MEM_BG_ASYNC 24
bc0a3387 PZ	116	#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB 25
bc0a3387 PZ	117	#define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB 26
a4cd8f22 SL	118	#define IPUV3_CHANNEL_MEM_FG_SYNC 27
	119	#define IPUV3_CHANNEL_MEM_DC_SYNC 28
	120	#define IPUV3_CHANNEL_MEM_FG_ASYNC 29
	121	#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
bc0a3387 PZ	122	#define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA 33
bc0a3387 PZ	123	#define IPUV3_CHANNEL_DC_MEM_READ 40
a4cd8f22	124	#define IPUV3_CHANNEL_MEM_DC_ASYNC 41
bc0a3387 PZ	125	#define IPUV3_CHANNEL_MEM_DC_COMMAND 42
	126	#define IPUV3_CHANNEL_MEM_DC_COMMAND2 43
	127	#define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK 44
a4cd8f22 SL	128	#define IPUV3_CHANNEL_MEM_ROT_ENC 45
	129	#define IPUV3_CHANNEL_MEM_ROT_VF 46
	130	#define IPUV3_CHANNEL_MEM_ROT_PP 47
	131	#define IPUV3_CHANNEL_ROT_ENC_MEM 48
	132	#define IPUV3_CHANNEL_ROT_VF_MEM 49
	133	#define IPUV3_CHANNEL_ROT_PP_MEM 50
	134	#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
bc0a3387	135	#define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52
a4cd8f22	136
861a50c1	137	int ipu_map_irq(struct ipu_soc *ipu, int irq);
aecfbdb1 SH	138	int ipu_idmac_channel_irq(struct ipu_soc ipu, struct ipuv3_channel channel,
	139	enum ipu_channel_irq irq);
	140
	141	#define IPU_IRQ_DP_SF_START (448 + 2)
	142	#define IPU_IRQ_DP_SF_END (448 + 3)
	143	#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
	144	#define IPU_IRQ_DC_FC_0 (448 + 8)
	145	#define IPU_IRQ_DC_FC_1 (448 + 9)
	146	#define IPU_IRQ_DC_FC_2 (448 + 10)
	147	#define IPU_IRQ_DC_FC_3 (448 + 11)
	148	#define IPU_IRQ_DC_FC_4 (448 + 12)
	149	#define IPU_IRQ_DC_FC_6 (448 + 13)
	150	#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
	151	#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
	152
ba07975f SL	153	/*
	154	* IPU Common functions
	155	*/
572a7615	156	int ipu_get_num(struct ipu_soc *ipu);
ba07975f SL	157	void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
ba07975f SL	158	void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
3feb049f	159	void ipu_dump(struct ipu_soc *ipu);
ba07975f	160
aecfbdb1 SH	161	/*
	162	* IPU Image DMA Controller (idmac) functions
	163	*/
	164	struct ipuv3_channel ipu_idmac_get(struct ipu_soc ipu, unsigned channel);
	165	void ipu_idmac_put(struct ipuv3_channel *);
	166
	167	int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
	168	int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
2bcf577e	169	void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
4fd1a07a	170	int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
fb822a39	171	int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
aecfbdb1 SH	172
	173	void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
	174	bool doublebuffer);
e9046097	175	int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
aa52f578	176	bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
aecfbdb1	177	void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
bce6f087	178	void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
aecfbdb1	179
7d2691da SL	180	/*
	181	* IPU Channel Parameter Memory (cpmem) functions
	182	*/
	183	struct ipu_rgb {
	184	struct fb_bitfield red;
	185	struct fb_bitfield green;
	186	struct fb_bitfield blue;
	187	struct fb_bitfield transp;
	188	int bits_per_pixel;
	189	};
	190
	191	struct ipu_image {
	192	struct v4l2_pix_format pix;
	193	struct v4l2_rect rect;
2094b603 SL	194	dma_addr_t phys0;
2094b603 SL	195	dma_addr_t phys1;
7d2691da SL	196	};
	197
	198	void ipu_cpmem_zero(struct ipuv3_channel *ch);
	199	void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
	200	void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
	201	void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
	202	void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
e5e8690f	203	void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
7d2691da	204	void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
555f0e66	205	void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
03085911	206	int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
7d2691da	207	void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
9b9da0be	208	void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
c42d37ca SL	209	void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
c42d37ca SL	210	enum ipu_rotate_mode rot);
7d2691da SL	211	int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
	212	const struct ipu_rgb *rgb);
	213	int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
	214	void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
	215	void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
90195c36 PZ	216	unsigned int uv_stride,
	217	unsigned int u_offset,
	218	unsigned int v_offset);
7d2691da SL	219	void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
	220	u32 pixel_format, int stride, int height);
	221	int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
	222	int ipu_cpmem_set_image(struct ipuv3_channel ch, struct ipu_image image);
60c04456	223	void ipu_cpmem_dump(struct ipuv3_channel *ch);
7d2691da	224
aecfbdb1 SH	225	/*
	226	* IPU Display Controller (dc) functions
	227	*/
	228	struct ipu_dc;
	229	struct ipu_di;
	230	struct ipu_dc ipu_dc_get(struct ipu_soc ipu, int channel);
	231	void ipu_dc_put(struct ipu_dc *dc);
	232	int ipu_dc_init_sync(struct ipu_dc dc, struct ipu_di di, bool interlaced,
	233	u32 pixel_fmt, u32 width);
1e6d486b	234	void ipu_dc_enable(struct ipu_soc *ipu);
aecfbdb1 SH	235	void ipu_dc_enable_channel(struct ipu_dc *dc);
aecfbdb1 SH	236	void ipu_dc_disable_channel(struct ipu_dc *dc);
1e6d486b	237	void ipu_dc_disable(struct ipu_soc *ipu);
aecfbdb1 SH	238
	239	/*
	240	* IPU Display Interface (di) functions
	241	*/
	242	struct ipu_di ipu_di_get(struct ipu_soc ipu, int disp);
	243	void ipu_di_put(struct ipu_di *);
	244	int ipu_di_disable(struct ipu_di *);
	245	int ipu_di_enable(struct ipu_di *);
	246	int ipu_di_get_num(struct ipu_di *);
6541d710	247	int ipu_di_adjust_videomode(struct ipu_di di, struct videomode mode);
aecfbdb1 SH	248	int ipu_di_init_sync_panel(struct ipu_di , struct ipu_di_signal_cfg sig);
	249
	250	/*
	251	* IPU Display Multi FIFO Controller (dmfc) functions
	252	*/
	253	struct dmfc_channel;
	254	int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
	255	void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
27630c20	256	void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
aecfbdb1 SH	257	struct dmfc_channel ipu_dmfc_get(struct ipu_soc ipu, int ipuv3_channel);
	258	void ipu_dmfc_put(struct dmfc_channel *dmfc);
	259
	260	/*
	261	* IPU Display Processor (dp) functions
	262	*/
	263	#define IPU_DP_FLOW_SYNC_BG 0
	264	#define IPU_DP_FLOW_SYNC_FG 1
	265	#define IPU_DP_FLOW_ASYNC0_BG 2
	266	#define IPU_DP_FLOW_ASYNC0_FG 3
	267	#define IPU_DP_FLOW_ASYNC1_BG 4
	268	#define IPU_DP_FLOW_ASYNC1_FG 5
	269
	270	struct ipu_dp ipu_dp_get(struct ipu_soc ipu, unsigned int flow);
	271	void ipu_dp_put(struct ipu_dp *);
285bbb01	272	int ipu_dp_enable(struct ipu_soc *ipu);
aecfbdb1 SH	273	int ipu_dp_enable_channel(struct ipu_dp *dp);
aecfbdb1 SH	274	void ipu_dp_disable_channel(struct ipu_dp *dp);
285bbb01	275	void ipu_dp_disable(struct ipu_soc *ipu);
aecfbdb1 SH	276	int ipu_dp_setup_channel(struct ipu_dp *dp,
	277	enum ipu_color_space in, enum ipu_color_space out);
	278	int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
	279	int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
	280	bool bg_chan);
	281
3f5a8a94 PZ	282	/*
	283	* IPU CMOS Sensor Interface (csi) functions
	284	*/
2ffd48f2 SL	285	struct ipu_csi;
	286	int ipu_csi_init_interface(struct ipu_csi *csi,
	287	struct v4l2_mbus_config *mbus_cfg,
	288	struct v4l2_mbus_framefmt *mbus_fmt);
	289	bool ipu_csi_is_interlaced(struct ipu_csi *csi);
	290	void ipu_csi_get_window(struct ipu_csi csi, struct v4l2_rect w);
	291	void ipu_csi_set_window(struct ipu_csi csi, struct v4l2_rect w);
	292	void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
	293	u32 r_value, u32 g_value, u32 b_value,
	294	u32 pix_clk);
	295	int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
	296	struct v4l2_mbus_framefmt *mbus_fmt);
	297	int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
	298	u32 max_ratio, u32 id);
	299	int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
	300	int ipu_csi_enable(struct ipu_csi *csi);
	301	int ipu_csi_disable(struct ipu_csi *csi);
	302	struct ipu_csi ipu_csi_get(struct ipu_soc ipu, int id);
	303	void ipu_csi_put(struct ipu_csi *csi);
	304	void ipu_csi_dump(struct ipu_csi *csi);
3f5a8a94	305
1aa8ea0d SL	306	/*
	307	* IPU Image Converter (ic) functions
	308	*/
	309	enum ipu_ic_task {
	310	IC_TASK_ENCODER,
	311	IC_TASK_VIEWFINDER,
	312	IC_TASK_POST_PROCESSOR,
	313	IC_NUM_TASKS,
	314	};
	315
	316	struct ipu_ic;
	317	int ipu_ic_task_init(struct ipu_ic *ic,
	318	int in_width, int in_height,
	319	int out_width, int out_height,
	320	enum ipu_color_space in_cs,
	321	enum ipu_color_space out_cs);
	322	int ipu_ic_task_graphics_init(struct ipu_ic *ic,
	323	enum ipu_color_space in_g_cs,
	324	bool galpha_en, u32 galpha,
	325	bool colorkey_en, u32 colorkey);
	326	void ipu_ic_task_enable(struct ipu_ic *ic);
	327	void ipu_ic_task_disable(struct ipu_ic *ic);
	328	int ipu_ic_task_idma_init(struct ipu_ic ic, struct ipuv3_channel channel,
	329	u32 width, u32 height, int burst_size,
	330	enum ipu_rotate_mode rot);
	331	int ipu_ic_enable(struct ipu_ic *ic);
	332	int ipu_ic_disable(struct ipu_ic *ic);
	333	struct ipu_ic ipu_ic_get(struct ipu_soc ipu, enum ipu_ic_task task);
	334	void ipu_ic_put(struct ipu_ic *ic);
	335	void ipu_ic_dump(struct ipu_ic *ic);
	336
35de925f PZ	337	/*
	338	* IPU Sensor Multiple FIFO Controller (SMFC) functions
	339	*/
7fafa8f0 SL	340	struct ipu_smfc ipu_smfc_get(struct ipu_soc ipu, unsigned int chno);
	341	void ipu_smfc_put(struct ipu_smfc *smfc);
	342	int ipu_smfc_enable(struct ipu_smfc *smfc);
	343	int ipu_smfc_disable(struct ipu_smfc *smfc);
	344	int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
	345	int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
a2be35e3	346	int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
35de925f	347
7cb17797	348	enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
aecfbdb1	349	enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
ae0e9708	350	enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
6930afdc	351	int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
4cea940d	352	bool ipu_pixelformat_is_planar(u32 pixelformat);
f835f386 SL	353	int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
	354	bool hflip, bool vflip);
	355	int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
	356	bool hflip, bool vflip);
aecfbdb1	357
aecfbdb1	358	struct ipu_client_platformdata {
d6ca8ca7	359	int csi;
aecfbdb1 SH	360	int di;
	361	int dc;
	362	int dp;
aecfbdb1	363	int dma[2];
310944d1	364	struct device_node *of_node;
aecfbdb1 SH	365	};
	366
	367	#endif /* __DRM_IPU_H__ */