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aecfbdb1 SH |
1 | /* |
2 | * Copyright 2005-2009 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU Lesser General | |
5 | * Public License. You may obtain a copy of the GNU Lesser General | |
6 | * Public License Version 2.1 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/lgpl-license.html | |
9 | * http://www.gnu.org/copyleft/lgpl.html | |
10 | */ | |
11 | ||
12 | #ifndef __DRM_IPU_H__ | |
13 | #define __DRM_IPU_H__ | |
14 | ||
15 | #include <linux/types.h> | |
16 | #include <linux/videodev2.h> | |
17 | #include <linux/bitmap.h> | |
18 | #include <linux/fb.h> | |
aecfbdb1 SH |
19 | |
20 | struct ipu_soc; | |
21 | ||
22 | enum ipuv3_type { | |
23 | IPUV3EX, | |
24 | IPUV3M, | |
25 | IPUV3H, | |
26 | }; | |
27 | ||
7f4392aa PZ |
28 | #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3') |
29 | ||
aecfbdb1 SH |
30 | /* |
31 | * Bitfield of Display Interface signal polarities. | |
32 | */ | |
33 | struct ipu_di_signal_cfg { | |
34 | unsigned datamask_en:1; | |
35 | unsigned interlaced:1; | |
36 | unsigned odd_field_first:1; | |
37 | unsigned clksel_en:1; | |
38 | unsigned clkidle_en:1; | |
39 | unsigned data_pol:1; /* true = inverted */ | |
40 | unsigned clk_pol:1; /* true = rising edge */ | |
41 | unsigned enable_pol:1; | |
42 | unsigned Hsync_pol:1; /* true = active high */ | |
43 | unsigned Vsync_pol:1; | |
44 | ||
45 | u16 width; | |
46 | u16 height; | |
47 | u32 pixel_fmt; | |
48 | u16 h_start_width; | |
49 | u16 h_sync_width; | |
50 | u16 h_end_width; | |
51 | u16 v_start_width; | |
52 | u16 v_sync_width; | |
53 | u16 v_end_width; | |
54 | u32 v_to_h_sync; | |
55 | unsigned long pixelclock; | |
56 | #define IPU_DI_CLKMODE_SYNC (1 << 0) | |
57 | #define IPU_DI_CLKMODE_EXT (1 << 1) | |
58 | unsigned long clkflags; | |
2ea42608 PZ |
59 | |
60 | u8 hsync_pin; | |
61 | u8 vsync_pin; | |
aecfbdb1 SH |
62 | }; |
63 | ||
64 | enum ipu_color_space { | |
65 | IPUV3_COLORSPACE_RGB, | |
66 | IPUV3_COLORSPACE_YUV, | |
67 | IPUV3_COLORSPACE_UNKNOWN, | |
68 | }; | |
69 | ||
70 | struct ipuv3_channel; | |
71 | ||
72 | enum ipu_channel_irq { | |
73 | IPU_IRQ_EOF = 0, | |
74 | IPU_IRQ_NFACK = 64, | |
75 | IPU_IRQ_NFB4EOF = 128, | |
76 | IPU_IRQ_EOS = 192, | |
77 | }; | |
78 | ||
79 | int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, | |
80 | enum ipu_channel_irq irq); | |
81 | ||
82 | #define IPU_IRQ_DP_SF_START (448 + 2) | |
83 | #define IPU_IRQ_DP_SF_END (448 + 3) | |
84 | #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END, | |
85 | #define IPU_IRQ_DC_FC_0 (448 + 8) | |
86 | #define IPU_IRQ_DC_FC_1 (448 + 9) | |
87 | #define IPU_IRQ_DC_FC_2 (448 + 10) | |
88 | #define IPU_IRQ_DC_FC_3 (448 + 11) | |
89 | #define IPU_IRQ_DC_FC_4 (448 + 12) | |
90 | #define IPU_IRQ_DC_FC_6 (448 + 13) | |
91 | #define IPU_IRQ_VSYNC_PRE_0 (448 + 14) | |
92 | #define IPU_IRQ_VSYNC_PRE_1 (448 + 15) | |
93 | ||
94 | /* | |
95 | * IPU Image DMA Controller (idmac) functions | |
96 | */ | |
97 | struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel); | |
98 | void ipu_idmac_put(struct ipuv3_channel *); | |
99 | ||
100 | int ipu_idmac_enable_channel(struct ipuv3_channel *channel); | |
101 | int ipu_idmac_disable_channel(struct ipuv3_channel *channel); | |
fb822a39 | 102 | int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms); |
aecfbdb1 SH |
103 | |
104 | void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, | |
105 | bool doublebuffer); | |
e9046097 | 106 | int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel); |
aecfbdb1 SH |
107 | void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num); |
108 | ||
109 | /* | |
110 | * IPU Display Controller (dc) functions | |
111 | */ | |
112 | struct ipu_dc; | |
113 | struct ipu_di; | |
114 | struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel); | |
115 | void ipu_dc_put(struct ipu_dc *dc); | |
116 | int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, | |
117 | u32 pixel_fmt, u32 width); | |
118 | void ipu_dc_enable_channel(struct ipu_dc *dc); | |
119 | void ipu_dc_disable_channel(struct ipu_dc *dc); | |
120 | ||
121 | /* | |
122 | * IPU Display Interface (di) functions | |
123 | */ | |
124 | struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp); | |
125 | void ipu_di_put(struct ipu_di *); | |
126 | int ipu_di_disable(struct ipu_di *); | |
127 | int ipu_di_enable(struct ipu_di *); | |
128 | int ipu_di_get_num(struct ipu_di *); | |
129 | int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig); | |
130 | ||
131 | /* | |
132 | * IPU Display Multi FIFO Controller (dmfc) functions | |
133 | */ | |
134 | struct dmfc_channel; | |
135 | int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc); | |
136 | void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc); | |
137 | int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc, | |
138 | unsigned long bandwidth_mbs, int burstsize); | |
139 | void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc); | |
140 | int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width); | |
141 | struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel); | |
142 | void ipu_dmfc_put(struct dmfc_channel *dmfc); | |
143 | ||
144 | /* | |
145 | * IPU Display Processor (dp) functions | |
146 | */ | |
147 | #define IPU_DP_FLOW_SYNC_BG 0 | |
148 | #define IPU_DP_FLOW_SYNC_FG 1 | |
149 | #define IPU_DP_FLOW_ASYNC0_BG 2 | |
150 | #define IPU_DP_FLOW_ASYNC0_FG 3 | |
151 | #define IPU_DP_FLOW_ASYNC1_BG 4 | |
152 | #define IPU_DP_FLOW_ASYNC1_FG 5 | |
153 | ||
154 | struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow); | |
155 | void ipu_dp_put(struct ipu_dp *); | |
156 | int ipu_dp_enable_channel(struct ipu_dp *dp); | |
157 | void ipu_dp_disable_channel(struct ipu_dp *dp); | |
158 | int ipu_dp_setup_channel(struct ipu_dp *dp, | |
159 | enum ipu_color_space in, enum ipu_color_space out); | |
160 | int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos); | |
161 | int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha, | |
162 | bool bg_chan); | |
163 | ||
3f5a8a94 PZ |
164 | /* |
165 | * IPU CMOS Sensor Interface (csi) functions | |
166 | */ | |
167 | int ipu_csi_enable(struct ipu_soc *ipu, int csi); | |
168 | int ipu_csi_disable(struct ipu_soc *ipu, int csi); | |
169 | ||
35de925f PZ |
170 | /* |
171 | * IPU Sensor Multiple FIFO Controller (SMFC) functions | |
172 | */ | |
3f5a8a94 PZ |
173 | int ipu_smfc_enable(struct ipu_soc *ipu); |
174 | int ipu_smfc_disable(struct ipu_soc *ipu); | |
35de925f PZ |
175 | int ipu_smfc_map_channel(struct ipu_soc *ipu, int channel, int csi_id, int mipi_id); |
176 | int ipu_smfc_set_burstsize(struct ipu_soc *ipu, int channel, int burstsize); | |
177 | ||
aecfbdb1 SH |
178 | #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size)) |
179 | ||
180 | #define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22) | |
181 | #define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22) | |
182 | #define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4) | |
183 | #define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1) | |
184 | #define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1) | |
185 | #define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14) | |
186 | #define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14) | |
187 | ||
188 | #define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10) | |
189 | #define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9) | |
190 | #define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13) | |
191 | #define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12) | |
192 | #define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1) | |
193 | #define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1) | |
194 | #define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12) | |
195 | #define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11) | |
196 | #define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10) | |
197 | #define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7) | |
198 | #define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10) | |
199 | #define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1) | |
200 | #define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1) | |
201 | #define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7) | |
202 | #define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1) | |
203 | #define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1) | |
204 | #define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3) | |
205 | #define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2) | |
206 | #define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1) | |
207 | #define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3) | |
208 | #define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2) | |
209 | #define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1) | |
210 | #define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1) | |
211 | #define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1) | |
212 | #define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1) | |
213 | #define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1) | |
214 | #define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1) | |
215 | #define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13) | |
216 | #define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12) | |
217 | #define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29) | |
218 | #define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29) | |
219 | #define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20) | |
220 | #define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7) | |
221 | #define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4) | |
222 | #define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1) | |
223 | #define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3) | |
224 | #define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2) | |
225 | #define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7) | |
226 | #define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14) | |
227 | #define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3) | |
228 | #define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3) | |
229 | #define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3) | |
230 | #define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3) | |
231 | #define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5) | |
232 | #define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5) | |
233 | #define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5) | |
234 | #define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5) | |
235 | #define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1) | |
236 | #define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1) | |
237 | #define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1) | |
238 | ||
239 | struct ipu_cpmem_word { | |
240 | u32 data[5]; | |
241 | u32 res[3]; | |
242 | }; | |
243 | ||
244 | struct ipu_ch_param { | |
245 | struct ipu_cpmem_word word[2]; | |
246 | }; | |
247 | ||
248 | void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v); | |
249 | u32 ipu_ch_param_read_field(struct ipu_ch_param __iomem *base, u32 wbs); | |
250 | struct ipu_ch_param __iomem *ipu_get_cpmem(struct ipuv3_channel *channel); | |
251 | void ipu_ch_param_dump(struct ipu_ch_param __iomem *p); | |
252 | ||
253 | static inline void ipu_ch_param_zero(struct ipu_ch_param __iomem *p) | |
254 | { | |
255 | int i; | |
256 | void __iomem *base = p; | |
257 | ||
258 | for (i = 0; i < sizeof(*p) / sizeof(u32); i++) | |
259 | writel(0, base + i * sizeof(u32)); | |
260 | } | |
261 | ||
262 | static inline void ipu_cpmem_set_buffer(struct ipu_ch_param __iomem *p, | |
263 | int bufnum, dma_addr_t buf) | |
264 | { | |
265 | if (bufnum) | |
266 | ipu_ch_param_write_field(p, IPU_FIELD_EBA1, buf >> 3); | |
267 | else | |
268 | ipu_ch_param_write_field(p, IPU_FIELD_EBA0, buf >> 3); | |
269 | } | |
270 | ||
271 | static inline void ipu_cpmem_set_resolution(struct ipu_ch_param __iomem *p, | |
272 | int xres, int yres) | |
273 | { | |
274 | ipu_ch_param_write_field(p, IPU_FIELD_FW, xres - 1); | |
275 | ipu_ch_param_write_field(p, IPU_FIELD_FH, yres - 1); | |
276 | } | |
277 | ||
278 | static inline void ipu_cpmem_set_stride(struct ipu_ch_param __iomem *p, | |
279 | int stride) | |
280 | { | |
281 | ipu_ch_param_write_field(p, IPU_FIELD_SLY, stride - 1); | |
282 | } | |
283 | ||
284 | void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel); | |
285 | ||
286 | struct ipu_rgb { | |
287 | struct fb_bitfield red; | |
288 | struct fb_bitfield green; | |
289 | struct fb_bitfield blue; | |
290 | struct fb_bitfield transp; | |
291 | int bits_per_pixel; | |
292 | }; | |
293 | ||
294 | struct ipu_image { | |
295 | struct v4l2_pix_format pix; | |
296 | struct v4l2_rect rect; | |
297 | dma_addr_t phys; | |
298 | }; | |
299 | ||
300 | int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem *p, | |
301 | int width); | |
302 | ||
303 | int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *, | |
e56af866 | 304 | const struct ipu_rgb *rgb); |
aecfbdb1 SH |
305 | |
306 | static inline void ipu_cpmem_interlaced_scan(struct ipu_ch_param *p, | |
307 | int stride) | |
308 | { | |
309 | ipu_ch_param_write_field(p, IPU_FIELD_SO, 1); | |
310 | ipu_ch_param_write_field(p, IPU_FIELD_ILO, stride / 8); | |
311 | ipu_ch_param_write_field(p, IPU_FIELD_SLY, (stride * 2) - 1); | |
312 | }; | |
313 | ||
314 | void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem *p, u32 pixel_format, | |
315 | int stride, int height); | |
6cadd88a FE |
316 | void ipu_cpmem_set_yuv_interleaved(struct ipu_ch_param __iomem *p, |
317 | u32 pixel_format); | |
aecfbdb1 SH |
318 | void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem *p, |
319 | u32 pixel_format, int stride, int u_offset, int v_offset); | |
320 | int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 pixelformat); | |
321 | int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem, | |
322 | struct ipu_image *image); | |
323 | ||
7cb17797 | 324 | enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc); |
aecfbdb1 SH |
325 | enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat); |
326 | ||
327 | static inline void ipu_cpmem_set_burstsize(struct ipu_ch_param __iomem *p, | |
328 | int burstsize) | |
329 | { | |
330 | ipu_ch_param_write_field(p, IPU_FIELD_NPB, burstsize - 1); | |
331 | }; | |
332 | ||
333 | struct ipu_client_platformdata { | |
334 | int di; | |
335 | int dc; | |
336 | int dp; | |
337 | int dmfc; | |
338 | int dma[2]; | |
339 | }; | |
340 | ||
341 | #endif /* __DRM_IPU_H__ */ |