gas/
[deliverable/binutils-gdb.git] / include / xtensa-config.h
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e0001a05 1/* Xtensa configuration settings.
43cd72b9 2 Copyright (C) 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
4
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5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
e0001a05 9
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10 This program is distributed in the hope that it will be useful, but
11 WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 General Public License for more details.
e0001a05 14
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15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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18
19#ifndef XTENSA_CONFIG_H
20#define XTENSA_CONFIG_H
21
22/* The macros defined here match those with the same names in the Xtensa
23 compile-time HAL (Hardware Abstraction Layer). Please refer to the
24 Xtensa System Software Reference Manual for documentation of these
25 macros. */
26
05235f71 27#undef XCHAL_HAVE_BE
e0001a05 28#define XCHAL_HAVE_BE 1
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29
30#undef XCHAL_HAVE_DENSITY
e0001a05 31#define XCHAL_HAVE_DENSITY 1
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32
33#undef XCHAL_HAVE_CONST16
902695bc 34#define XCHAL_HAVE_CONST16 0
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35
36#undef XCHAL_HAVE_ABS
902695bc 37#define XCHAL_HAVE_ABS 1
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38
39#undef XCHAL_HAVE_ADDX
902695bc 40#define XCHAL_HAVE_ADDX 1
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41
42#undef XCHAL_HAVE_L32R
902695bc 43#define XCHAL_HAVE_L32R 1
05235f71 44
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45#undef XSHAL_USE_ABSOLUTE_LITERALS
46#define XSHAL_USE_ABSOLUTE_LITERALS 0
47
05235f71 48#undef XCHAL_HAVE_MAC16
e0001a05 49#define XCHAL_HAVE_MAC16 0
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50
51#undef XCHAL_HAVE_MUL16
e0001a05 52#define XCHAL_HAVE_MUL16 0
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53
54#undef XCHAL_HAVE_MUL32
e0001a05 55#define XCHAL_HAVE_MUL32 0
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56
57#undef XCHAL_HAVE_DIV32
e0001a05 58#define XCHAL_HAVE_DIV32 0
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59
60#undef XCHAL_HAVE_NSA
e0001a05 61#define XCHAL_HAVE_NSA 1
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62
63#undef XCHAL_HAVE_MINMAX
e0001a05 64#define XCHAL_HAVE_MINMAX 0
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65
66#undef XCHAL_HAVE_SEXT
e0001a05 67#define XCHAL_HAVE_SEXT 0
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68
69#undef XCHAL_HAVE_LOOPS
e0001a05 70#define XCHAL_HAVE_LOOPS 1
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71
72#undef XCHAL_HAVE_BOOLEANS
e0001a05 73#define XCHAL_HAVE_BOOLEANS 0
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74
75#undef XCHAL_HAVE_FP
e0001a05 76#define XCHAL_HAVE_FP 0
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77
78#undef XCHAL_HAVE_FP_DIV
e0001a05 79#define XCHAL_HAVE_FP_DIV 0
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80
81#undef XCHAL_HAVE_FP_RECIP
e0001a05 82#define XCHAL_HAVE_FP_RECIP 0
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83
84#undef XCHAL_HAVE_FP_SQRT
e0001a05 85#define XCHAL_HAVE_FP_SQRT 0
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86
87#undef XCHAL_HAVE_FP_RSQRT
e0001a05 88#define XCHAL_HAVE_FP_RSQRT 0
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89
90#undef XCHAL_HAVE_WINDOWED
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91#define XCHAL_HAVE_WINDOWED 1
92
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93#undef XCHAL_HAVE_PREDICTED_BRANCHES
94#define XCHAL_HAVE_PREDICTED_BRANCHES 0
95
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96
97#undef XCHAL_ICACHE_SIZE
e0001a05 98#define XCHAL_ICACHE_SIZE 8192
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99
100#undef XCHAL_DCACHE_SIZE
e0001a05 101#define XCHAL_DCACHE_SIZE 8192
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102
103#undef XCHAL_ICACHE_LINESIZE
e0001a05 104#define XCHAL_ICACHE_LINESIZE 16
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105
106#undef XCHAL_DCACHE_LINESIZE
e0001a05 107#define XCHAL_DCACHE_LINESIZE 16
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108
109#undef XCHAL_ICACHE_LINEWIDTH
e0001a05 110#define XCHAL_ICACHE_LINEWIDTH 4
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111
112#undef XCHAL_DCACHE_LINEWIDTH
e0001a05 113#define XCHAL_DCACHE_LINEWIDTH 4
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114
115#undef XCHAL_DCACHE_IS_WRITEBACK
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116#define XCHAL_DCACHE_IS_WRITEBACK 0
117
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118
119#undef XCHAL_HAVE_MMU
e0001a05 120#define XCHAL_HAVE_MMU 1
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121
122#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
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123#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
124
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125
126#undef XCHAL_HAVE_DEBUG
e0001a05 127#define XCHAL_HAVE_DEBUG 1
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128
129#undef XCHAL_NUM_IBREAK
e0001a05 130#define XCHAL_NUM_IBREAK 2
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131
132#undef XCHAL_NUM_DBREAK
e0001a05 133#define XCHAL_NUM_DBREAK 2
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134
135#undef XCHAL_DEBUGLEVEL
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136#define XCHAL_DEBUGLEVEL 4
137
05235f71 138
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139#undef XCHAL_INST_FETCH_WIDTH
140#define XCHAL_INST_FETCH_WIDTH 4
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141
142#endif /* !XTENSA_CONFIG_H */
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