x86: don't accept FI{LD,STP,STTP}LL in Intel syntax mode
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
672a349b
JB
12020-03-06 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
4 * i386-tbl.h: Re-generate.
5
4ed21b58
JB
62020-03-06 Jan Beulich <jbeulich@suse.com>
7
8 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
9 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
10 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
11 VexW0 on SSE2AVX variants.
12 (vmovq): Drop NoRex64 from XMM/XMM variants.
13 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
14 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
15 applicable use VexW0.
16 * i386-tbl.h: Re-generate.
17
643bb870
JB
182020-03-06 Jan Beulich <jbeulich@suse.com>
19
20 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
21 * i386-opc.h (Rex64): Delete.
22 (struct i386_opcode_modifier): Remove rex64 field.
23 * i386-opc.tbl (crc32): Drop Rex64.
24 Replace Rex64 with Size64 everywhere else.
25 * i386-tbl.h: Re-generate.
26
a23b33b3
JB
272020-03-06 Jan Beulich <jbeulich@suse.com>
28
29 * i386-dis.c (OP_E_memory): Exclude recording of used address
30 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
31 addressed memory operands for MPX insns.
32
a0497384
JB
332020-03-06 Jan Beulich <jbeulich@suse.com>
34
35 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
36 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
37 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
38 (ptwrite): Split into non-64-bit and 64-bit forms.
39 * i386-tbl.h: Re-generate.
40
b630c145
JB
412020-03-06 Jan Beulich <jbeulich@suse.com>
42
43 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
44 template.
45 * i386-tbl.h: Re-generate.
46
a847e322
JB
472020-03-04 Jan Beulich <jbeulich@suse.com>
48
49 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
50 (prefix_table): Move vmmcall here. Add vmgexit.
51 (rm_table): Replace vmmcall entry by prefix_table[] escape.
52 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
53 (cpu_flags): Add CpuSEV_ES entry.
54 * i386-opc.h (CpuSEV_ES): New.
55 (union i386_cpu_flags): Add cpusev_es field.
56 * i386-opc.tbl (vmgexit): New.
57 * i386-init.h, i386-tbl.h: Re-generate.
58
3cd7f3e3
L
592020-03-03 H.J. Lu <hongjiu.lu@intel.com>
60
61 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
62 with MnemonicSize.
63 * i386-opc.h (IGNORESIZE): New.
64 (DEFAULTSIZE): Likewise.
65 (IgnoreSize): Removed.
66 (DefaultSize): Likewise.
67 (MnemonicSize): New.
68 (i386_opcode_modifier): Replace ignoresize/defaultsize with
69 mnemonicsize.
70 * i386-opc.tbl (IgnoreSize): New.
71 (DefaultSize): Likewise.
72 * i386-tbl.h: Regenerated.
73
b8ba1385
SB
742020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
75
76 PR 25627
77 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
78 instructions.
79
10d97a0f
L
802020-03-03 H.J. Lu <hongjiu.lu@intel.com>
81
82 PR gas/25622
83 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
84 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
85 * i386-tbl.h: Regenerated.
86
dc1e8a47
AM
872020-02-26 Alan Modra <amodra@gmail.com>
88
89 * aarch64-asm.c: Indent labels correctly.
90 * aarch64-dis.c: Likewise.
91 * aarch64-gen.c: Likewise.
92 * aarch64-opc.c: Likewise.
93 * alpha-dis.c: Likewise.
94 * i386-dis.c: Likewise.
95 * nds32-asm.c: Likewise.
96 * nfp-dis.c: Likewise.
97 * visium-dis.c: Likewise.
98
265b4673
CZ
992020-02-25 Claudiu Zissulescu <claziss@gmail.com>
100
101 * arc-regs.h (int_vector_base): Make it available for all ARC
102 CPUs.
103
bd0cf5a6
NC
1042020-02-20 Nelson Chu <nelson.chu@sifive.com>
105
106 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
107 changed.
108
fa164239
JW
1092020-02-19 Nelson Chu <nelson.chu@sifive.com>
110
111 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
112 c.mv/c.li if rs1 is zero.
113
272a84b1
L
1142020-02-17 H.J. Lu <hongjiu.lu@intel.com>
115
116 * i386-gen.c (cpu_flag_init): Replace CpuABM with
117 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
118 CPU_POPCNT_FLAGS.
119 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
120 * i386-opc.h (CpuABM): Removed.
121 (CpuPOPCNT): New.
122 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
123 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
124 popcnt. Remove CpuABM from lzcnt.
125 * i386-init.h: Regenerated.
126 * i386-tbl.h: Likewise.
127
1f730c46
JB
1282020-02-17 Jan Beulich <jbeulich@suse.com>
129
130 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
131 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
132 VexW1 instead of open-coding them.
133 * i386-tbl.h: Re-generate.
134
c8f8eebc
JB
1352020-02-17 Jan Beulich <jbeulich@suse.com>
136
137 * i386-opc.tbl (AddrPrefixOpReg): Define.
138 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
139 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
140 templates. Drop NoRex64.
141 * i386-tbl.h: Re-generate.
142
b9915cbc
JB
1432020-02-17 Jan Beulich <jbeulich@suse.com>
144
145 PR gas/6518
146 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
147 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
148 into Intel syntax instance (with Unpsecified) and AT&T one
149 (without).
150 (vcvtneps2bf16): Likewise, along with folding the two so far
151 separate ones.
152 * i386-tbl.h: Re-generate.
153
ce504911
L
1542020-02-16 H.J. Lu <hongjiu.lu@intel.com>
155
156 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
157 CPU_ANY_SSE4A_FLAGS.
158
dabec65d
AM
1592020-02-17 Alan Modra <amodra@gmail.com>
160
161 * i386-gen.c (cpu_flag_init): Correct last change.
162
af5c13b0
L
1632020-02-16 H.J. Lu <hongjiu.lu@intel.com>
164
165 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
166 CPU_ANY_SSE4_FLAGS.
167
6867aac0
L
1682020-02-14 H.J. Lu <hongjiu.lu@intel.com>
169
170 * i386-opc.tbl (movsx): Remove Intel syntax comments.
171 (movzx): Likewise.
172
65fca059
JB
1732020-02-14 Jan Beulich <jbeulich@suse.com>
174
175 PR gas/25438
176 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
177 destination for Cpu64-only variant.
178 (movzx): Fold patterns.
179 * i386-tbl.h: Re-generate.
180
7deea9aa
JB
1812020-02-13 Jan Beulich <jbeulich@suse.com>
182
183 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
184 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
185 CPU_ANY_SSE4_FLAGS entry.
186 * i386-init.h: Re-generate.
187
6c0946d0
JB
1882020-02-12 Jan Beulich <jbeulich@suse.com>
189
190 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
191 with Unspecified, making the present one AT&T syntax only.
192 * i386-tbl.h: Re-generate.
193
ddb56fe6
JB
1942020-02-12 Jan Beulich <jbeulich@suse.com>
195
196 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
197 * i386-tbl.h: Re-generate.
198
5990e377
JB
1992020-02-12 Jan Beulich <jbeulich@suse.com>
200
201 PR gas/24546
202 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
203 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
204 Amd64 and Intel64 templates.
205 (call, jmp): Likewise for far indirect variants. Dro
206 Unspecified.
207 * i386-tbl.h: Re-generate.
208
50128d0c
JB
2092020-02-11 Jan Beulich <jbeulich@suse.com>
210
211 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
212 * i386-opc.h (ShortForm): Delete.
213 (struct i386_opcode_modifier): Remove shortform field.
214 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
215 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
216 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
217 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
218 Drop ShortForm.
219 * i386-tbl.h: Re-generate.
220
1e05b5c4
JB
2212020-02-11 Jan Beulich <jbeulich@suse.com>
222
223 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
224 fucompi): Drop ShortForm from operand-less templates.
225 * i386-tbl.h: Re-generate.
226
2f5dd314
AM
2272020-02-11 Alan Modra <amodra@gmail.com>
228
229 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
230 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
231 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
232 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
233 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
234
5aae9ae9
MM
2352020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
236
237 * arm-dis.c (print_insn_cde): Define 'V' parse character.
238 (cde_opcodes): Add VCX* instructions.
239
4934a27c
MM
2402020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
241 Matthew Malcomson <matthew.malcomson@arm.com>
242
243 * arm-dis.c (struct cdeopcode32): New.
244 (CDE_OPCODE): New macro.
245 (cde_opcodes): New disassembly table.
246 (regnames): New option to table.
247 (cde_coprocs): New global variable.
248 (print_insn_cde): New
249 (print_insn_thumb32): Use print_insn_cde.
250 (parse_arm_disassembler_options): Parse coprocN args.
251
4b5aaf5f
L
2522020-02-10 H.J. Lu <hongjiu.lu@intel.com>
253
254 PR gas/25516
255 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
256 with ISA64.
257 * i386-opc.h (AMD64): Removed.
258 (Intel64): Likewose.
259 (AMD64): New.
260 (INTEL64): Likewise.
261 (INTEL64ONLY): Likewise.
262 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
263 * i386-opc.tbl (Amd64): New.
264 (Intel64): Likewise.
265 (Intel64Only): Likewise.
266 Replace AMD64 with Amd64. Update sysenter/sysenter with
267 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
268 * i386-tbl.h: Regenerated.
269
9fc0b501
SB
2702020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
271
272 PR 25469
273 * z80-dis.c: Add support for GBZ80 opcodes.
274
c5d7be0c
AM
2752020-02-04 Alan Modra <amodra@gmail.com>
276
277 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
278
44e4546f
AM
2792020-02-03 Alan Modra <amodra@gmail.com>
280
281 * m32c-ibld.c: Regenerate.
282
b2b1453a
AM
2832020-02-01 Alan Modra <amodra@gmail.com>
284
285 * frv-ibld.c: Regenerate.
286
4102be5c
JB
2872020-01-31 Jan Beulich <jbeulich@suse.com>
288
289 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
290 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
291 (OP_E_memory): Replace xmm_mdq_mode case label by
292 vex_scalar_w_dq_mode one.
293 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
294
825bd36c
JB
2952020-01-31 Jan Beulich <jbeulich@suse.com>
296
297 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
298 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
299 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
300 (intel_operand_size): Drop vex_w_dq_mode case label.
301
c3036ed0
RS
3022020-01-31 Richard Sandiford <richard.sandiford@arm.com>
303
304 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
305 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
306
0c115f84
AM
3072020-01-30 Alan Modra <amodra@gmail.com>
308
309 * m32c-ibld.c: Regenerate.
310
bd434cc4
JM
3112020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
312
313 * bpf-opc.c: Regenerate.
314
aeab2b26
JB
3152020-01-30 Jan Beulich <jbeulich@suse.com>
316
317 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
318 (dis386): Use them to replace C2/C3 table entries.
319 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
320 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
321 ones. Use Size64 instead of DefaultSize on Intel64 ones.
322 * i386-tbl.h: Re-generate.
323
62b3f548
JB
3242020-01-30 Jan Beulich <jbeulich@suse.com>
325
326 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
327 forms.
328 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
329 DefaultSize.
330 * i386-tbl.h: Re-generate.
331
1bd8ae10
AM
3322020-01-30 Alan Modra <amodra@gmail.com>
333
334 * tic4x-dis.c (tic4x_dp): Make unsigned.
335
bc31405e
L
3362020-01-27 H.J. Lu <hongjiu.lu@intel.com>
337 Jan Beulich <jbeulich@suse.com>
338
339 PR binutils/25445
340 * i386-dis.c (MOVSXD_Fixup): New function.
341 (movsxd_mode): New enum.
342 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
343 (intel_operand_size): Handle movsxd_mode.
344 (OP_E_register): Likewise.
345 (OP_G): Likewise.
346 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
347 register on movsxd. Add movsxd with 16-bit destination register
348 for AMD64 and Intel64 ISAs.
349 * i386-tbl.h: Regenerated.
350
7568c93b
TC
3512020-01-27 Tamar Christina <tamar.christina@arm.com>
352
353 PR 25403
354 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
355 * aarch64-asm-2.c: Regenerate
356 * aarch64-dis-2.c: Likewise.
357 * aarch64-opc-2.c: Likewise.
358
c006a730
JB
3592020-01-21 Jan Beulich <jbeulich@suse.com>
360
361 * i386-opc.tbl (sysret): Drop DefaultSize.
362 * i386-tbl.h: Re-generate.
363
c906a69a
JB
3642020-01-21 Jan Beulich <jbeulich@suse.com>
365
366 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
367 Dword.
368 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
369 * i386-tbl.h: Re-generate.
370
26916852
NC
3712020-01-20 Nick Clifton <nickc@redhat.com>
372
373 * po/de.po: Updated German translation.
374 * po/pt_BR.po: Updated Brazilian Portuguese translation.
375 * po/uk.po: Updated Ukranian translation.
376
4d6cbb64
AM
3772020-01-20 Alan Modra <amodra@gmail.com>
378
379 * hppa-dis.c (fput_const): Remove useless cast.
380
2bddb71a
AM
3812020-01-20 Alan Modra <amodra@gmail.com>
382
383 * arm-dis.c (print_insn_arm): Wrap 'T' value.
384
1b1bb2c6
NC
3852020-01-18 Nick Clifton <nickc@redhat.com>
386
387 * configure: Regenerate.
388 * po/opcodes.pot: Regenerate.
389
ae774686
NC
3902020-01-18 Nick Clifton <nickc@redhat.com>
391
392 Binutils 2.34 branch created.
393
07f1f3aa
CB
3942020-01-17 Christian Biesinger <cbiesinger@google.com>
395
396 * opintl.h: Fix spelling error (seperate).
397
42e04b36
L
3982020-01-17 H.J. Lu <hongjiu.lu@intel.com>
399
400 * i386-opc.tbl: Add {vex} pseudo prefix.
401 * i386-tbl.h: Regenerated.
402
2da2eaf4
AV
4032020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
404
405 PR 25376
406 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
407 (neon_opcodes): Likewise.
408 (select_arm_features): Make sure we enable MVE bits when selecting
409 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
410 any architecture.
411
d0849eed
JB
4122020-01-16 Jan Beulich <jbeulich@suse.com>
413
414 * i386-opc.tbl: Drop stale comment from XOP section.
415
9cf70a44
JB
4162020-01-16 Jan Beulich <jbeulich@suse.com>
417
418 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
419 (extractps): Add VexWIG to SSE2AVX forms.
420 * i386-tbl.h: Re-generate.
421
4814632e
JB
4222020-01-16 Jan Beulich <jbeulich@suse.com>
423
424 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
425 Size64 from and use VexW1 on SSE2AVX forms.
426 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
427 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
428 * i386-tbl.h: Re-generate.
429
aad09917
AM
4302020-01-15 Alan Modra <amodra@gmail.com>
431
432 * tic4x-dis.c (tic4x_version): Make unsigned long.
433 (optab, optab_special, registernames): New file scope vars.
434 (tic4x_print_register): Set up registernames rather than
435 malloc'd registertable.
436 (tic4x_disassemble): Delete optable and optable_special. Use
437 optab and optab_special instead. Throw away old optab,
438 optab_special and registernames when info->mach changes.
439
7a6bf3be
SB
4402020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
441
442 PR 25377
443 * z80-dis.c (suffix): Use .db instruction to generate double
444 prefix.
445
ca1eaac0
AM
4462020-01-14 Alan Modra <amodra@gmail.com>
447
448 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
449 values to unsigned before shifting.
450
1d67fe3b
TT
4512020-01-13 Thomas Troeger <tstroege@gmx.de>
452
453 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
454 flow instructions.
455 (print_insn_thumb16, print_insn_thumb32): Likewise.
456 (print_insn): Initialize the insn info.
457 * i386-dis.c (print_insn): Initialize the insn info fields, and
458 detect jumps.
459
5e4f7e05
CZ
4602012-01-13 Claudiu Zissulescu <claziss@gmail.com>
461
462 * arc-opc.c (C_NE): Make it required.
463
b9fe6b8a
CZ
4642012-01-13 Claudiu Zissulescu <claziss@gmail.com>
465
466 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
467 reserved register name.
468
90dee485
AM
4692020-01-13 Alan Modra <amodra@gmail.com>
470
471 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
472 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
473
febda64f
AM
4742020-01-13 Alan Modra <amodra@gmail.com>
475
476 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
477 result of wasm_read_leb128 in a uint64_t and check that bits
478 are not lost when copying to other locals. Use uint32_t for
479 most locals. Use PRId64 when printing int64_t.
480
df08b588
AM
4812020-01-13 Alan Modra <amodra@gmail.com>
482
483 * score-dis.c: Formatting.
484 * score7-dis.c: Formatting.
485
b2c759ce
AM
4862020-01-13 Alan Modra <amodra@gmail.com>
487
488 * score-dis.c (print_insn_score48): Use unsigned variables for
489 unsigned values. Don't left shift negative values.
490 (print_insn_score32): Likewise.
491 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
492
5496abe1
AM
4932020-01-13 Alan Modra <amodra@gmail.com>
494
495 * tic4x-dis.c (tic4x_print_register): Remove dead code.
496
202e762b
AM
4972020-01-13 Alan Modra <amodra@gmail.com>
498
499 * fr30-ibld.c: Regenerate.
500
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5012020-01-13 Alan Modra <amodra@gmail.com>
502
503 * xgate-dis.c (print_insn): Don't left shift signed value.
504 (ripBits): Formatting, use 1u.
505
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5062020-01-10 Alan Modra <amodra@gmail.com>
507
508 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
509 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
510
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5112020-01-10 Alan Modra <amodra@gmail.com>
512
513 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
514 and XRREG value earlier to avoid a shift with negative exponent.
515 * m10200-dis.c (disassemble): Similarly.
516
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5172020-01-09 Nick Clifton <nickc@redhat.com>
518
519 PR 25224
520 * z80-dis.c (ld_ii_ii): Use correct cast.
521
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5222020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
523
524 PR 25224
525 * z80-dis.c (ld_ii_ii): Use character constant when checking
526 opcode byte value.
527
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JB
5282020-01-09 Jan Beulich <jbeulich@suse.com>
529
530 * i386-dis.c (SEP_Fixup): New.
531 (SEP): Define.
532 (dis386_twobyte): Use it for sysenter/sysexit.
533 (enum x86_64_isa): Change amd64 enumerator to value 1.
534 (OP_J): Compare isa64 against intel64 instead of amd64.
535 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
536 forms.
537 * i386-tbl.h: Re-generate.
538
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5392020-01-08 Alan Modra <amodra@gmail.com>
540
541 * z8k-dis.c: Include libiberty.h
542 (instr_data_s): Make max_fetched unsigned.
543 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
544 Don't exceed byte_info bounds.
545 (output_instr): Make num_bytes unsigned.
546 (unpack_instr): Likewise for nibl_count and loop.
547 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
548 idx unsigned.
549 * z8k-opc.h: Regenerate.
550
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5512020-01-07 Shahab Vahedi <shahab@synopsys.com>
552
553 * arc-tbl.h (llock): Use 'LLOCK' as class.
554 (llockd): Likewise.
555 (scond): Use 'SCOND' as class.
556 (scondd): Likewise.
557 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
558 (scondd): Likewise.
559
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5602020-01-06 Alan Modra <amodra@gmail.com>
561
562 * m32c-ibld.c: Regenerate.
563
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5642020-01-06 Alan Modra <amodra@gmail.com>
565
566 PR 25344
567 * z80-dis.c (suffix): Don't use a local struct buffer copy.
568 Peek at next byte to prevent recursion on repeated prefix bytes.
569 Ensure uninitialised "mybuf" is not accessed.
570 (print_insn_z80): Don't zero n_fetch and n_used here,..
571 (print_insn_z80_buf): ..do it here instead.
572
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5732020-01-04 Alan Modra <amodra@gmail.com>
574
575 * m32r-ibld.c: Regenerate.
576
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5772020-01-04 Alan Modra <amodra@gmail.com>
578
579 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
580
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5812020-01-04 Alan Modra <amodra@gmail.com>
582
583 * crx-dis.c (match_opcode): Avoid shift left of signed value.
584
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5852020-01-04 Alan Modra <amodra@gmail.com>
586
587 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
588
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5892020-01-03 Jan Beulich <jbeulich@suse.com>
590
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591 * aarch64-tbl.h (aarch64_opcode_table): Use
592 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
593
5942020-01-03 Jan Beulich <jbeulich@suse.com>
595
596 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB
597 forms of SUDOT and USDOT.
598
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5992020-01-03 Jan Beulich <jbeulich@suse.com>
600
5437a02a 601 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
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JB
602 uzip{1,2}.
603 * opcodes/aarch64-dis-2.c: Re-generate.
604
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6052020-01-03 Jan Beulich <jbeulich@suse.com>
606
5437a02a 607 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
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608 FMMLA encoding.
609 * opcodes/aarch64-dis-2.c: Re-generate.
610
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6112020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
612
613 * z80-dis.c: Add support for eZ80 and Z80 instructions.
614
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6152020-01-01 Alan Modra <amodra@gmail.com>
616
617 Update year range in copyright notice of all files.
618
0b114740 619For older changes see ChangeLog-2019
3499769a 620\f
0b114740 621Copyright (C) 2020 Free Software Foundation, Inc.
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622
623Copying and distribution of this file, with or without modification,
624are permitted in any medium without royalty provided the copyright
625notice and this notice are preserved.
626
627Local Variables:
628mode: change-log
629left-margin: 8
630fill-column: 74
631version-control: never
632End:
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