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Power10 128-bit binary integer operations
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c7d7aea2
AM		 12020-05-11 Alan Modra <amodra@gmail.com>
2
3 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
4 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
5 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
6 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
7 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
8
94ba9882
AM		 92020-05-11 Alan Modra <amodra@gmail.com>
10
11 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
12 (XTP, DQXP, DQXP_MASK): Define.
13 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
14 (prefix_opcodes): Add plxvp and pstxvp.
15
f4791f1a
AM		 162020-05-11 Alan Modra <amodra@gmail.com>
17
18 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
19 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
20 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
21
3ff0a5ba
PB		 222020-05-11 Peter Bergner <bergner@linux.ibm.com>
23
24 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
25
afef4fe9
PB		 262020-05-11 Peter Bergner <bergner@linux.ibm.com>
27
28 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
29 (L1OPT): Define.
30 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
31
1224c05d
PB		 322020-05-11 Peter Bergner <bergner@linux.ibm.com>
33
34 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
35
6bbb0c05
AM		 362020-05-11 Alan Modra <amodra@gmail.com>
37
38 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
39
7c1f4227
AM		 402020-05-11 Alan Modra <amodra@gmail.com>
41
42 * ppc-dis.c (ppc_opts): Add "power10" entry.
43 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
44 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
45
73199c2b
NC		 462020-05-11 Nick Clifton <nickc@redhat.com>
47
48 * po/fr.po: Updated French translation.
49
09c1e68a
AC		 502020-04-30 Alex Coplan <alex.coplan@arm.com>
51
52 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
53 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
54 (operand_general_constraint_met_p): validate
55 AARCH64_OPND_UNDEFINED.
56 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
57 for FLD_imm16_2.
58 * aarch64-asm-2.c: Regenerated.
59 * aarch64-dis-2.c: Regenerated.
60 * aarch64-opc-2.c: Regenerated.
61
9654d51a
NC		 622020-04-29 Nick Clifton <nickc@redhat.com>
63
64 PR 22699
65 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
66 and SETRC insns.
67
c2e71e57
NC		 682020-04-29 Nick Clifton <nickc@redhat.com>
69
70 * po/sv.po: Updated Swedish translation.
71
5c936ef5
NC		 722020-04-29 Nick Clifton <nickc@redhat.com>
73
74 PR 22699
75 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
76 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
77 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
78 IMM0_8U case.
79
bb2a1453
AS		 802020-04-21 Andreas Schwab <schwab@linux-m68k.org>
81
82 PR 25848
83 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
84 cmpi only on m68020up and cpu32.
85
c2e5c986
SD		 862020-04-20 Sudakshina Das <sudi.das@arm.com>
87
88 * aarch64-asm.c (aarch64_ins_none): New.
89 * aarch64-asm.h (ins_none): New declaration.
90 * aarch64-dis.c (aarch64_ext_none): New.
91 * aarch64-dis.h (ext_none): New declaration.
92 * aarch64-opc.c (aarch64_print_operand): Update case for
93 AARCH64_OPND_BARRIER_PSB.
94 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
95 (AARCH64_OPERANDS): Update inserter/extracter for
96 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
97 * aarch64-asm-2.c: Regenerated.
98 * aarch64-dis-2.c: Regenerated.
99 * aarch64-opc-2.c: Regenerated.
100
8a6e1d1d
SD		 1012020-04-20 Sudakshina Das <sudi.das@arm.com>
102
103 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
104 (aarch64_feature_ras, RAS): Likewise.
105 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
106 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
107 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
108 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
109 * aarch64-asm-2.c: Regenerated.
110 * aarch64-dis-2.c: Regenerated.
111 * aarch64-opc-2.c: Regenerated.
112
e409955d
FS		 1132020-04-17 Fredrik Strupe <fredrik@strupe.net>
114
115 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
116 (print_insn_neon): Support disassembly of conditional
117 instructions.
118
c54a9b56
DF		 1192020-02-16 David Faust <david.faust@oracle.com>
120
121 * bpf-desc.c: Regenerate.
122 * bpf-desc.h: Likewise.
123 * bpf-opc.c: Regenerate.
124 * bpf-opc.h: Likewise.
125
bb651e8b
CL		 1262020-04-07 Lili Cui <lili.cui@intel.com>
127
128 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
129 (prefix_table): New instructions (see prefixes above).
130 (rm_table): Likewise
131 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
132 CPU_ANY_TSXLDTRK_FLAGS.
133 (cpu_flags): Add CpuTSXLDTRK.
134 * i386-opc.h (enum): Add CpuTSXLDTRK.
135 (i386_cpu_flags): Add cputsxldtrk.
136 * i386-opc.tbl: Add XSUSPLDTRK insns.
137 * i386-init.h: Regenerate.
138 * i386-tbl.h: Likewise.
139
4b27d27c
L		 1402020-04-02 Lili Cui <lili.cui@intel.com>
141
142 * i386-dis.c (prefix_table): New instructions serialize.
143 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
144 CPU_ANY_SERIALIZE_FLAGS.
145 (cpu_flags): Add CpuSERIALIZE.
146 * i386-opc.h (enum): Add CpuSERIALIZE.
147 (i386_cpu_flags): Add cpuserialize.
148 * i386-opc.tbl: Add SERIALIZE insns.
149 * i386-init.h: Regenerate.
150 * i386-tbl.h: Likewise.
151
832a5807
AM		 1522020-03-26 Alan Modra <amodra@gmail.com>
153
154 * disassemble.h (opcodes_assert): Declare.
155 (OPCODES_ASSERT): Define.
156 * disassemble.c: Don't include assert.h. Include opintl.h.
157 (opcodes_assert): New function.
158 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
159 (bfd_h8_disassemble): Reduce size of data array. Correctly
160 calculate maxlen. Omit insn decoding when insn length exceeds
161 maxlen. Exit from nibble loop when looking for E, before
162 accessing next data byte. Move processing of E outside loop.
163 Replace tests of maxlen in loop with assertions.
164
4c4addbe
AM		 1652020-03-26 Alan Modra <amodra@gmail.com>
166
167 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
168
a18cd0ca
AM		 1692020-03-25 Alan Modra <amodra@gmail.com>
170
171 * z80-dis.c (suffix): Init mybuf.
172
57cb32b3
AM		 1732020-03-22 Alan Modra <amodra@gmail.com>
174
175 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
176 successflly read from section.
177
beea5cc1
AM		 1782020-03-22 Alan Modra <amodra@gmail.com>
179
180 * arc-dis.c (find_format): Use ISO C string concatenation rather
181 than line continuation within a string. Don't access needs_limm
182 before testing opcode != NULL.
183
03704c77
AM		 1842020-03-22 Alan Modra <amodra@gmail.com>
185
186 * ns32k-dis.c (print_insn_arg): Update comment.
187 (print_insn_ns32k): Reduce size of index_offset array, and
188 initialize, passing -1 to print_insn_arg for args that are not
189 an index. Don't exit arg loop early. Abort on bad arg number.
190
d1023b5d
AM		 1912020-03-22 Alan Modra <amodra@gmail.com>
192
193 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
194 * s12z-opc.c: Formatting.
195 (operands_f): Return an int.
196 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
197 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
198 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
199 (exg_sex_discrim): Likewise.
200 (create_immediate_operand, create_bitfield_operand),
201 (create_register_operand_with_size, create_register_all_operand),
202 (create_register_all16_operand, create_simple_memory_operand),
203 (create_memory_operand, create_memory_auto_operand): Don't
204 segfault on malloc failure.
205 (z_ext24_decode): Return an int status, negative on fail, zero
206 on success.
207 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
208 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
209 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
210 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
211 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
212 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
213 (loop_primitive_decode, shift_decode, psh_pul_decode),
214 (bit_field_decode): Similarly.
215 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
216 to return value, update callers.
217 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
218 Don't segfault on NULL operand.
219 (decode_operation): Return OP_INVALID on first fail.
220 (decode_s12z): Check all reads, returning -1 on fail.
221
340f3ac8
AM		 2222020-03-20 Alan Modra <amodra@gmail.com>
223
224 * metag-dis.c (print_insn_metag): Don't ignore status from
225 read_memory_func.
226
fe90ae8a
AM		 2272020-03-20 Alan Modra <amodra@gmail.com>
228
229 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
230 Initialize parts of buffer not written when handling a possible
231 2-byte insn at end of section. Don't attempt decoding of such
232 an insn by the 4-byte machinery.
233
833d919c
AM		 2342020-03-20 Alan Modra <amodra@gmail.com>
235
236 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
237 partially filled buffer. Prevent lookup of 4-byte insns when
238 only VLE 2-byte insns are possible due to section size. Print
239 ".word" rather than ".long" for 2-byte leftovers.
240
327ef784
NC		 2412020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
242
243 PR 25641
244 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
245
1673df32
JB		 2462020-03-13 Jan Beulich <jbeulich@suse.com>
247
248 * i386-dis.c (X86_64_0D): Rename to ...
249 (X86_64_0E): ... this.
250
384f3689
L		 2512020-03-09 H.J. Lu <hongjiu.lu@intel.com>
252
253 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
254 * Makefile.in: Regenerated.
255
865e2027
JB		 2562020-03-09 Jan Beulich <jbeulich@suse.com>
257
258 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
259 3-operand pseudos.
260 * i386-tbl.h: Re-generate.
261
2f13234b
JB		 2622020-03-09 Jan Beulich <jbeulich@suse.com>
263
264 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
265 vprot*, vpsha*, and vpshl*.
266 * i386-tbl.h: Re-generate.
267
3fabc179
JB		 2682020-03-09 Jan Beulich <jbeulich@suse.com>
269
270 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
271 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
272 * i386-tbl.h: Re-generate.
273
3677e4c1
JB		 2742020-03-09 Jan Beulich <jbeulich@suse.com>
275
276 * i386-gen.c (set_bitfield): Ignore zero-length field names.
277 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
278 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
279 * i386-tbl.h: Re-generate.
280
4c4898e8
JB		 2812020-03-09 Jan Beulich <jbeulich@suse.com>
282
283 * i386-gen.c (struct template_arg, struct template_instance,
284 struct template_param, struct template, templates,
285 parse_template, expand_templates): New.
286 (process_i386_opcodes): Various local variables moved to
287 expand_templates. Call parse_template and expand_templates.
288 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
289 * i386-tbl.h: Re-generate.
290
bc49bfd8
JB		 2912020-03-06 Jan Beulich <jbeulich@suse.com>
292
293 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
294 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
295 register and memory source templates. Replace VexW= by VexW*
296 where applicable.
297 * i386-tbl.h: Re-generate.
298
4873e243
JB		 2992020-03-06 Jan Beulich <jbeulich@suse.com>
300
301 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
302 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
303 * i386-tbl.h: Re-generate.
304
672a349b
JB		 3052020-03-06 Jan Beulich <jbeulich@suse.com>
306
307 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
308 * i386-tbl.h: Re-generate.
309
4ed21b58
JB		 3102020-03-06 Jan Beulich <jbeulich@suse.com>
311
312 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
313 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
314 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
315 VexW0 on SSE2AVX variants.
316 (vmovq): Drop NoRex64 from XMM/XMM variants.
317 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
318 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
319 applicable use VexW0.
320 * i386-tbl.h: Re-generate.
321
643bb870
JB		 3222020-03-06 Jan Beulich <jbeulich@suse.com>
323
324 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
325 * i386-opc.h (Rex64): Delete.
326 (struct i386_opcode_modifier): Remove rex64 field.
327 * i386-opc.tbl (crc32): Drop Rex64.
328 Replace Rex64 with Size64 everywhere else.
329 * i386-tbl.h: Re-generate.
330
a23b33b3
JB		 3312020-03-06 Jan Beulich <jbeulich@suse.com>
332
333 * i386-dis.c (OP_E_memory): Exclude recording of used address
334 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
335 addressed memory operands for MPX insns.
336
a0497384
JB		 3372020-03-06 Jan Beulich <jbeulich@suse.com>
338
339 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
340 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
341 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
342 (ptwrite): Split into non-64-bit and 64-bit forms.
343 * i386-tbl.h: Re-generate.
344
b630c145
JB		 3452020-03-06 Jan Beulich <jbeulich@suse.com>
346
347 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
348 template.
349 * i386-tbl.h: Re-generate.
350
a847e322
JB		 3512020-03-04 Jan Beulich <jbeulich@suse.com>
352
353 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
354 (prefix_table): Move vmmcall here. Add vmgexit.
355 (rm_table): Replace vmmcall entry by prefix_table[] escape.
356 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
357 (cpu_flags): Add CpuSEV_ES entry.
358 * i386-opc.h (CpuSEV_ES): New.
359 (union i386_cpu_flags): Add cpusev_es field.
360 * i386-opc.tbl (vmgexit): New.
361 * i386-init.h, i386-tbl.h: Re-generate.
362
3cd7f3e3
L		 3632020-03-03 H.J. Lu <hongjiu.lu@intel.com>
364
365 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
366 with MnemonicSize.
367 * i386-opc.h (IGNORESIZE): New.
368 (DEFAULTSIZE): Likewise.
369 (IgnoreSize): Removed.
370 (DefaultSize): Likewise.
371 (MnemonicSize): New.
372 (i386_opcode_modifier): Replace ignoresize/defaultsize with
373 mnemonicsize.
374 * i386-opc.tbl (IgnoreSize): New.
375 (DefaultSize): Likewise.
376 * i386-tbl.h: Regenerated.
377
b8ba1385
SB		 3782020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
379
380 PR 25627
381 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
382 instructions.
383
10d97a0f
L		 3842020-03-03 H.J. Lu <hongjiu.lu@intel.com>
385
386 PR gas/25622
387 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
388 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
389 * i386-tbl.h: Regenerated.
390
dc1e8a47
AM		 3912020-02-26 Alan Modra <amodra@gmail.com>
392
393 * aarch64-asm.c: Indent labels correctly.
394 * aarch64-dis.c: Likewise.
395 * aarch64-gen.c: Likewise.
396 * aarch64-opc.c: Likewise.
397 * alpha-dis.c: Likewise.
398 * i386-dis.c: Likewise.
399 * nds32-asm.c: Likewise.
400 * nfp-dis.c: Likewise.
401 * visium-dis.c: Likewise.
402
265b4673
CZ		 4032020-02-25 Claudiu Zissulescu <claziss@gmail.com>
404
405 * arc-regs.h (int_vector_base): Make it available for all ARC
406 CPUs.
407
bd0cf5a6
NC		 4082020-02-20 Nelson Chu <nelson.chu@sifive.com>
409
410 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
411 changed.
412
fa164239
JW		 4132020-02-19 Nelson Chu <nelson.chu@sifive.com>
414
415 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
416 c.mv/c.li if rs1 is zero.
417
272a84b1
L		 4182020-02-17 H.J. Lu <hongjiu.lu@intel.com>
419
420 * i386-gen.c (cpu_flag_init): Replace CpuABM with
421 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
422 CPU_POPCNT_FLAGS.
423 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
424 * i386-opc.h (CpuABM): Removed.
425 (CpuPOPCNT): New.
426 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
427 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
428 popcnt. Remove CpuABM from lzcnt.
429 * i386-init.h: Regenerated.
430 * i386-tbl.h: Likewise.
431
1f730c46
JB		 4322020-02-17 Jan Beulich <jbeulich@suse.com>
433
434 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
435 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
436 VexW1 instead of open-coding them.
437 * i386-tbl.h: Re-generate.
438
c8f8eebc
JB		 4392020-02-17 Jan Beulich <jbeulich@suse.com>
440
441 * i386-opc.tbl (AddrPrefixOpReg): Define.
442 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
443 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
444 templates. Drop NoRex64.
445 * i386-tbl.h: Re-generate.
446
b9915cbc
JB		 4472020-02-17 Jan Beulich <jbeulich@suse.com>
448
449 PR gas/6518
450 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
451 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
452 into Intel syntax instance (with Unpsecified) and AT&T one
453 (without).
454 (vcvtneps2bf16): Likewise, along with folding the two so far
455 separate ones.
456 * i386-tbl.h: Re-generate.
457
ce504911
L		 4582020-02-16 H.J. Lu <hongjiu.lu@intel.com>
459
460 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
461 CPU_ANY_SSE4A_FLAGS.
462
dabec65d
AM		 4632020-02-17 Alan Modra <amodra@gmail.com>
464
465 * i386-gen.c (cpu_flag_init): Correct last change.
466
af5c13b0
L		 4672020-02-16 H.J. Lu <hongjiu.lu@intel.com>
468
469 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
470 CPU_ANY_SSE4_FLAGS.
471
6867aac0
L		 4722020-02-14 H.J. Lu <hongjiu.lu@intel.com>
473
474 * i386-opc.tbl (movsx): Remove Intel syntax comments.
475 (movzx): Likewise.
476
65fca059
JB		 4772020-02-14 Jan Beulich <jbeulich@suse.com>
478
479 PR gas/25438
480 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
481 destination for Cpu64-only variant.
482 (movzx): Fold patterns.
483 * i386-tbl.h: Re-generate.
484
7deea9aa
JB		 4852020-02-13 Jan Beulich <jbeulich@suse.com>
486
487 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
488 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
489 CPU_ANY_SSE4_FLAGS entry.
490 * i386-init.h: Re-generate.
491
6c0946d0
JB		 4922020-02-12 Jan Beulich <jbeulich@suse.com>
493
494 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
495 with Unspecified, making the present one AT&T syntax only.
496 * i386-tbl.h: Re-generate.
497
ddb56fe6
JB		 4982020-02-12 Jan Beulich <jbeulich@suse.com>
499
500 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
501 * i386-tbl.h: Re-generate.
502
5990e377
JB		 5032020-02-12 Jan Beulich <jbeulich@suse.com>
504
505 PR gas/24546
506 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
507 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
508 Amd64 and Intel64 templates.
509 (call, jmp): Likewise for far indirect variants. Dro
510 Unspecified.
511 * i386-tbl.h: Re-generate.
512
50128d0c
JB		 5132020-02-11 Jan Beulich <jbeulich@suse.com>
514
515 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
516 * i386-opc.h (ShortForm): Delete.
517 (struct i386_opcode_modifier): Remove shortform field.
518 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
519 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
520 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
521 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
522 Drop ShortForm.
523 * i386-tbl.h: Re-generate.
524
1e05b5c4
JB		 5252020-02-11 Jan Beulich <jbeulich@suse.com>
526
527 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
528 fucompi): Drop ShortForm from operand-less templates.
529 * i386-tbl.h: Re-generate.
530
2f5dd314
AM		 5312020-02-11 Alan Modra <amodra@gmail.com>
532
533 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
534 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
535 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
536 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
537 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
538
5aae9ae9
MM		 5392020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
540
541 * arm-dis.c (print_insn_cde): Define 'V' parse character.
542 (cde_opcodes): Add VCX* instructions.
543
4934a27c
MM		 5442020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
545 Matthew Malcomson <matthew.malcomson@arm.com>
546
547 * arm-dis.c (struct cdeopcode32): New.
548 (CDE_OPCODE): New macro.
549 (cde_opcodes): New disassembly table.
550 (regnames): New option to table.
551 (cde_coprocs): New global variable.
552 (print_insn_cde): New
553 (print_insn_thumb32): Use print_insn_cde.
554 (parse_arm_disassembler_options): Parse coprocN args.
555
4b5aaf5f
L		 5562020-02-10 H.J. Lu <hongjiu.lu@intel.com>
557
558 PR gas/25516
559 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
560 with ISA64.
561 * i386-opc.h (AMD64): Removed.
562 (Intel64): Likewose.
563 (AMD64): New.
564 (INTEL64): Likewise.
565 (INTEL64ONLY): Likewise.
566 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
567 * i386-opc.tbl (Amd64): New.
568 (Intel64): Likewise.
569 (Intel64Only): Likewise.
570 Replace AMD64 with Amd64. Update sysenter/sysenter with
571 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
572 * i386-tbl.h: Regenerated.
573
9fc0b501
SB		 5742020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
575
576 PR 25469
577 * z80-dis.c: Add support for GBZ80 opcodes.
578
c5d7be0c
AM		 5792020-02-04 Alan Modra <amodra@gmail.com>
580
581 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
582
44e4546f
AM		 5832020-02-03 Alan Modra <amodra@gmail.com>
584
585 * m32c-ibld.c: Regenerate.
586
b2b1453a
AM		 5872020-02-01 Alan Modra <amodra@gmail.com>
588
589 * frv-ibld.c: Regenerate.
590
4102be5c
JB		 5912020-01-31 Jan Beulich <jbeulich@suse.com>
592
593 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
594 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
595 (OP_E_memory): Replace xmm_mdq_mode case label by
596 vex_scalar_w_dq_mode one.
597 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
598
825bd36c
JB		 5992020-01-31 Jan Beulich <jbeulich@suse.com>
600
601 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
602 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
603 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
604 (intel_operand_size): Drop vex_w_dq_mode case label.
605
c3036ed0
RS		 6062020-01-31 Richard Sandiford <richard.sandiford@arm.com>
607
608 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
609 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
610
0c115f84
AM		 6112020-01-30 Alan Modra <amodra@gmail.com>
612
613 * m32c-ibld.c: Regenerate.
614
bd434cc4
JM		 6152020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
616
617 * bpf-opc.c: Regenerate.
618
aeab2b26
JB		 6192020-01-30 Jan Beulich <jbeulich@suse.com>
620
621 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
622 (dis386): Use them to replace C2/C3 table entries.
623 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
624 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
625 ones. Use Size64 instead of DefaultSize on Intel64 ones.
626 * i386-tbl.h: Re-generate.
627
62b3f548
JB		 6282020-01-30 Jan Beulich <jbeulich@suse.com>
629
630 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
631 forms.
632 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
633 DefaultSize.
634 * i386-tbl.h: Re-generate.
635
1bd8ae10
AM		 6362020-01-30 Alan Modra <amodra@gmail.com>
637
638 * tic4x-dis.c (tic4x_dp): Make unsigned.
639
bc31405e
L		 6402020-01-27 H.J. Lu <hongjiu.lu@intel.com>
641 Jan Beulich <jbeulich@suse.com>
642
643 PR binutils/25445
644 * i386-dis.c (MOVSXD_Fixup): New function.
645 (movsxd_mode): New enum.
646 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
647 (intel_operand_size): Handle movsxd_mode.
648 (OP_E_register): Likewise.
649 (OP_G): Likewise.
650 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
651 register on movsxd. Add movsxd with 16-bit destination register
652 for AMD64 and Intel64 ISAs.
653 * i386-tbl.h: Regenerated.
654
7568c93b
TC		 6552020-01-27 Tamar Christina <tamar.christina@arm.com>
656
657 PR 25403
658 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
659 * aarch64-asm-2.c: Regenerate
660 * aarch64-dis-2.c: Likewise.
661 * aarch64-opc-2.c: Likewise.
662
c006a730
JB		 6632020-01-21 Jan Beulich <jbeulich@suse.com>
664
665 * i386-opc.tbl (sysret): Drop DefaultSize.
666 * i386-tbl.h: Re-generate.
667
c906a69a
JB		 6682020-01-21 Jan Beulich <jbeulich@suse.com>
669
670 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
671 Dword.
672 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
673 * i386-tbl.h: Re-generate.
674
26916852
NC		 6752020-01-20 Nick Clifton <nickc@redhat.com>
676
677 * po/de.po: Updated German translation.
678 * po/pt_BR.po: Updated Brazilian Portuguese translation.
679 * po/uk.po: Updated Ukranian translation.
680
4d6cbb64
AM		 6812020-01-20 Alan Modra <amodra@gmail.com>
682
683 * hppa-dis.c (fput_const): Remove useless cast.
684
2bddb71a
AM		 6852020-01-20 Alan Modra <amodra@gmail.com>
686
687 * arm-dis.c (print_insn_arm): Wrap 'T' value.
688
1b1bb2c6
NC		 6892020-01-18 Nick Clifton <nickc@redhat.com>
690
691 * configure: Regenerate.
692 * po/opcodes.pot: Regenerate.
693
ae774686
NC		 6942020-01-18 Nick Clifton <nickc@redhat.com>
695
696 Binutils 2.34 branch created.
697
07f1f3aa
CB		 6982020-01-17 Christian Biesinger <cbiesinger@google.com>
699
700 * opintl.h: Fix spelling error (seperate).
701
42e04b36
L		 7022020-01-17 H.J. Lu <hongjiu.lu@intel.com>
703
704 * i386-opc.tbl: Add {vex} pseudo prefix.
705 * i386-tbl.h: Regenerated.
706
2da2eaf4
AV		 7072020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
708
709 PR 25376
710 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
711 (neon_opcodes): Likewise.
712 (select_arm_features): Make sure we enable MVE bits when selecting
713 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
714 any architecture.
715
d0849eed
JB		 7162020-01-16 Jan Beulich <jbeulich@suse.com>
717
718 * i386-opc.tbl: Drop stale comment from XOP section.
719
9cf70a44
JB		 7202020-01-16 Jan Beulich <jbeulich@suse.com>
721
722 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
723 (extractps): Add VexWIG to SSE2AVX forms.
724 * i386-tbl.h: Re-generate.
725
4814632e
JB		 7262020-01-16 Jan Beulich <jbeulich@suse.com>
727
728 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
729 Size64 from and use VexW1 on SSE2AVX forms.
730 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
731 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
732 * i386-tbl.h: Re-generate.
733
aad09917
AM		 7342020-01-15 Alan Modra <amodra@gmail.com>
735
736 * tic4x-dis.c (tic4x_version): Make unsigned long.
737 (optab, optab_special, registernames): New file scope vars.
738 (tic4x_print_register): Set up registernames rather than
739 malloc'd registertable.
740 (tic4x_disassemble): Delete optable and optable_special. Use
741 optab and optab_special instead. Throw away old optab,
742 optab_special and registernames when info->mach changes.
743
7a6bf3be
SB		 7442020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
745
746 PR 25377
747 * z80-dis.c (suffix): Use .db instruction to generate double
748 prefix.
749
ca1eaac0
AM		 7502020-01-14 Alan Modra <amodra@gmail.com>
751
752 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
753 values to unsigned before shifting.
754
1d67fe3b
TT		 7552020-01-13 Thomas Troeger <tstroege@gmx.de>
756
757 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
758 flow instructions.
759 (print_insn_thumb16, print_insn_thumb32): Likewise.
760 (print_insn): Initialize the insn info.
761 * i386-dis.c (print_insn): Initialize the insn info fields, and
762 detect jumps.
763
5e4f7e05
CZ		 7642012-01-13 Claudiu Zissulescu <claziss@gmail.com>
765
766 * arc-opc.c (C_NE): Make it required.
767
b9fe6b8a
CZ		 7682012-01-13 Claudiu Zissulescu <claziss@gmail.com>
769
770 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
771 reserved register name.
772
90dee485
AM		 7732020-01-13 Alan Modra <amodra@gmail.com>
774
775 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
776 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
777
febda64f
AM		 7782020-01-13 Alan Modra <amodra@gmail.com>
779
780 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
781 result of wasm_read_leb128 in a uint64_t and check that bits
782 are not lost when copying to other locals. Use uint32_t for
783 most locals. Use PRId64 when printing int64_t.
784
df08b588
AM		 7852020-01-13 Alan Modra <amodra@gmail.com>
786
787 * score-dis.c: Formatting.
788 * score7-dis.c: Formatting.
789
b2c759ce
AM		 7902020-01-13 Alan Modra <amodra@gmail.com>
791
792 * score-dis.c (print_insn_score48): Use unsigned variables for
793 unsigned values. Don't left shift negative values.
794 (print_insn_score32): Likewise.
795 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
796
5496abe1
AM		 7972020-01-13 Alan Modra <amodra@gmail.com>
798
799 * tic4x-dis.c (tic4x_print_register): Remove dead code.
800
202e762b
AM		 8012020-01-13 Alan Modra <amodra@gmail.com>
802
803 * fr30-ibld.c: Regenerate.
804
7ef412cf
AM		 8052020-01-13 Alan Modra <amodra@gmail.com>
806
807 * xgate-dis.c (print_insn): Don't left shift signed value.
808 (ripBits): Formatting, use 1u.
809
7f578b95
AM		 8102020-01-10 Alan Modra <amodra@gmail.com>
811
812 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
813 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
814
441af85b
AM		 8152020-01-10 Alan Modra <amodra@gmail.com>
816
817 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
818 and XRREG value earlier to avoid a shift with negative exponent.
819 * m10200-dis.c (disassemble): Similarly.
820
bce58db4
NC		 8212020-01-09 Nick Clifton <nickc@redhat.com>
822
823 PR 25224
824 * z80-dis.c (ld_ii_ii): Use correct cast.
825
40c75bc8
SB		 8262020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
827
828 PR 25224
829 * z80-dis.c (ld_ii_ii): Use character constant when checking
830 opcode byte value.
831
d835a58b
JB		 8322020-01-09 Jan Beulich <jbeulich@suse.com>
833
834 * i386-dis.c (SEP_Fixup): New.
835 (SEP): Define.
836 (dis386_twobyte): Use it for sysenter/sysexit.
837 (enum x86_64_isa): Change amd64 enumerator to value 1.
838 (OP_J): Compare isa64 against intel64 instead of amd64.
839 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
840 forms.
841 * i386-tbl.h: Re-generate.
842
030a2e78
AM		 8432020-01-08 Alan Modra <amodra@gmail.com>
844
845 * z8k-dis.c: Include libiberty.h
846 (instr_data_s): Make max_fetched unsigned.
847 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
848 Don't exceed byte_info bounds.
849 (output_instr): Make num_bytes unsigned.
850 (unpack_instr): Likewise for nibl_count and loop.
851 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
852 idx unsigned.
853 * z8k-opc.h: Regenerate.
854
bb82aefe
SV		 8552020-01-07 Shahab Vahedi <shahab@synopsys.com>
856
857 * arc-tbl.h (llock): Use 'LLOCK' as class.
858 (llockd): Likewise.
859 (scond): Use 'SCOND' as class.
860 (scondd): Likewise.
861 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
862 (scondd): Likewise.
863
cc6aa1a6
AM		 8642020-01-06 Alan Modra <amodra@gmail.com>
865
866 * m32c-ibld.c: Regenerate.
867
660e62b1
AM		 8682020-01-06 Alan Modra <amodra@gmail.com>
869
870 PR 25344
871 * z80-dis.c (suffix): Don't use a local struct buffer copy.
872 Peek at next byte to prevent recursion on repeated prefix bytes.
873 Ensure uninitialised "mybuf" is not accessed.
874 (print_insn_z80): Don't zero n_fetch and n_used here,..
875 (print_insn_z80_buf): ..do it here instead.
876
c9ae58fe
AM		 8772020-01-04 Alan Modra <amodra@gmail.com>
878
879 * m32r-ibld.c: Regenerate.
880
5f57d4ec
AM		 8812020-01-04 Alan Modra <amodra@gmail.com>
882
883 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
884
2c5c1196
AM		 8852020-01-04 Alan Modra <amodra@gmail.com>
886
887 * crx-dis.c (match_opcode): Avoid shift left of signed value.
888
2e98c6c5
AM		 8892020-01-04 Alan Modra <amodra@gmail.com>
890
891 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
892
567dfba2
JB		 8932020-01-03 Jan Beulich <jbeulich@suse.com>
894
5437a02a
JB		 895 * aarch64-tbl.h (aarch64_opcode_table): Use
896 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
897
8982020-01-03 Jan Beulich <jbeulich@suse.com>
899
900 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 901 forms of SUDOT and USDOT.
902
8c45011a
JB		 9032020-01-03 Jan Beulich <jbeulich@suse.com>
904
5437a02a 905 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 906 uzip{1,2}.
907 * opcodes/aarch64-dis-2.c: Re-generate.
908
f4950f76
JB		 9092020-01-03 Jan Beulich <jbeulich@suse.com>
910
5437a02a 911 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 912 FMMLA encoding.
913 * opcodes/aarch64-dis-2.c: Re-generate.
914
6655dba2
SB		 9152020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
916
917 * z80-dis.c: Add support for eZ80 and Z80 instructions.
918
b14ce8bf
AM		 9192020-01-01 Alan Modra <amodra@gmail.com>
920
921 Update year range in copyright notice of all files.
922
0b114740 923For older changes see ChangeLog-2019
3499769a 924\f
0b114740 925Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 926
927Copying and distribution of this file, with or without modification,
928are permitted in any medium without royalty provided the copyright
929notice and this notice are preserved.
930
931Local Variables:
932mode: change-log
933left-margin: 8
934fill-column: 74
935version-control: never
936End:
GDB Binutils - Deliverables
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