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x86: use template for SSE floating point comparison insns
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3677e4c1
JB		 12020-03-09 Jan Beulich <jbeulich@suse.com>
2
3 * i386-gen.c (set_bitfield): Ignore zero-length field names.
4 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
5 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
6 * i386-tbl.h: Re-generate.
7
4c4898e8
JB		 82020-03-09 Jan Beulich <jbeulich@suse.com>
9
10 * i386-gen.c (struct template_arg, struct template_instance,
11 struct template_param, struct template, templates,
12 parse_template, expand_templates): New.
13 (process_i386_opcodes): Various local variables moved to
14 expand_templates. Call parse_template and expand_templates.
15 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
16 * i386-tbl.h: Re-generate.
17
bc49bfd8
JB		 182020-03-06 Jan Beulich <jbeulich@suse.com>
19
20 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
21 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
22 register and memory source templates. Replace VexW= by VexW*
23 where applicable.
24 * i386-tbl.h: Re-generate.
25
4873e243
JB		 262020-03-06 Jan Beulich <jbeulich@suse.com>
27
28 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
29 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
30 * i386-tbl.h: Re-generate.
31
672a349b
JB		 322020-03-06 Jan Beulich <jbeulich@suse.com>
33
34 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
35 * i386-tbl.h: Re-generate.
36
4ed21b58
JB		 372020-03-06 Jan Beulich <jbeulich@suse.com>
38
39 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
40 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
41 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
42 VexW0 on SSE2AVX variants.
43 (vmovq): Drop NoRex64 from XMM/XMM variants.
44 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
45 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
46 applicable use VexW0.
47 * i386-tbl.h: Re-generate.
48
643bb870
JB		 492020-03-06 Jan Beulich <jbeulich@suse.com>
50
51 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
52 * i386-opc.h (Rex64): Delete.
53 (struct i386_opcode_modifier): Remove rex64 field.
54 * i386-opc.tbl (crc32): Drop Rex64.
55 Replace Rex64 with Size64 everywhere else.
56 * i386-tbl.h: Re-generate.
57
a23b33b3
JB		 582020-03-06 Jan Beulich <jbeulich@suse.com>
59
60 * i386-dis.c (OP_E_memory): Exclude recording of used address
61 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
62 addressed memory operands for MPX insns.
63
a0497384
JB		 642020-03-06 Jan Beulich <jbeulich@suse.com>
65
66 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
67 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
68 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
69 (ptwrite): Split into non-64-bit and 64-bit forms.
70 * i386-tbl.h: Re-generate.
71
b630c145
JB		 722020-03-06 Jan Beulich <jbeulich@suse.com>
73
74 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
75 template.
76 * i386-tbl.h: Re-generate.
77
a847e322
JB		 782020-03-04 Jan Beulich <jbeulich@suse.com>
79
80 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
81 (prefix_table): Move vmmcall here. Add vmgexit.
82 (rm_table): Replace vmmcall entry by prefix_table[] escape.
83 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
84 (cpu_flags): Add CpuSEV_ES entry.
85 * i386-opc.h (CpuSEV_ES): New.
86 (union i386_cpu_flags): Add cpusev_es field.
87 * i386-opc.tbl (vmgexit): New.
88 * i386-init.h, i386-tbl.h: Re-generate.
89
3cd7f3e3
L		 902020-03-03 H.J. Lu <hongjiu.lu@intel.com>
91
92 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
93 with MnemonicSize.
94 * i386-opc.h (IGNORESIZE): New.
95 (DEFAULTSIZE): Likewise.
96 (IgnoreSize): Removed.
97 (DefaultSize): Likewise.
98 (MnemonicSize): New.
99 (i386_opcode_modifier): Replace ignoresize/defaultsize with
100 mnemonicsize.
101 * i386-opc.tbl (IgnoreSize): New.
102 (DefaultSize): Likewise.
103 * i386-tbl.h: Regenerated.
104
b8ba1385
SB		 1052020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
106
107 PR 25627
108 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
109 instructions.
110
10d97a0f
L		 1112020-03-03 H.J. Lu <hongjiu.lu@intel.com>
112
113 PR gas/25622
114 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
115 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
116 * i386-tbl.h: Regenerated.
117
dc1e8a47
AM		 1182020-02-26 Alan Modra <amodra@gmail.com>
119
120 * aarch64-asm.c: Indent labels correctly.
121 * aarch64-dis.c: Likewise.
122 * aarch64-gen.c: Likewise.
123 * aarch64-opc.c: Likewise.
124 * alpha-dis.c: Likewise.
125 * i386-dis.c: Likewise.
126 * nds32-asm.c: Likewise.
127 * nfp-dis.c: Likewise.
128 * visium-dis.c: Likewise.
129
265b4673
CZ		 1302020-02-25 Claudiu Zissulescu <claziss@gmail.com>
131
132 * arc-regs.h (int_vector_base): Make it available for all ARC
133 CPUs.
134
bd0cf5a6
NC		 1352020-02-20 Nelson Chu <nelson.chu@sifive.com>
136
137 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
138 changed.
139
fa164239
JW		 1402020-02-19 Nelson Chu <nelson.chu@sifive.com>
141
142 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
143 c.mv/c.li if rs1 is zero.
144
272a84b1
L		 1452020-02-17 H.J. Lu <hongjiu.lu@intel.com>
146
147 * i386-gen.c (cpu_flag_init): Replace CpuABM with
148 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
149 CPU_POPCNT_FLAGS.
150 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
151 * i386-opc.h (CpuABM): Removed.
152 (CpuPOPCNT): New.
153 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
154 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
155 popcnt. Remove CpuABM from lzcnt.
156 * i386-init.h: Regenerated.
157 * i386-tbl.h: Likewise.
158
1f730c46
JB		 1592020-02-17 Jan Beulich <jbeulich@suse.com>
160
161 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
162 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
163 VexW1 instead of open-coding them.
164 * i386-tbl.h: Re-generate.
165
c8f8eebc
JB		 1662020-02-17 Jan Beulich <jbeulich@suse.com>
167
168 * i386-opc.tbl (AddrPrefixOpReg): Define.
169 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
170 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
171 templates. Drop NoRex64.
172 * i386-tbl.h: Re-generate.
173
b9915cbc
JB		 1742020-02-17 Jan Beulich <jbeulich@suse.com>
175
176 PR gas/6518
177 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
178 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
179 into Intel syntax instance (with Unpsecified) and AT&T one
180 (without).
181 (vcvtneps2bf16): Likewise, along with folding the two so far
182 separate ones.
183 * i386-tbl.h: Re-generate.
184
ce504911
L		 1852020-02-16 H.J. Lu <hongjiu.lu@intel.com>
186
187 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
188 CPU_ANY_SSE4A_FLAGS.
189
dabec65d
AM		 1902020-02-17 Alan Modra <amodra@gmail.com>
191
192 * i386-gen.c (cpu_flag_init): Correct last change.
193
af5c13b0
L		 1942020-02-16 H.J. Lu <hongjiu.lu@intel.com>
195
196 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
197 CPU_ANY_SSE4_FLAGS.
198
6867aac0
L		 1992020-02-14 H.J. Lu <hongjiu.lu@intel.com>
200
201 * i386-opc.tbl (movsx): Remove Intel syntax comments.
202 (movzx): Likewise.
203
65fca059
JB		 2042020-02-14 Jan Beulich <jbeulich@suse.com>
205
206 PR gas/25438
207 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
208 destination for Cpu64-only variant.
209 (movzx): Fold patterns.
210 * i386-tbl.h: Re-generate.
211
7deea9aa
JB		 2122020-02-13 Jan Beulich <jbeulich@suse.com>
213
214 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
215 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
216 CPU_ANY_SSE4_FLAGS entry.
217 * i386-init.h: Re-generate.
218
6c0946d0
JB		 2192020-02-12 Jan Beulich <jbeulich@suse.com>
220
221 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
222 with Unspecified, making the present one AT&T syntax only.
223 * i386-tbl.h: Re-generate.
224
ddb56fe6
JB		 2252020-02-12 Jan Beulich <jbeulich@suse.com>
226
227 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
228 * i386-tbl.h: Re-generate.
229
5990e377
JB		 2302020-02-12 Jan Beulich <jbeulich@suse.com>
231
232 PR gas/24546
233 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
234 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
235 Amd64 and Intel64 templates.
236 (call, jmp): Likewise for far indirect variants. Dro
237 Unspecified.
238 * i386-tbl.h: Re-generate.
239
50128d0c
JB		 2402020-02-11 Jan Beulich <jbeulich@suse.com>
241
242 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
243 * i386-opc.h (ShortForm): Delete.
244 (struct i386_opcode_modifier): Remove shortform field.
245 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
246 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
247 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
248 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
249 Drop ShortForm.
250 * i386-tbl.h: Re-generate.
251
1e05b5c4
JB		 2522020-02-11 Jan Beulich <jbeulich@suse.com>
253
254 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
255 fucompi): Drop ShortForm from operand-less templates.
256 * i386-tbl.h: Re-generate.
257
2f5dd314
AM		 2582020-02-11 Alan Modra <amodra@gmail.com>
259
260 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
261 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
262 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
263 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
264 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
265
5aae9ae9
MM		 2662020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
267
268 * arm-dis.c (print_insn_cde): Define 'V' parse character.
269 (cde_opcodes): Add VCX* instructions.
270
4934a27c
MM		 2712020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
272 Matthew Malcomson <matthew.malcomson@arm.com>
273
274 * arm-dis.c (struct cdeopcode32): New.
275 (CDE_OPCODE): New macro.
276 (cde_opcodes): New disassembly table.
277 (regnames): New option to table.
278 (cde_coprocs): New global variable.
279 (print_insn_cde): New
280 (print_insn_thumb32): Use print_insn_cde.
281 (parse_arm_disassembler_options): Parse coprocN args.
282
4b5aaf5f
L		 2832020-02-10 H.J. Lu <hongjiu.lu@intel.com>
284
285 PR gas/25516
286 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
287 with ISA64.
288 * i386-opc.h (AMD64): Removed.
289 (Intel64): Likewose.
290 (AMD64): New.
291 (INTEL64): Likewise.
292 (INTEL64ONLY): Likewise.
293 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
294 * i386-opc.tbl (Amd64): New.
295 (Intel64): Likewise.
296 (Intel64Only): Likewise.
297 Replace AMD64 with Amd64. Update sysenter/sysenter with
298 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
299 * i386-tbl.h: Regenerated.
300
9fc0b501
SB		 3012020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
302
303 PR 25469
304 * z80-dis.c: Add support for GBZ80 opcodes.
305
c5d7be0c
AM		 3062020-02-04 Alan Modra <amodra@gmail.com>
307
308 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
309
44e4546f
AM		 3102020-02-03 Alan Modra <amodra@gmail.com>
311
312 * m32c-ibld.c: Regenerate.
313
b2b1453a
AM		 3142020-02-01 Alan Modra <amodra@gmail.com>
315
316 * frv-ibld.c: Regenerate.
317
4102be5c
JB		 3182020-01-31 Jan Beulich <jbeulich@suse.com>
319
320 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
321 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
322 (OP_E_memory): Replace xmm_mdq_mode case label by
323 vex_scalar_w_dq_mode one.
324 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
325
825bd36c
JB		 3262020-01-31 Jan Beulich <jbeulich@suse.com>
327
328 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
329 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
330 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
331 (intel_operand_size): Drop vex_w_dq_mode case label.
332
c3036ed0
RS		 3332020-01-31 Richard Sandiford <richard.sandiford@arm.com>
334
335 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
336 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
337
0c115f84
AM		 3382020-01-30 Alan Modra <amodra@gmail.com>
339
340 * m32c-ibld.c: Regenerate.
341
bd434cc4
JM		 3422020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
343
344 * bpf-opc.c: Regenerate.
345
aeab2b26
JB		 3462020-01-30 Jan Beulich <jbeulich@suse.com>
347
348 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
349 (dis386): Use them to replace C2/C3 table entries.
350 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
351 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
352 ones. Use Size64 instead of DefaultSize on Intel64 ones.
353 * i386-tbl.h: Re-generate.
354
62b3f548
JB		 3552020-01-30 Jan Beulich <jbeulich@suse.com>
356
357 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
358 forms.
359 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
360 DefaultSize.
361 * i386-tbl.h: Re-generate.
362
1bd8ae10
AM		 3632020-01-30 Alan Modra <amodra@gmail.com>
364
365 * tic4x-dis.c (tic4x_dp): Make unsigned.
366
bc31405e
L		 3672020-01-27 H.J. Lu <hongjiu.lu@intel.com>
368 Jan Beulich <jbeulich@suse.com>
369
370 PR binutils/25445
371 * i386-dis.c (MOVSXD_Fixup): New function.
372 (movsxd_mode): New enum.
373 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
374 (intel_operand_size): Handle movsxd_mode.
375 (OP_E_register): Likewise.
376 (OP_G): Likewise.
377 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
378 register on movsxd. Add movsxd with 16-bit destination register
379 for AMD64 and Intel64 ISAs.
380 * i386-tbl.h: Regenerated.
381
7568c93b
TC		 3822020-01-27 Tamar Christina <tamar.christina@arm.com>
383
384 PR 25403
385 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
386 * aarch64-asm-2.c: Regenerate
387 * aarch64-dis-2.c: Likewise.
388 * aarch64-opc-2.c: Likewise.
389
c006a730
JB		 3902020-01-21 Jan Beulich <jbeulich@suse.com>
391
392 * i386-opc.tbl (sysret): Drop DefaultSize.
393 * i386-tbl.h: Re-generate.
394
c906a69a
JB		 3952020-01-21 Jan Beulich <jbeulich@suse.com>
396
397 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
398 Dword.
399 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
400 * i386-tbl.h: Re-generate.
401
26916852
NC		 4022020-01-20 Nick Clifton <nickc@redhat.com>
403
404 * po/de.po: Updated German translation.
405 * po/pt_BR.po: Updated Brazilian Portuguese translation.
406 * po/uk.po: Updated Ukranian translation.
407
4d6cbb64
AM		 4082020-01-20 Alan Modra <amodra@gmail.com>
409
410 * hppa-dis.c (fput_const): Remove useless cast.
411
2bddb71a
AM		 4122020-01-20 Alan Modra <amodra@gmail.com>
413
414 * arm-dis.c (print_insn_arm): Wrap 'T' value.
415
1b1bb2c6
NC		 4162020-01-18 Nick Clifton <nickc@redhat.com>
417
418 * configure: Regenerate.
419 * po/opcodes.pot: Regenerate.
420
ae774686
NC		 4212020-01-18 Nick Clifton <nickc@redhat.com>
422
423 Binutils 2.34 branch created.
424
07f1f3aa
CB		 4252020-01-17 Christian Biesinger <cbiesinger@google.com>
426
427 * opintl.h: Fix spelling error (seperate).
428
42e04b36
L		 4292020-01-17 H.J. Lu <hongjiu.lu@intel.com>
430
431 * i386-opc.tbl: Add {vex} pseudo prefix.
432 * i386-tbl.h: Regenerated.
433
2da2eaf4
AV		 4342020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
435
436 PR 25376
437 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
438 (neon_opcodes): Likewise.
439 (select_arm_features): Make sure we enable MVE bits when selecting
440 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
441 any architecture.
442
d0849eed
JB		 4432020-01-16 Jan Beulich <jbeulich@suse.com>
444
445 * i386-opc.tbl: Drop stale comment from XOP section.
446
9cf70a44
JB		 4472020-01-16 Jan Beulich <jbeulich@suse.com>
448
449 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
450 (extractps): Add VexWIG to SSE2AVX forms.
451 * i386-tbl.h: Re-generate.
452
4814632e
JB		 4532020-01-16 Jan Beulich <jbeulich@suse.com>
454
455 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
456 Size64 from and use VexW1 on SSE2AVX forms.
457 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
458 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
459 * i386-tbl.h: Re-generate.
460
aad09917
AM		 4612020-01-15 Alan Modra <amodra@gmail.com>
462
463 * tic4x-dis.c (tic4x_version): Make unsigned long.
464 (optab, optab_special, registernames): New file scope vars.
465 (tic4x_print_register): Set up registernames rather than
466 malloc'd registertable.
467 (tic4x_disassemble): Delete optable and optable_special. Use
468 optab and optab_special instead. Throw away old optab,
469 optab_special and registernames when info->mach changes.
470
7a6bf3be
SB		 4712020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
472
473 PR 25377
474 * z80-dis.c (suffix): Use .db instruction to generate double
475 prefix.
476
ca1eaac0
AM		 4772020-01-14 Alan Modra <amodra@gmail.com>
478
479 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
480 values to unsigned before shifting.
481
1d67fe3b
TT		 4822020-01-13 Thomas Troeger <tstroege@gmx.de>
483
484 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
485 flow instructions.
486 (print_insn_thumb16, print_insn_thumb32): Likewise.
487 (print_insn): Initialize the insn info.
488 * i386-dis.c (print_insn): Initialize the insn info fields, and
489 detect jumps.
490
5e4f7e05
CZ		 4912012-01-13 Claudiu Zissulescu <claziss@gmail.com>
492
493 * arc-opc.c (C_NE): Make it required.
494
b9fe6b8a
CZ		 4952012-01-13 Claudiu Zissulescu <claziss@gmail.com>
496
497 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
498 reserved register name.
499
90dee485
AM		 5002020-01-13 Alan Modra <amodra@gmail.com>
501
502 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
503 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
504
febda64f
AM		 5052020-01-13 Alan Modra <amodra@gmail.com>
506
507 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
508 result of wasm_read_leb128 in a uint64_t and check that bits
509 are not lost when copying to other locals. Use uint32_t for
510 most locals. Use PRId64 when printing int64_t.
511
df08b588
AM		 5122020-01-13 Alan Modra <amodra@gmail.com>
513
514 * score-dis.c: Formatting.
515 * score7-dis.c: Formatting.
516
b2c759ce
AM		 5172020-01-13 Alan Modra <amodra@gmail.com>
518
519 * score-dis.c (print_insn_score48): Use unsigned variables for
520 unsigned values. Don't left shift negative values.
521 (print_insn_score32): Likewise.
522 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
523
5496abe1
AM		 5242020-01-13 Alan Modra <amodra@gmail.com>
525
526 * tic4x-dis.c (tic4x_print_register): Remove dead code.
527
202e762b
AM		 5282020-01-13 Alan Modra <amodra@gmail.com>
529
530 * fr30-ibld.c: Regenerate.
531
7ef412cf
AM		 5322020-01-13 Alan Modra <amodra@gmail.com>
533
534 * xgate-dis.c (print_insn): Don't left shift signed value.
535 (ripBits): Formatting, use 1u.
536
7f578b95
AM		 5372020-01-10 Alan Modra <amodra@gmail.com>
538
539 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
540 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
541
441af85b
AM		 5422020-01-10 Alan Modra <amodra@gmail.com>
543
544 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
545 and XRREG value earlier to avoid a shift with negative exponent.
546 * m10200-dis.c (disassemble): Similarly.
547
bce58db4
NC		 5482020-01-09 Nick Clifton <nickc@redhat.com>
549
550 PR 25224
551 * z80-dis.c (ld_ii_ii): Use correct cast.
552
40c75bc8
SB		 5532020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
554
555 PR 25224
556 * z80-dis.c (ld_ii_ii): Use character constant when checking
557 opcode byte value.
558
d835a58b
JB		 5592020-01-09 Jan Beulich <jbeulich@suse.com>
560
561 * i386-dis.c (SEP_Fixup): New.
562 (SEP): Define.
563 (dis386_twobyte): Use it for sysenter/sysexit.
564 (enum x86_64_isa): Change amd64 enumerator to value 1.
565 (OP_J): Compare isa64 against intel64 instead of amd64.
566 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
567 forms.
568 * i386-tbl.h: Re-generate.
569
030a2e78
AM		 5702020-01-08 Alan Modra <amodra@gmail.com>
571
572 * z8k-dis.c: Include libiberty.h
573 (instr_data_s): Make max_fetched unsigned.
574 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
575 Don't exceed byte_info bounds.
576 (output_instr): Make num_bytes unsigned.
577 (unpack_instr): Likewise for nibl_count and loop.
578 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
579 idx unsigned.
580 * z8k-opc.h: Regenerate.
581
bb82aefe
SV		 5822020-01-07 Shahab Vahedi <shahab@synopsys.com>
583
584 * arc-tbl.h (llock): Use 'LLOCK' as class.
585 (llockd): Likewise.
586 (scond): Use 'SCOND' as class.
587 (scondd): Likewise.
588 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
589 (scondd): Likewise.
590
cc6aa1a6
AM		 5912020-01-06 Alan Modra <amodra@gmail.com>
592
593 * m32c-ibld.c: Regenerate.
594
660e62b1
AM		 5952020-01-06 Alan Modra <amodra@gmail.com>
596
597 PR 25344
598 * z80-dis.c (suffix): Don't use a local struct buffer copy.
599 Peek at next byte to prevent recursion on repeated prefix bytes.
600 Ensure uninitialised "mybuf" is not accessed.
601 (print_insn_z80): Don't zero n_fetch and n_used here,..
602 (print_insn_z80_buf): ..do it here instead.
603
c9ae58fe
AM		 6042020-01-04 Alan Modra <amodra@gmail.com>
605
606 * m32r-ibld.c: Regenerate.
607
5f57d4ec
AM		 6082020-01-04 Alan Modra <amodra@gmail.com>
609
610 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
611
2c5c1196
AM		 6122020-01-04 Alan Modra <amodra@gmail.com>
613
614 * crx-dis.c (match_opcode): Avoid shift left of signed value.
615
2e98c6c5
AM		 6162020-01-04 Alan Modra <amodra@gmail.com>
617
618 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
619
567dfba2
JB		 6202020-01-03 Jan Beulich <jbeulich@suse.com>
621
5437a02a
JB		 622 * aarch64-tbl.h (aarch64_opcode_table): Use
623 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
624
6252020-01-03 Jan Beulich <jbeulich@suse.com>
626
627 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 628 forms of SUDOT and USDOT.
629
8c45011a
JB		 6302020-01-03 Jan Beulich <jbeulich@suse.com>
631
5437a02a 632 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 633 uzip{1,2}.
634 * opcodes/aarch64-dis-2.c: Re-generate.
635
f4950f76
JB		 6362020-01-03 Jan Beulich <jbeulich@suse.com>
637
5437a02a 638 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 639 FMMLA encoding.
640 * opcodes/aarch64-dis-2.c: Re-generate.
641
6655dba2
SB		 6422020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
643
644 * z80-dis.c: Add support for eZ80 and Z80 instructions.
645
b14ce8bf
AM		 6462020-01-01 Alan Modra <amodra@gmail.com>
647
648 Update year range in copyright notice of all files.
649
0b114740 650For older changes see ChangeLog-2019
3499769a 651\f
0b114740 652Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 653
654Copying and distribution of this file, with or without modification,
655are permitted in any medium without royalty provided the copyright
656notice and this notice are preserved.
657
658Local Variables:
659mode: change-log
660left-margin: 8
661fill-column: 74
662version-control: never
663End:
GDB Binutils - Deliverables
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