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Power10 byte reverse instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3ff0a5ba
PB		 12020-05-11 Peter Bergner <bergner@linux.ibm.com>
2
3 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
4
afef4fe9
PB		 52020-05-11 Peter Bergner <bergner@linux.ibm.com>
6
7 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
8 (L1OPT): Define.
9 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
10
1224c05d
PB		 112020-05-11 Peter Bergner <bergner@linux.ibm.com>
12
13 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
14
6bbb0c05
AM		 152020-05-11 Alan Modra <amodra@gmail.com>
16
17 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
18
7c1f4227
AM		 192020-05-11 Alan Modra <amodra@gmail.com>
20
21 * ppc-dis.c (ppc_opts): Add "power10" entry.
22 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
23 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
24
73199c2b
NC		 252020-05-11 Nick Clifton <nickc@redhat.com>
26
27 * po/fr.po: Updated French translation.
28
09c1e68a
AC		 292020-04-30 Alex Coplan <alex.coplan@arm.com>
30
31 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
32 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
33 (operand_general_constraint_met_p): validate
34 AARCH64_OPND_UNDEFINED.
35 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
36 for FLD_imm16_2.
37 * aarch64-asm-2.c: Regenerated.
38 * aarch64-dis-2.c: Regenerated.
39 * aarch64-opc-2.c: Regenerated.
40
9654d51a
NC		 412020-04-29 Nick Clifton <nickc@redhat.com>
42
43 PR 22699
44 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
45 and SETRC insns.
46
c2e71e57
NC		 472020-04-29 Nick Clifton <nickc@redhat.com>
48
49 * po/sv.po: Updated Swedish translation.
50
5c936ef5
NC		 512020-04-29 Nick Clifton <nickc@redhat.com>
52
53 PR 22699
54 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
55 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
56 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
57 IMM0_8U case.
58
bb2a1453
AS		 592020-04-21 Andreas Schwab <schwab@linux-m68k.org>
60
61 PR 25848
62 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
63 cmpi only on m68020up and cpu32.
64
c2e5c986
SD		 652020-04-20 Sudakshina Das <sudi.das@arm.com>
66
67 * aarch64-asm.c (aarch64_ins_none): New.
68 * aarch64-asm.h (ins_none): New declaration.
69 * aarch64-dis.c (aarch64_ext_none): New.
70 * aarch64-dis.h (ext_none): New declaration.
71 * aarch64-opc.c (aarch64_print_operand): Update case for
72 AARCH64_OPND_BARRIER_PSB.
73 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
74 (AARCH64_OPERANDS): Update inserter/extracter for
75 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
76 * aarch64-asm-2.c: Regenerated.
77 * aarch64-dis-2.c: Regenerated.
78 * aarch64-opc-2.c: Regenerated.
79
8a6e1d1d
SD		 802020-04-20 Sudakshina Das <sudi.das@arm.com>
81
82 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
83 (aarch64_feature_ras, RAS): Likewise.
84 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
85 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
86 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
87 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
88 * aarch64-asm-2.c: Regenerated.
89 * aarch64-dis-2.c: Regenerated.
90 * aarch64-opc-2.c: Regenerated.
91
e409955d
FS		 922020-04-17 Fredrik Strupe <fredrik@strupe.net>
93
94 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
95 (print_insn_neon): Support disassembly of conditional
96 instructions.
97
c54a9b56
DF		 982020-02-16 David Faust <david.faust@oracle.com>
99
100 * bpf-desc.c: Regenerate.
101 * bpf-desc.h: Likewise.
102 * bpf-opc.c: Regenerate.
103 * bpf-opc.h: Likewise.
104
bb651e8b
CL		 1052020-04-07 Lili Cui <lili.cui@intel.com>
106
107 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
108 (prefix_table): New instructions (see prefixes above).
109 (rm_table): Likewise
110 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
111 CPU_ANY_TSXLDTRK_FLAGS.
112 (cpu_flags): Add CpuTSXLDTRK.
113 * i386-opc.h (enum): Add CpuTSXLDTRK.
114 (i386_cpu_flags): Add cputsxldtrk.
115 * i386-opc.tbl: Add XSUSPLDTRK insns.
116 * i386-init.h: Regenerate.
117 * i386-tbl.h: Likewise.
118
4b27d27c
L		 1192020-04-02 Lili Cui <lili.cui@intel.com>
120
121 * i386-dis.c (prefix_table): New instructions serialize.
122 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
123 CPU_ANY_SERIALIZE_FLAGS.
124 (cpu_flags): Add CpuSERIALIZE.
125 * i386-opc.h (enum): Add CpuSERIALIZE.
126 (i386_cpu_flags): Add cpuserialize.
127 * i386-opc.tbl: Add SERIALIZE insns.
128 * i386-init.h: Regenerate.
129 * i386-tbl.h: Likewise.
130
832a5807
AM		 1312020-03-26 Alan Modra <amodra@gmail.com>
132
133 * disassemble.h (opcodes_assert): Declare.
134 (OPCODES_ASSERT): Define.
135 * disassemble.c: Don't include assert.h. Include opintl.h.
136 (opcodes_assert): New function.
137 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
138 (bfd_h8_disassemble): Reduce size of data array. Correctly
139 calculate maxlen. Omit insn decoding when insn length exceeds
140 maxlen. Exit from nibble loop when looking for E, before
141 accessing next data byte. Move processing of E outside loop.
142 Replace tests of maxlen in loop with assertions.
143
4c4addbe
AM		 1442020-03-26 Alan Modra <amodra@gmail.com>
145
146 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
147
a18cd0ca
AM		 1482020-03-25 Alan Modra <amodra@gmail.com>
149
150 * z80-dis.c (suffix): Init mybuf.
151
57cb32b3
AM		 1522020-03-22 Alan Modra <amodra@gmail.com>
153
154 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
155 successflly read from section.
156
beea5cc1
AM		 1572020-03-22 Alan Modra <amodra@gmail.com>
158
159 * arc-dis.c (find_format): Use ISO C string concatenation rather
160 than line continuation within a string. Don't access needs_limm
161 before testing opcode != NULL.
162
03704c77
AM		 1632020-03-22 Alan Modra <amodra@gmail.com>
164
165 * ns32k-dis.c (print_insn_arg): Update comment.
166 (print_insn_ns32k): Reduce size of index_offset array, and
167 initialize, passing -1 to print_insn_arg for args that are not
168 an index. Don't exit arg loop early. Abort on bad arg number.
169
d1023b5d
AM		 1702020-03-22 Alan Modra <amodra@gmail.com>
171
172 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
173 * s12z-opc.c: Formatting.
174 (operands_f): Return an int.
175 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
176 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
177 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
178 (exg_sex_discrim): Likewise.
179 (create_immediate_operand, create_bitfield_operand),
180 (create_register_operand_with_size, create_register_all_operand),
181 (create_register_all16_operand, create_simple_memory_operand),
182 (create_memory_operand, create_memory_auto_operand): Don't
183 segfault on malloc failure.
184 (z_ext24_decode): Return an int status, negative on fail, zero
185 on success.
186 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
187 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
188 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
189 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
190 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
191 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
192 (loop_primitive_decode, shift_decode, psh_pul_decode),
193 (bit_field_decode): Similarly.
194 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
195 to return value, update callers.
196 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
197 Don't segfault on NULL operand.
198 (decode_operation): Return OP_INVALID on first fail.
199 (decode_s12z): Check all reads, returning -1 on fail.
200
340f3ac8
AM		 2012020-03-20 Alan Modra <amodra@gmail.com>
202
203 * metag-dis.c (print_insn_metag): Don't ignore status from
204 read_memory_func.
205
fe90ae8a
AM		 2062020-03-20 Alan Modra <amodra@gmail.com>
207
208 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
209 Initialize parts of buffer not written when handling a possible
210 2-byte insn at end of section. Don't attempt decoding of such
211 an insn by the 4-byte machinery.
212
833d919c
AM		 2132020-03-20 Alan Modra <amodra@gmail.com>
214
215 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
216 partially filled buffer. Prevent lookup of 4-byte insns when
217 only VLE 2-byte insns are possible due to section size. Print
218 ".word" rather than ".long" for 2-byte leftovers.
219
327ef784
NC		 2202020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
221
222 PR 25641
223 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
224
1673df32
JB		 2252020-03-13 Jan Beulich <jbeulich@suse.com>
226
227 * i386-dis.c (X86_64_0D): Rename to ...
228 (X86_64_0E): ... this.
229
384f3689
L		 2302020-03-09 H.J. Lu <hongjiu.lu@intel.com>
231
232 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
233 * Makefile.in: Regenerated.
234
865e2027
JB		 2352020-03-09 Jan Beulich <jbeulich@suse.com>
236
237 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
238 3-operand pseudos.
239 * i386-tbl.h: Re-generate.
240
2f13234b
JB		 2412020-03-09 Jan Beulich <jbeulich@suse.com>
242
243 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
244 vprot*, vpsha*, and vpshl*.
245 * i386-tbl.h: Re-generate.
246
3fabc179
JB		 2472020-03-09 Jan Beulich <jbeulich@suse.com>
248
249 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
250 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
251 * i386-tbl.h: Re-generate.
252
3677e4c1
JB		 2532020-03-09 Jan Beulich <jbeulich@suse.com>
254
255 * i386-gen.c (set_bitfield): Ignore zero-length field names.
256 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
257 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
258 * i386-tbl.h: Re-generate.
259
4c4898e8
JB		 2602020-03-09 Jan Beulich <jbeulich@suse.com>
261
262 * i386-gen.c (struct template_arg, struct template_instance,
263 struct template_param, struct template, templates,
264 parse_template, expand_templates): New.
265 (process_i386_opcodes): Various local variables moved to
266 expand_templates. Call parse_template and expand_templates.
267 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
268 * i386-tbl.h: Re-generate.
269
bc49bfd8
JB		 2702020-03-06 Jan Beulich <jbeulich@suse.com>
271
272 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
273 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
274 register and memory source templates. Replace VexW= by VexW*
275 where applicable.
276 * i386-tbl.h: Re-generate.
277
4873e243
JB		 2782020-03-06 Jan Beulich <jbeulich@suse.com>
279
280 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
281 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
282 * i386-tbl.h: Re-generate.
283
672a349b
JB		 2842020-03-06 Jan Beulich <jbeulich@suse.com>
285
286 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
287 * i386-tbl.h: Re-generate.
288
4ed21b58
JB		 2892020-03-06 Jan Beulich <jbeulich@suse.com>
290
291 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
292 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
293 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
294 VexW0 on SSE2AVX variants.
295 (vmovq): Drop NoRex64 from XMM/XMM variants.
296 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
297 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
298 applicable use VexW0.
299 * i386-tbl.h: Re-generate.
300
643bb870
JB		 3012020-03-06 Jan Beulich <jbeulich@suse.com>
302
303 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
304 * i386-opc.h (Rex64): Delete.
305 (struct i386_opcode_modifier): Remove rex64 field.
306 * i386-opc.tbl (crc32): Drop Rex64.
307 Replace Rex64 with Size64 everywhere else.
308 * i386-tbl.h: Re-generate.
309
a23b33b3
JB		 3102020-03-06 Jan Beulich <jbeulich@suse.com>
311
312 * i386-dis.c (OP_E_memory): Exclude recording of used address
313 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
314 addressed memory operands for MPX insns.
315
a0497384
JB		 3162020-03-06 Jan Beulich <jbeulich@suse.com>
317
318 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
319 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
320 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
321 (ptwrite): Split into non-64-bit and 64-bit forms.
322 * i386-tbl.h: Re-generate.
323
b630c145
JB		 3242020-03-06 Jan Beulich <jbeulich@suse.com>
325
326 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
327 template.
328 * i386-tbl.h: Re-generate.
329
a847e322
JB		 3302020-03-04 Jan Beulich <jbeulich@suse.com>
331
332 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
333 (prefix_table): Move vmmcall here. Add vmgexit.
334 (rm_table): Replace vmmcall entry by prefix_table[] escape.
335 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
336 (cpu_flags): Add CpuSEV_ES entry.
337 * i386-opc.h (CpuSEV_ES): New.
338 (union i386_cpu_flags): Add cpusev_es field.
339 * i386-opc.tbl (vmgexit): New.
340 * i386-init.h, i386-tbl.h: Re-generate.
341
3cd7f3e3
L		 3422020-03-03 H.J. Lu <hongjiu.lu@intel.com>
343
344 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
345 with MnemonicSize.
346 * i386-opc.h (IGNORESIZE): New.
347 (DEFAULTSIZE): Likewise.
348 (IgnoreSize): Removed.
349 (DefaultSize): Likewise.
350 (MnemonicSize): New.
351 (i386_opcode_modifier): Replace ignoresize/defaultsize with
352 mnemonicsize.
353 * i386-opc.tbl (IgnoreSize): New.
354 (DefaultSize): Likewise.
355 * i386-tbl.h: Regenerated.
356
b8ba1385
SB		 3572020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
358
359 PR 25627
360 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
361 instructions.
362
10d97a0f
L		 3632020-03-03 H.J. Lu <hongjiu.lu@intel.com>
364
365 PR gas/25622
366 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
367 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
368 * i386-tbl.h: Regenerated.
369
dc1e8a47
AM		 3702020-02-26 Alan Modra <amodra@gmail.com>
371
372 * aarch64-asm.c: Indent labels correctly.
373 * aarch64-dis.c: Likewise.
374 * aarch64-gen.c: Likewise.
375 * aarch64-opc.c: Likewise.
376 * alpha-dis.c: Likewise.
377 * i386-dis.c: Likewise.
378 * nds32-asm.c: Likewise.
379 * nfp-dis.c: Likewise.
380 * visium-dis.c: Likewise.
381
265b4673
CZ		 3822020-02-25 Claudiu Zissulescu <claziss@gmail.com>
383
384 * arc-regs.h (int_vector_base): Make it available for all ARC
385 CPUs.
386
bd0cf5a6
NC		 3872020-02-20 Nelson Chu <nelson.chu@sifive.com>
388
389 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
390 changed.
391
fa164239
JW		 3922020-02-19 Nelson Chu <nelson.chu@sifive.com>
393
394 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
395 c.mv/c.li if rs1 is zero.
396
272a84b1
L		 3972020-02-17 H.J. Lu <hongjiu.lu@intel.com>
398
399 * i386-gen.c (cpu_flag_init): Replace CpuABM with
400 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
401 CPU_POPCNT_FLAGS.
402 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
403 * i386-opc.h (CpuABM): Removed.
404 (CpuPOPCNT): New.
405 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
406 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
407 popcnt. Remove CpuABM from lzcnt.
408 * i386-init.h: Regenerated.
409 * i386-tbl.h: Likewise.
410
1f730c46
JB		 4112020-02-17 Jan Beulich <jbeulich@suse.com>
412
413 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
414 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
415 VexW1 instead of open-coding them.
416 * i386-tbl.h: Re-generate.
417
c8f8eebc
JB		 4182020-02-17 Jan Beulich <jbeulich@suse.com>
419
420 * i386-opc.tbl (AddrPrefixOpReg): Define.
421 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
422 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
423 templates. Drop NoRex64.
424 * i386-tbl.h: Re-generate.
425
b9915cbc
JB		 4262020-02-17 Jan Beulich <jbeulich@suse.com>
427
428 PR gas/6518
429 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
430 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
431 into Intel syntax instance (with Unpsecified) and AT&T one
432 (without).
433 (vcvtneps2bf16): Likewise, along with folding the two so far
434 separate ones.
435 * i386-tbl.h: Re-generate.
436
ce504911
L		 4372020-02-16 H.J. Lu <hongjiu.lu@intel.com>
438
439 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
440 CPU_ANY_SSE4A_FLAGS.
441
dabec65d
AM		 4422020-02-17 Alan Modra <amodra@gmail.com>
443
444 * i386-gen.c (cpu_flag_init): Correct last change.
445
af5c13b0
L		 4462020-02-16 H.J. Lu <hongjiu.lu@intel.com>
447
448 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
449 CPU_ANY_SSE4_FLAGS.
450
6867aac0
L		 4512020-02-14 H.J. Lu <hongjiu.lu@intel.com>
452
453 * i386-opc.tbl (movsx): Remove Intel syntax comments.
454 (movzx): Likewise.
455
65fca059
JB		 4562020-02-14 Jan Beulich <jbeulich@suse.com>
457
458 PR gas/25438
459 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
460 destination for Cpu64-only variant.
461 (movzx): Fold patterns.
462 * i386-tbl.h: Re-generate.
463
7deea9aa
JB		 4642020-02-13 Jan Beulich <jbeulich@suse.com>
465
466 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
467 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
468 CPU_ANY_SSE4_FLAGS entry.
469 * i386-init.h: Re-generate.
470
6c0946d0
JB		 4712020-02-12 Jan Beulich <jbeulich@suse.com>
472
473 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
474 with Unspecified, making the present one AT&T syntax only.
475 * i386-tbl.h: Re-generate.
476
ddb56fe6
JB		 4772020-02-12 Jan Beulich <jbeulich@suse.com>
478
479 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
480 * i386-tbl.h: Re-generate.
481
5990e377
JB		 4822020-02-12 Jan Beulich <jbeulich@suse.com>
483
484 PR gas/24546
485 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
486 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
487 Amd64 and Intel64 templates.
488 (call, jmp): Likewise for far indirect variants. Dro
489 Unspecified.
490 * i386-tbl.h: Re-generate.
491
50128d0c
JB		 4922020-02-11 Jan Beulich <jbeulich@suse.com>
493
494 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
495 * i386-opc.h (ShortForm): Delete.
496 (struct i386_opcode_modifier): Remove shortform field.
497 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
498 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
499 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
500 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
501 Drop ShortForm.
502 * i386-tbl.h: Re-generate.
503
1e05b5c4
JB		 5042020-02-11 Jan Beulich <jbeulich@suse.com>
505
506 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
507 fucompi): Drop ShortForm from operand-less templates.
508 * i386-tbl.h: Re-generate.
509
2f5dd314
AM		 5102020-02-11 Alan Modra <amodra@gmail.com>
511
512 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
513 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
514 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
515 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
516 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
517
5aae9ae9
MM		 5182020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
519
520 * arm-dis.c (print_insn_cde): Define 'V' parse character.
521 (cde_opcodes): Add VCX* instructions.
522
4934a27c
MM		 5232020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
524 Matthew Malcomson <matthew.malcomson@arm.com>
525
526 * arm-dis.c (struct cdeopcode32): New.
527 (CDE_OPCODE): New macro.
528 (cde_opcodes): New disassembly table.
529 (regnames): New option to table.
530 (cde_coprocs): New global variable.
531 (print_insn_cde): New
532 (print_insn_thumb32): Use print_insn_cde.
533 (parse_arm_disassembler_options): Parse coprocN args.
534
4b5aaf5f
L		 5352020-02-10 H.J. Lu <hongjiu.lu@intel.com>
536
537 PR gas/25516
538 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
539 with ISA64.
540 * i386-opc.h (AMD64): Removed.
541 (Intel64): Likewose.
542 (AMD64): New.
543 (INTEL64): Likewise.
544 (INTEL64ONLY): Likewise.
545 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
546 * i386-opc.tbl (Amd64): New.
547 (Intel64): Likewise.
548 (Intel64Only): Likewise.
549 Replace AMD64 with Amd64. Update sysenter/sysenter with
550 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
551 * i386-tbl.h: Regenerated.
552
9fc0b501
SB		 5532020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
554
555 PR 25469
556 * z80-dis.c: Add support for GBZ80 opcodes.
557
c5d7be0c
AM		 5582020-02-04 Alan Modra <amodra@gmail.com>
559
560 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
561
44e4546f
AM		 5622020-02-03 Alan Modra <amodra@gmail.com>
563
564 * m32c-ibld.c: Regenerate.
565
b2b1453a
AM		 5662020-02-01 Alan Modra <amodra@gmail.com>
567
568 * frv-ibld.c: Regenerate.
569
4102be5c
JB		 5702020-01-31 Jan Beulich <jbeulich@suse.com>
571
572 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
573 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
574 (OP_E_memory): Replace xmm_mdq_mode case label by
575 vex_scalar_w_dq_mode one.
576 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
577
825bd36c
JB		 5782020-01-31 Jan Beulich <jbeulich@suse.com>
579
580 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
581 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
582 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
583 (intel_operand_size): Drop vex_w_dq_mode case label.
584
c3036ed0
RS		 5852020-01-31 Richard Sandiford <richard.sandiford@arm.com>
586
587 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
588 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
589
0c115f84
AM		 5902020-01-30 Alan Modra <amodra@gmail.com>
591
592 * m32c-ibld.c: Regenerate.
593
bd434cc4
JM		 5942020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
595
596 * bpf-opc.c: Regenerate.
597
aeab2b26
JB		 5982020-01-30 Jan Beulich <jbeulich@suse.com>
599
600 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
601 (dis386): Use them to replace C2/C3 table entries.
602 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
603 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
604 ones. Use Size64 instead of DefaultSize on Intel64 ones.
605 * i386-tbl.h: Re-generate.
606
62b3f548
JB		 6072020-01-30 Jan Beulich <jbeulich@suse.com>
608
609 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
610 forms.
611 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
612 DefaultSize.
613 * i386-tbl.h: Re-generate.
614
1bd8ae10
AM		 6152020-01-30 Alan Modra <amodra@gmail.com>
616
617 * tic4x-dis.c (tic4x_dp): Make unsigned.
618
bc31405e
L		 6192020-01-27 H.J. Lu <hongjiu.lu@intel.com>
620 Jan Beulich <jbeulich@suse.com>
621
622 PR binutils/25445
623 * i386-dis.c (MOVSXD_Fixup): New function.
624 (movsxd_mode): New enum.
625 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
626 (intel_operand_size): Handle movsxd_mode.
627 (OP_E_register): Likewise.
628 (OP_G): Likewise.
629 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
630 register on movsxd. Add movsxd with 16-bit destination register
631 for AMD64 and Intel64 ISAs.
632 * i386-tbl.h: Regenerated.
633
7568c93b
TC		 6342020-01-27 Tamar Christina <tamar.christina@arm.com>
635
636 PR 25403
637 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
638 * aarch64-asm-2.c: Regenerate
639 * aarch64-dis-2.c: Likewise.
640 * aarch64-opc-2.c: Likewise.
641
c006a730
JB		 6422020-01-21 Jan Beulich <jbeulich@suse.com>
643
644 * i386-opc.tbl (sysret): Drop DefaultSize.
645 * i386-tbl.h: Re-generate.
646
c906a69a
JB		 6472020-01-21 Jan Beulich <jbeulich@suse.com>
648
649 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
650 Dword.
651 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
652 * i386-tbl.h: Re-generate.
653
26916852
NC		 6542020-01-20 Nick Clifton <nickc@redhat.com>
655
656 * po/de.po: Updated German translation.
657 * po/pt_BR.po: Updated Brazilian Portuguese translation.
658 * po/uk.po: Updated Ukranian translation.
659
4d6cbb64
AM		 6602020-01-20 Alan Modra <amodra@gmail.com>
661
662 * hppa-dis.c (fput_const): Remove useless cast.
663
2bddb71a
AM		 6642020-01-20 Alan Modra <amodra@gmail.com>
665
666 * arm-dis.c (print_insn_arm): Wrap 'T' value.
667
1b1bb2c6
NC		 6682020-01-18 Nick Clifton <nickc@redhat.com>
669
670 * configure: Regenerate.
671 * po/opcodes.pot: Regenerate.
672
ae774686
NC		 6732020-01-18 Nick Clifton <nickc@redhat.com>
674
675 Binutils 2.34 branch created.
676
07f1f3aa
CB		 6772020-01-17 Christian Biesinger <cbiesinger@google.com>
678
679 * opintl.h: Fix spelling error (seperate).
680
42e04b36
L		 6812020-01-17 H.J. Lu <hongjiu.lu@intel.com>
682
683 * i386-opc.tbl: Add {vex} pseudo prefix.
684 * i386-tbl.h: Regenerated.
685
2da2eaf4
AV		 6862020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
687
688 PR 25376
689 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
690 (neon_opcodes): Likewise.
691 (select_arm_features): Make sure we enable MVE bits when selecting
692 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
693 any architecture.
694
d0849eed
JB		 6952020-01-16 Jan Beulich <jbeulich@suse.com>
696
697 * i386-opc.tbl: Drop stale comment from XOP section.
698
9cf70a44
JB		 6992020-01-16 Jan Beulich <jbeulich@suse.com>
700
701 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
702 (extractps): Add VexWIG to SSE2AVX forms.
703 * i386-tbl.h: Re-generate.
704
4814632e
JB		 7052020-01-16 Jan Beulich <jbeulich@suse.com>
706
707 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
708 Size64 from and use VexW1 on SSE2AVX forms.
709 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
710 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
711 * i386-tbl.h: Re-generate.
712
aad09917
AM		 7132020-01-15 Alan Modra <amodra@gmail.com>
714
715 * tic4x-dis.c (tic4x_version): Make unsigned long.
716 (optab, optab_special, registernames): New file scope vars.
717 (tic4x_print_register): Set up registernames rather than
718 malloc'd registertable.
719 (tic4x_disassemble): Delete optable and optable_special. Use
720 optab and optab_special instead. Throw away old optab,
721 optab_special and registernames when info->mach changes.
722
7a6bf3be
SB		 7232020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
724
725 PR 25377
726 * z80-dis.c (suffix): Use .db instruction to generate double
727 prefix.
728
ca1eaac0
AM		 7292020-01-14 Alan Modra <amodra@gmail.com>
730
731 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
732 values to unsigned before shifting.
733
1d67fe3b
TT		 7342020-01-13 Thomas Troeger <tstroege@gmx.de>
735
736 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
737 flow instructions.
738 (print_insn_thumb16, print_insn_thumb32): Likewise.
739 (print_insn): Initialize the insn info.
740 * i386-dis.c (print_insn): Initialize the insn info fields, and
741 detect jumps.
742
5e4f7e05
CZ		 7432012-01-13 Claudiu Zissulescu <claziss@gmail.com>
744
745 * arc-opc.c (C_NE): Make it required.
746
b9fe6b8a
CZ		 7472012-01-13 Claudiu Zissulescu <claziss@gmail.com>
748
749 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
750 reserved register name.
751
90dee485
AM		 7522020-01-13 Alan Modra <amodra@gmail.com>
753
754 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
755 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
756
febda64f
AM		 7572020-01-13 Alan Modra <amodra@gmail.com>
758
759 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
760 result of wasm_read_leb128 in a uint64_t and check that bits
761 are not lost when copying to other locals. Use uint32_t for
762 most locals. Use PRId64 when printing int64_t.
763
df08b588
AM		 7642020-01-13 Alan Modra <amodra@gmail.com>
765
766 * score-dis.c: Formatting.
767 * score7-dis.c: Formatting.
768
b2c759ce
AM		 7692020-01-13 Alan Modra <amodra@gmail.com>
770
771 * score-dis.c (print_insn_score48): Use unsigned variables for
772 unsigned values. Don't left shift negative values.
773 (print_insn_score32): Likewise.
774 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
775
5496abe1
AM		 7762020-01-13 Alan Modra <amodra@gmail.com>
777
778 * tic4x-dis.c (tic4x_print_register): Remove dead code.
779
202e762b
AM		 7802020-01-13 Alan Modra <amodra@gmail.com>
781
782 * fr30-ibld.c: Regenerate.
783
7ef412cf
AM		 7842020-01-13 Alan Modra <amodra@gmail.com>
785
786 * xgate-dis.c (print_insn): Don't left shift signed value.
787 (ripBits): Formatting, use 1u.
788
7f578b95
AM		 7892020-01-10 Alan Modra <amodra@gmail.com>
790
791 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
792 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
793
441af85b
AM		 7942020-01-10 Alan Modra <amodra@gmail.com>
795
796 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
797 and XRREG value earlier to avoid a shift with negative exponent.
798 * m10200-dis.c (disassemble): Similarly.
799
bce58db4
NC		 8002020-01-09 Nick Clifton <nickc@redhat.com>
801
802 PR 25224
803 * z80-dis.c (ld_ii_ii): Use correct cast.
804
40c75bc8
SB		 8052020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
806
807 PR 25224
808 * z80-dis.c (ld_ii_ii): Use character constant when checking
809 opcode byte value.
810
d835a58b
JB		 8112020-01-09 Jan Beulich <jbeulich@suse.com>
812
813 * i386-dis.c (SEP_Fixup): New.
814 (SEP): Define.
815 (dis386_twobyte): Use it for sysenter/sysexit.
816 (enum x86_64_isa): Change amd64 enumerator to value 1.
817 (OP_J): Compare isa64 against intel64 instead of amd64.
818 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
819 forms.
820 * i386-tbl.h: Re-generate.
821
030a2e78
AM		 8222020-01-08 Alan Modra <amodra@gmail.com>
823
824 * z8k-dis.c: Include libiberty.h
825 (instr_data_s): Make max_fetched unsigned.
826 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
827 Don't exceed byte_info bounds.
828 (output_instr): Make num_bytes unsigned.
829 (unpack_instr): Likewise for nibl_count and loop.
830 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
831 idx unsigned.
832 * z8k-opc.h: Regenerate.
833
bb82aefe
SV		 8342020-01-07 Shahab Vahedi <shahab@synopsys.com>
835
836 * arc-tbl.h (llock): Use 'LLOCK' as class.
837 (llockd): Likewise.
838 (scond): Use 'SCOND' as class.
839 (scondd): Likewise.
840 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
841 (scondd): Likewise.
842
cc6aa1a6
AM		 8432020-01-06 Alan Modra <amodra@gmail.com>
844
845 * m32c-ibld.c: Regenerate.
846
660e62b1
AM		 8472020-01-06 Alan Modra <amodra@gmail.com>
848
849 PR 25344
850 * z80-dis.c (suffix): Don't use a local struct buffer copy.
851 Peek at next byte to prevent recursion on repeated prefix bytes.
852 Ensure uninitialised "mybuf" is not accessed.
853 (print_insn_z80): Don't zero n_fetch and n_used here,..
854 (print_insn_z80_buf): ..do it here instead.
855
c9ae58fe
AM		 8562020-01-04 Alan Modra <amodra@gmail.com>
857
858 * m32r-ibld.c: Regenerate.
859
5f57d4ec
AM		 8602020-01-04 Alan Modra <amodra@gmail.com>
861
862 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
863
2c5c1196
AM		 8642020-01-04 Alan Modra <amodra@gmail.com>
865
866 * crx-dis.c (match_opcode): Avoid shift left of signed value.
867
2e98c6c5
AM		 8682020-01-04 Alan Modra <amodra@gmail.com>
869
870 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
871
567dfba2
JB		 8722020-01-03 Jan Beulich <jbeulich@suse.com>
873
5437a02a
JB		 874 * aarch64-tbl.h (aarch64_opcode_table): Use
875 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
876
8772020-01-03 Jan Beulich <jbeulich@suse.com>
878
879 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 880 forms of SUDOT and USDOT.
881
8c45011a
JB		 8822020-01-03 Jan Beulich <jbeulich@suse.com>
883
5437a02a 884 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 885 uzip{1,2}.
886 * opcodes/aarch64-dis-2.c: Re-generate.
887
f4950f76
JB		 8882020-01-03 Jan Beulich <jbeulich@suse.com>
889
5437a02a 890 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 891 FMMLA encoding.
892 * opcodes/aarch64-dis-2.c: Re-generate.
893
6655dba2
SB		 8942020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
895
896 * z80-dis.c: Add support for eZ80 and Z80 instructions.
897
b14ce8bf
AM		 8982020-01-01 Alan Modra <amodra@gmail.com>
899
900 Update year range in copyright notice of all files.
901
0b114740 902For older changes see ChangeLog-2019
3499769a 903\f
0b114740 904Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 905
906Copying and distribution of this file, with or without modification,
907are permitted in any medium without royalty provided the copyright
908notice and this notice are preserved.
909
910Local Variables:
911mode: change-log
912left-margin: 8
913fill-column: 74
914version-control: never
915End:
GDB Binutils - Deliverables
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