projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* app.c (do_scrub_chars): Do not UNGET an EOF value.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
fa452fa6
PB		 12008-06-13 Peter Bergner <bergner@vnet.ibm.com>
2
3 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
4 ppc_cpu_t typedef.
5 (struct dis_private): New.
6 (POWERPC_DIALECT): New define.
7 (powerpc_dialect): Renamed to...
8 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
9 struct dis_private.
10 (print_insn_big_powerpc): Update for using structure in
11 info->private_data.
12 (print_insn_little_powerpc): Likewise.
13 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
14 (skip_optional_operands): Likewise.
15 (print_insn_powerpc): Likewise. Remove initialization of dialect.
16 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
17 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
18 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
19 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
20 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
21 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
22 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
23 param to be of type ppc_cpu_t. Update prototype.
24
bb35fb24
NC		 252008-06-12 Adam Nemet <anemet@caviumnetworks.com>
26
27 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
28 +s, +S.
29 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
30 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
31 syncw, syncws, vm3mulu, vm0 and vmulu.
32
dd3cbb7e
NC		 33 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
34 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
35 seqi, sne and snei.
36
a5dabbb0
L		 372008-05-30 H.J. Lu <hongjiu.lu@intel.com>
38
39 * i386-opc.tbl: Add vmovd with 64bit operand.
40 * i386-tbl.h: Regenerated.
41
725a9891
MS		 422008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
43
44 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
45
cbc80391
L		 462008-05-22 H.J. Lu <hongjiu.lu@intel.com>
47
48 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
49 * i386-tbl.h: Regenerated.
50
116615c5
L		 512008-05-22 H.J. Lu <hongjiu.lu@intel.com>
52
53 PR gas/6517
54 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
55 into 32bit and 64bit. Remove Reg64|Qword and add
56 IgnoreSize|No_qSuf on 32bit version.
57 * i386-tbl.h: Regenerated.
58
d9479f2d
L		 592008-05-21 H.J. Lu <hongjiu.lu@intel.com>
60
61 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
62 * i386-tbl.h: Regenerated.
63
3ce6fddb
NC		 642008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
65
66 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
67
8944f3c2
AM		 682008-05-14 Alan Modra <amodra@bigpond.net.au>
69
70 * Makefile.am: Run "make dep-am".
71 * Makefile.in: Regenerate.
72
f1f8f695
L		 732008-05-02 H.J. Lu <hongjiu.lu@intel.com>
74
75 * i386-dis.c (MOVBE_Fixup): New.
76 (Mo): Likewise.
77 (PREFIX_0F3880): Likewise.
78 (PREFIX_0F3881): Likewise.
79 (PREFIX_0F38F0): Updated.
80 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
81 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
82 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
83
84 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
85 CPU_EPT_FLAGS.
86 (cpu_flags): Add CpuMovbe and CpuEPT.
87
88 * i386-opc.h (CpuMovbe): New.
89 (CpuEPT): Likewise.
90 (CpuLM): Updated.
91 (i386_cpu_flags): Add cpumovbe and cpuept.
92
93 * i386-opc.tbl: Add entries for movbe and EPT instructions.
94 * i386-init.h: Regenerated.
95 * i386-tbl.h: Likewise.
96
89aa3097
AN		 972008-04-29 Adam Nemet <anemet@caviumnetworks.com>
98
99 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
100 the two drem and the two dremu macros.
101
39c5c168
AN		 1022008-04-28 Adam Nemet <anemet@caviumnetworks.com>
103
104 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
105 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
106 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
107 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
108
f04d18b7
DM		 1092008-04-25 David S. Miller <davem@davemloft.net>
110
111 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
112 instead of %sys_tick_cmpr, as suggested in architecture manuals.
113
6194aaab
L		 1142008-04-23 Paolo Bonzini <bonzini@gnu.org>
115
116 * aclocal.m4: Regenerate.
117 * configure: Regenerate.
118
1a6b486f
DM		 1192008-04-23 David S. Miller <davem@davemloft.net>
120
121 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
122 extended values.
123 (prefetch_table): Add missing values.
124
81f8a913
L		 1252008-04-22 H.J. Lu <hongjiu.lu@intel.com>
126
127 * i386-gen.c (opcode_modifiers): Add NoAVX.
128
129 * i386-opc.h (NoAVX): New.
130 (OldGcc): Updated.
131 (i386_opcode_modifier): Add noavx.
132
133 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
134 instructions which don't have AVX equivalent.
135 * i386-tbl.h: Regenerated.
136
dae39acc
L		 1372008-04-18 H.J. Lu <hongjiu.lu@intel.com>
138
139 * i386-dis.c (OP_VEX_FMA): New.
140 (OP_EX_VexImmW): Likewise.
141 (VexFMA): Likewise.
142 (Vex128FMA): Likewise.
143 (EXVexImmW): Likewise.
144 (get_vex_imm8): Likewise.
145 (OP_EX_VexReg): Likewise.
146 (vex_i4_done): Renamed to ...
147 (vex_w_done): This.
148 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
149 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
150 FMA instructions.
151 (print_insn): Updated.
152 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
153 (OP_REG_VexI4): Check invalid high registers.
154
ce886ab1
DR		 1552008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
156 Michael Meissner <michael.meissner@amd.com>
157
158 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
159 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 160
19a6653c
AM		 1612008-04-14 Edmar Wienskoski <edmar@freescale.com>
162
163 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
164 accept Power E500MC instructions.
165 (print_ppc_disassembler_options): Document -Me500mc.
166 * ppc-opc.c (DUIS, DUI, T): New.
167 (XRT, XRTRA): Likewise.
168 (E500MC): Likewise.
169 (powerpc_opcodes): Add new Power E500MC instructions.
170
112b7c50
AK		 1712008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
172
173 * s390-dis.c (init_disasm): Evaluate disassembler_options.
174 (print_s390_disassembler_options): New function.
175 * disassemble.c (disassembler_usage): Invoke
176 print_s390_disassembler_options.
177
7ff42648
AK		 1782008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
179
180 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
181 of local variables used for mnemonic parsing: prefix, suffix and
182 number.
183
45a5551e
AK		 1842008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
185
186 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
187 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
188 (s390_crb_extensions): New extensions table.
189 (insertExpandedMnemonic): Handle '$' tag.
190 * s390-opc.txt: Remove conditional jump variants which can now
191 be expanded automatically.
192 Replace '*' tag with '$' in the compare and branch instructions.
193
06c8514a
L		 1942008-04-07 H.J. Lu <hongjiu.lu@intel.com>
195
196 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
197 (PREFIX_VEX_3AXX): Likewis.
198
b122c285
L		 1992008-04-07 H.J. Lu <hongjiu.lu@intel.com>
200
201 * i386-opc.tbl: Remove 4 extra blank lines.
202
594ab6a3
L		 2032008-04-04 H.J. Lu <hongjiu.lu@intel.com>
204
205 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
206 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
207 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
208 * i386-opc.tbl: Likewise.
209
210 * i386-opc.h (CpuCLMUL): Renamed to ...
211 (CpuPCLMUL): This.
212 (CpuFMA): Updated.
213 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
214
215 * i386-init.h: Regenerated.
216
c0f3af97
L		 2172008-04-03 H.J. Lu <hongjiu.lu@intel.com>
218
219 * i386-dis.c (OP_E_register): New.
220 (OP_E_memory): Likewise.
221 (OP_VEX): Likewise.
222 (OP_EX_Vex): Likewise.
223 (OP_EX_VexW): Likewise.
224 (OP_XMM_Vex): Likewise.
225 (OP_XMM_VexW): Likewise.
226 (OP_REG_VexI4): Likewise.
227 (PCLMUL_Fixup): Likewise.
228 (VEXI4_Fixup): Likewise.
229 (VZERO_Fixup): Likewise.
230 (VCMP_Fixup): Likewise.
231 (VPERMIL2_Fixup): Likewise.
232 (rex_original): Likewise.
233 (rex_ignored): Likewise.
234 (Mxmm): Likewise.
235 (XMM): Likewise.
236 (EXxmm): Likewise.
237 (EXxmmq): Likewise.
238 (EXymmq): Likewise.
239 (Vex): Likewise.
240 (Vex128): Likewise.
241 (Vex256): Likewise.
242 (VexI4): Likewise.
243 (EXdVex): Likewise.
244 (EXqVex): Likewise.
245 (EXVexW): Likewise.
246 (EXdVexW): Likewise.
247 (EXqVexW): Likewise.
248 (XMVex): Likewise.
249 (XMVexW): Likewise.
250 (XMVexI4): Likewise.
251 (PCLMUL): Likewise.
252 (VZERO): Likewise.
253 (VCMP): Likewise.
254 (VPERMIL2): Likewise.
255 (xmm_mode): Likewise.
256 (xmmq_mode): Likewise.
257 (ymmq_mode): Likewise.
258 (vex_mode): Likewise.
259 (vex128_mode): Likewise.
260 (vex256_mode): Likewise.
261 (USE_VEX_C4_TABLE): Likewise.
262 (USE_VEX_C5_TABLE): Likewise.
263 (USE_VEX_LEN_TABLE): Likewise.
264 (VEX_C4_TABLE): Likewise.
265 (VEX_C5_TABLE): Likewise.
266 (VEX_LEN_TABLE): Likewise.
267 (REG_VEX_XX): Likewise.
268 (MOD_VEX_XXX): Likewise.
269 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
270 (PREFIX_0F3A44): Likewise.
271 (PREFIX_0F3ADF): Likewise.
272 (PREFIX_VEX_XXX): Likewise.
273 (VEX_OF): Likewise.
274 (VEX_OF38): Likewise.
275 (VEX_OF3A): Likewise.
276 (VEX_LEN_XXX): Likewise.
277 (vex): Likewise.
278 (need_vex): Likewise.
279 (need_vex_reg): Likewise.
280 (vex_i4_done): Likewise.
281 (vex_table): Likewise.
282 (vex_len_table): Likewise.
283 (OP_REG_VexI4): Likewise.
284 (vex_cmp_op): Likewise.
285 (pclmul_op): Likewise.
286 (vpermil2_op): Likewise.
287 (m_mode): Updated.
288 (es_reg): Likewise.
289 (PREFIX_0F38F0): Likewise.
290 (PREFIX_0F3A60): Likewise.
291 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
292 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
293 and PREFIX_VEX_XXX entries.
294 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
295 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
296 PREFIX_0F3ADF.
297 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
298 Add MOD_VEX_XXX entries.
299 (ckprefix): Initialize rex_original and rex_ignored. Store the
300 REX byte in rex_original.
301 (get_valid_dis386): Handle the implicit prefix in VEX prefix
302 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
303 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
304 calling get_valid_dis386. Use rex_original and rex_ignored when
305 printing out REX.
306 (putop): Handle "XY".
307 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
308 ymmq_mode.
309 (OP_E_extended): Updated to use OP_E_register and
310 OP_E_memory.
311 (OP_XMM): Handle VEX.
312 (OP_EX): Likewise.
313 (XMM_Fixup): Likewise.
314 (CMP_Fixup): Use ARRAY_SIZE.
315
316 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
317 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
318 (operand_type_init): Add OPERAND_TYPE_REGYMM and
319 OPERAND_TYPE_VEX_IMM4.
320 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
321 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
322 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
323 VexImmExt and SSE2AVX.
324 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
325
326 * i386-opc.h (CpuAVX): New.
327 (CpuAES): Likewise.
328 (CpuCLMUL): Likewise.
329 (CpuFMA): Likewise.
330 (Vex): Likewise.
331 (Vex256): Likewise.
332 (VexNDS): Likewise.
333 (VexNDD): Likewise.
334 (VexW0): Likewise.
335 (VexW1): Likewise.
336 (Vex0F): Likewise.
337 (Vex0F38): Likewise.
338 (Vex0F3A): Likewise.
339 (Vex3Sources): Likewise.
340 (VexImmExt): Likewise.
341 (SSE2AVX): Likewise.
342 (RegYMM): Likewise.
343 (Ymmword): Likewise.
344 (Vex_Imm4): Likewise.
345 (Implicit1stXmm0): Likewise.
346 (CpuXsave): Updated.
347 (CpuLM): Likewise.
348 (ByteOkIntel): Likewise.
349 (OldGcc): Likewise.
350 (Control): Likewise.
351 (Unspecified): Likewise.
352 (OTMax): Likewise.
353 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
354 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
355 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
356 vex3sources, veximmext and sse2avx.
357 (i386_operand_type): Add regymm, ymmword and vex_imm4.
358
359 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
360
361 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
362
363 * i386-init.h: Regenerated.
364 * i386-tbl.h: Likewise.
365
b21c9cb4
BS		 3662008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
367
368 From Robin Getz <robin.getz@analog.com>
369 * bfin-dis.c (bu32): Typedef.
370 (enum const_forms_t): Add c_uimm32 and c_huimm32.
371 (constant_formats[]): Add uimm32 and huimm16.
372 (fmtconst_val): New.
373 (uimm32): Define.
374 (huimm32): Define.
375 (imm16_val): Define.
376 (luimm16_val): Define.
377 (struct saved_state): Define.
378 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
379 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
380 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
381 (get_allreg): New.
382 (decode_LDIMMhalf_0): Print out the whole register value.
383
ee171c8f
BS		 384 From Jie Zhang <jie.zhang@analog.com>
385 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
386 multiply and multiply-accumulate to data register instruction.
387
086134ec
BS		 388 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
389 c_imm32, c_huimm32e): Define.
390 (constant_formats): Add flags for printing decimal, leading spaces, and
391 exact symbols.
392 (comment, parallel): Add global flags in all disassembly.
393 (fmtconst): Take advantage of new flags, and print default in hex.
394 (fmtconst_val): Likewise.
395 (decode_macfunc): Be consistant with spaces, tabs, comments,
396 capitalization in disassembly, fix minor coding style issues.
397 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
398 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
399 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
400 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
401 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
402 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
403 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
404 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
405 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
406 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
407 _print_insn_bfin, print_insn_bfin): Likewise.
408
58c85be7
RW		 4092008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
410
411 * aclocal.m4: Regenerate.
412 * configure: Likewise.
413 * Makefile.in: Likewise.
414
50e7d84b
AM		 4152008-03-13 Alan Modra <amodra@bigpond.net.au>
416
417 * Makefile.am: Run "make dep-am".
418 * Makefile.in: Regenerate.
419 * configure: Regenerate.
420
de866fcc
AM		 4212008-03-07 Alan Modra <amodra@bigpond.net.au>
422
423 * ppc-opc.c (powerpc_opcodes): Order and format.
424
28dbc079
L		 4252008-03-01 H.J. Lu <hongjiu.lu@intel.com>
426
427 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
428 * i386-tbl.h: Regenerated.
429
849830bd
L		 4302008-02-23 H.J. Lu <hongjiu.lu@intel.com>
431
432 * i386-opc.tbl: Disallow 16-bit near indirect branches for
433 x86-64.
434 * i386-tbl.h: Regenerated.
435
743ddb6b
JB		 4362008-02-21 Jan Beulich <jbeulich@novell.com>
437
438 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
439 and Fword for far indirect jmp. Allow Reg16 and Word for near
440 indirect jmp on x86-64. Disallow Fword for lcall.
441 * i386-tbl.h: Re-generate.
442
796d5313
NC		 4432008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
444
445 * cr16-opc.c (cr16_num_optab): Defined
446
65da13b5
L		 4472008-02-16 H.J. Lu <hongjiu.lu@intel.com>
448
449 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
450 * i386-init.h: Regenerated.
451
0e336180
NC		 4522008-02-14 Nick Clifton <nickc@redhat.com>
453
454 PR binutils/5524
455 * configure.in (SHARED_LIBADD): Select the correct host specific
456 file extension for shared libraries.
457 * configure: Regenerate.
458
b7240065
JB		 4592008-02-13 Jan Beulich <jbeulich@novell.com>
460
461 * i386-opc.h (RegFlat): New.
462 * i386-reg.tbl (flat): Add.
463 * i386-tbl.h: Re-generate.
464
34b772a6
JB		 4652008-02-13 Jan Beulich <jbeulich@novell.com>
466
467 * i386-dis.c (a_mode): New.
468 (cond_jump_mode): Adjust.
469 (Ma): Change to a_mode.
470 (intel_operand_size): Handle a_mode.
471 * i386-opc.tbl: Allow Dword and Qword for bound.
472 * i386-tbl.h: Re-generate.
473
a60de03c
JB		 4742008-02-13 Jan Beulich <jbeulich@novell.com>
475
476 * i386-gen.c (process_i386_registers): Process new fields.
477 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
478 unsigned char. Add dw2_regnum and Dw2Inval.
479 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
480 register names.
481 * i386-tbl.h: Re-generate.
482
f03fe4c1
L		 4832008-02-11 H.J. Lu <hongjiu.lu@intel.com>
484
4b6bc8eb 485 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 486 * i386-init.h: Updated.
487
475a2301
L		 4882008-02-11 H.J. Lu <hongjiu.lu@intel.com>
489
490 * i386-gen.c (cpu_flags): Add CpuXsave.
491
492 * i386-opc.h (CpuXsave): New.
4b6bc8eb 493 (CpuLM): Updated.
475a2301
L		 494 (i386_cpu_flags): Add cpuxsave.
495
496 * i386-dis.c (MOD_0FAE_REG_4): New.
497 (RM_0F01_REG_2): Likewise.
498 (MOD_0FAE_REG_5): Updated.
499 (RM_0F01_REG_3): Likewise.
500 (reg_table): Use MOD_0FAE_REG_4.
501 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
502 for xrstor.
503 (rm_table): Add RM_0F01_REG_2.
504
505 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
506 * i386-init.h: Regenerated.
507 * i386-tbl.h: Likewise.
508
595785c6 5092008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 510
595785c6
JB		 511 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
512 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
513 * i386-tbl.h: Re-generate.
514
bb8541b9
L		 5152008-02-04 H.J. Lu <hongjiu.lu@intel.com>
516
517 PR 5715
518 * configure: Regenerated.
519
57b592a3
AN		 5202008-02-04 Adam Nemet <anemet@caviumnetworks.com>
521
522 * mips-dis.c: Update copyright.
523 (mips_arch_choices): Add Octeon.
524 * mips-opc.c: Update copyright.
525 (IOCT): New macro.
526 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
527
930bb4cf
AM		 5282008-01-29 Alan Modra <amodra@bigpond.net.au>
529
530 * ppc-opc.c: Support optional L form mtmsr.
531
82c18208
L		 5322008-01-24 H.J. Lu <hongjiu.lu@intel.com>
533
534 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
535
599121aa
L		 5362008-01-23 H.J. Lu <hongjiu.lu@intel.com>
537
538 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
539 * i386-init.h: Regenerated.
540
80098f51
TG		 5412008-01-23 Tristan Gingold <gingold@adacore.com>
542
543 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
544 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
545
115c7c25
L		 5462008-01-22 H.J. Lu <hongjiu.lu@intel.com>
547
548 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
549 (cpu_flags): Likewise.
550
551 * i386-opc.h (CpuMMX2): Removed.
552 (CpuSSE): Updated.
553
554 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
555 * i386-init.h: Regenerated.
556 * i386-tbl.h: Likewise.
557
6305a203
L		 5582008-01-22 H.J. Lu <hongjiu.lu@intel.com>
559
560 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
561 CPU_SMX_FLAGS.
562 * i386-init.h: Regenerated.
563
fd07a1c8
L		 5642008-01-15 H.J. Lu <hongjiu.lu@intel.com>
565
566 * i386-opc.tbl: Use Qword on movddup.
567 * i386-tbl.h: Regenerated.
568
321fd21e
L		 5692008-01-15 H.J. Lu <hongjiu.lu@intel.com>
570
571 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
572 * i386-tbl.h: Regenerated.
573
4ee52178
L		 5742008-01-15 H.J. Lu <hongjiu.lu@intel.com>
575
576 * i386-dis.c (Mx): New.
577 (PREFIX_0FC3): Likewise.
578 (PREFIX_0FC7_REG_6): Updated.
579 (dis386_twobyte): Use PREFIX_0FC3.
580 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
581 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
582 movntss.
583
5c07affc
L		 5842008-01-14 H.J. Lu <hongjiu.lu@intel.com>
585
586 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
587 (operand_types): Add Mem.
588
589 * i386-opc.h (IntelSyntax): New.
590 * i386-opc.h (Mem): New.
591 (Byte): Updated.
592 (Opcode_Modifier_Max): Updated.
593 (i386_opcode_modifier): Add intelsyntax.
594 (i386_operand_type): Add mem.
595
596 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
597 instructions.
598
599 * i386-reg.tbl: Add size for accumulator.
600
601 * i386-init.h: Regenerated.
602 * i386-tbl.h: Likewise.
603
0d6a2f58
L		 6042008-01-13 H.J. Lu <hongjiu.lu@intel.com>
605
606 * i386-opc.h (Byte): Fix a typo.
607
7d5e4556
L		 6082008-01-12 H.J. Lu <hongjiu.lu@intel.com>
609
610 PR gas/5534
611 * i386-gen.c (operand_type_init): Add Dword to
612 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
613 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
614 Qword and Xmmword.
615 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
616 Xmmword, Unspecified and Anysize.
617 (set_bitfield): Make Mmword an alias of Qword. Make Oword
618 an alias of Xmmword.
619
620 * i386-opc.h (CheckSize): Removed.
621 (Byte): Updated.
622 (Word): Likewise.
623 (Dword): Likewise.
624 (Qword): Likewise.
625 (Xmmword): Likewise.
626 (FWait): Updated.
627 (OTMax): Likewise.
628 (i386_opcode_modifier): Remove checksize, byte, word, dword,
629 qword and xmmword.
630 (Fword): New.
631 (TBYTE): Likewise.
632 (Unspecified): Likewise.
633 (Anysize): Likewise.
634 (i386_operand_type): Add byte, word, dword, fword, qword,
635 tbyte xmmword, unspecified and anysize.
636
637 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
638 Tbyte, Xmmword, Unspecified and Anysize.
639
640 * i386-reg.tbl: Add size for accumulator.
641
642 * i386-init.h: Regenerated.
643 * i386-tbl.h: Likewise.
644
b5b1fc4f
L		 6452008-01-10 H.J. Lu <hongjiu.lu@intel.com>
646
647 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
648 (REG_0F18): Updated.
649 (reg_table): Updated.
650 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
651 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
652
50e8458f
L		 6532008-01-08 H.J. Lu <hongjiu.lu@intel.com>
654
655 * i386-gen.c (set_bitfield): Use fail () on error.
656
3d4d5afa
L		 6572008-01-08 H.J. Lu <hongjiu.lu@intel.com>
658
659 * i386-gen.c (lineno): New.
660 (filename): Likewise.
661 (set_bitfield): Report filename and line numer on error.
662 (process_i386_opcodes): Set filename and update lineno.
663 (process_i386_registers): Likewise.
664
e1d4d893
L		 6652008-01-05 H.J. Lu <hongjiu.lu@intel.com>
666
667 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
668 ATTSyntax.
669
670 * i386-opc.h (IntelMnemonic): Renamed to ..
671 (ATTSyntax): This
672 (Opcode_Modifier_Max): Updated.
673 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
674 and intelsyntax.
675
8944f3c2 676 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 677 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
678 * i386-tbl.h: Regenerated.
679
6f143e4d
L		 6802008-01-04 H.J. Lu <hongjiu.lu@intel.com>
681
682 * i386-gen.c: Update copyright to 2008.
683 * i386-opc.h: Likewise.
684 * i386-opc.tbl: Likewise.
685
686 * i386-init.h: Regenerated.
687 * i386-tbl.h: Likewise.
688
c6add537
L		 6892008-01-04 H.J. Lu <hongjiu.lu@intel.com>
690
691 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
692 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
693 * i386-tbl.h: Regenerated.
694
3629bb00
L		 6952008-01-03 H.J. Lu <hongjiu.lu@intel.com>
696
697 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
698 CpuSSE4_2_Or_ABM.
699 (cpu_flags): Likewise.
700
701 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
702 (CpuSSE4_2_Or_ABM): Likewise.
703 (CpuLM): Updated.
704 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
705
706 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
707 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
708 and CpuPadLock, respectively.
709 * i386-init.h: Regenerated.
710 * i386-tbl.h: Likewise.
711
24995bd6
L		 7122008-01-03 H.J. Lu <hongjiu.lu@intel.com>
713
714 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
715
716 * i386-opc.h (No_xSuf): Removed.
717 (CheckSize): Updated.
718
719 * i386-tbl.h: Regenerated.
720
e0329a22
L		 7212008-01-02 H.J. Lu <hongjiu.lu@intel.com>
722
723 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
724 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
725 CPU_SSE5_FLAGS.
726 (cpu_flags): Add CpuSSE4_2_Or_ABM.
727
728 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
729 (CpuLM): Updated.
730 (i386_cpu_flags): Add cpusse4_2_or_abm.
731
732 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
733 CpuABM|CpuSSE4_2 on popcnt.
734 * i386-init.h: Regenerated.
735 * i386-tbl.h: Likewise.
736
f2a9c676
L		 7372008-01-02 H.J. Lu <hongjiu.lu@intel.com>
738
739 * i386-opc.h: Update comments.
740
d978b5be
L		 7412008-01-02 H.J. Lu <hongjiu.lu@intel.com>
742
743 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
744 * i386-opc.h: Likewise.
745 * i386-opc.tbl: Likewise.
746
582d5edd
L		 7472008-01-02 H.J. Lu <hongjiu.lu@intel.com>
748
749 PR gas/5534
750 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
751 Byte, Word, Dword, QWord and Xmmword.
752
753 * i386-opc.h (No_xSuf): New.
754 (CheckSize): Likewise.
755 (Byte): Likewise.
756 (Word): Likewise.
757 (Dword): Likewise.
758 (QWord): Likewise.
759 (Xmmword): Likewise.
760 (FWait): Updated.
761 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
762 Dword, QWord and Xmmword.
763
764 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
765 used.
766 * i386-tbl.h: Regenerated.
767
3fe15143
MK		 7682008-01-02 Mark Kettenis <kettenis@gnu.org>
769
770 * m88k-dis.c (instructions): Fix fcvt.* instructions.
771 From Miod Vallat.
772
6c7ac64e 773For older changes see ChangeLog-2007
252b5132
RH		 774\f
775Local Variables:
2f6d2f85
NC		 776mode: change-log
777left-margin: 8
778fill-column: 74
252b5132
RH		 779version-control: never
780End:
GDB Binutils - Deliverables
This page took 0.498407 seconds and 4 git commands to generate.