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Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, even when...
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
02f12cd4
VK		 12015-10-27 Vinay Kumar <vinay.g@kpit.com>
2
3 PR binutils/19157
4 * rl78-decode.opc: Add 'a' print operator to mov instructions
5 using stack pointer plus index addressing.
6 * rl78-decode.c: Regenerate.
7
485f23cf
AK		 82015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
9
10 * s390-opc.c: Fix comment.
11 * s390-opc.txt: Change instruction type for troo, trot, trto, and
12 trtt to RRF_U0RER since the second parameter does not need to be a
13 register pair.
14
3f94e60d
NC		 152015-10-08 Nick Clifton <nickc@redhat.com>
16
17 * arc-dis.c (print_insn_arc): Initiallise insn array.
18
875880c6
YQ		 192015-10-07 Yao Qi <yao.qi@linaro.org>
20
21 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
22 'name' rather than 'template'.
23 * aarch64-opc.c (aarch64_print_operand): Likewise.
24
886a2506
NC		 252015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
26
27 * arc-dis.c: Revamped file for ARC support
28 * arc-dis.h: Likewise.
29 * arc-ext.c: Likewise.
30 * arc-ext.h: Likewise.
31 * arc-opc.c: Likewise.
32 * arc-fxi.h: New file.
33 * arc-regs.h: Likewise.
34 * arc-tbl.h: Likewise.
35
36f4aab1
YQ		 362015-10-02 Yao Qi <yao.qi@linaro.org>
37
38 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
39 argument insn type to aarch64_insn. Rename to ...
40 (aarch64_decode_insn): ... it.
41 (print_insn_aarch64_word): Caller updated.
42
7232d389
YQ		 432015-10-02 Yao Qi <yao.qi@linaro.org>
44
45 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
46 (print_insn_aarch64_word): Caller updated.
47
7ecc513a
DV		 482015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
49
50 * s390-mkopc.c (main): Parse htm and vx flag.
51 * s390-opc.txt: Mark instructions from the hardware transactional
52 memory and vector facilities with the "htm"/"vx" flag.
53
b08b78e7
NC		 542015-09-28 Nick Clifton <nickc@redhat.com>
55
56 * po/de.po: Updated German translation.
57
36f7a941
TR		 582015-09-28 Tom Rix <tom@bumblecow.com>
59
60 * ppc-opc.c (PPC500): Mark some opcodes as invalid
61
b6518b38
NC		 622015-09-23 Nick Clifton <nickc@redhat.com>
63
64 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
65 function.
66 * tic30-dis.c (print_branch): Likewise.
67 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
68 value before left shifting.
69 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
70 * hppa-dis.c (print_insn_hppa): Likewise.
71 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
72 array.
73 * msp430-dis.c (msp430_singleoperand): Likewise.
74 (msp430_doubleoperand): Likewise.
75 (print_insn_msp430): Likewise.
76 * nds32-asm.c (parse_operand): Likewise.
77 * sh-opc.h (MASK): Likewise.
78 * v850-dis.c (get_operand_value): Likewise.
79
f04265ec
NC		 802015-09-22 Nick Clifton <nickc@redhat.com>
81
82 * rx-decode.opc (bwl): Use RX_Bad_Size.
83 (sbwl): Likewise.
84 (ubwl): Likewise. Rename to ubw.
85 (uBWL): Rename to uBW.
86 Replace all references to uBWL with uBW.
87 * rx-decode.c: Regenerate.
88 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
89 (opsize_names): Likewise.
90 (print_insn_rx): Detect and report RX_Bad_Size.
91
6dca4fd1
AB		 922015-09-22 Anton Blanchard <anton@samba.org>
93
94 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
95
38074311
JM		 962015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
97
98 * sparc-dis.c (print_insn_sparc): Handle the privileged register
99 %pmcdper.
100
5f40e14d
JS		 1012015-08-24 Jan Stancek <jstancek@redhat.com>
102
103 * i386-dis.c (print_insn): Fix decoding of three byte operands.
104
ab4e4ed5
AF		 1052015-08-21 Alexander Fomin <alexander.fomin@intel.com>
106
107 PR binutils/18257
108 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
109 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
110 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
111 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
112 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
113 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
114 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
115 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
116 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
117 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
118 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
119 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
120 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
121 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
122 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
123 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
124 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
125 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
126 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
127 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
128 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
129 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
130 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
131 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
132 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
133 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
134 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
135 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
136 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
137 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
138 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
139 (vex_w_table): Replace terminals with MOD_TABLE entries for
140 most of mask instructions.
141
919b75f7
AM		 1422015-08-17 Alan Modra <amodra@gmail.com>
143
144 * cgen.sh: Trim trailing space from cgen output.
145 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
146 (print_dis_table): Likewise.
147 * opc2c.c (dump_lines): Likewise.
148 (orig_filename): Warning fix.
149 * ia64-asmtab.c: Regenerate.
150
4ab90a7a
AV		 1512015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
152
153 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
154 and higher with ARM instruction set will now mark the 26-bit
155 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
156 (arm_opcodes): Fix for unpredictable nop being recognized as a
157 teq.
158
40fc1451
SD		 1592015-08-12 Simon Dardis <simon.dardis@imgtec.com>
160
161 * micromips-opc.c (micromips_opcodes): Re-order table so that move
162 based on 'or' is first.
163 * mips-opc.c (mips_builtin_opcodes): Ditto.
164
922c5db5
NC		 1652015-08-11 Nick Clifton <nickc@redhat.com>
166
167 PR 18800
168 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
169 instruction.
170
75fb7498
RS		 1712015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
172
173 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
174
36aed29d
AP		 1752015-08-07 Amit Pawar <Amit.Pawar@amd.com>
176
177 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
178 * i386-init.h: Regenerated.
179
a8484f96
L		 1802015-07-30 H.J. Lu <hongjiu.lu@intel.com>
181
182 PR binutils/13571
183 * i386-dis.c (MOD_0FC3): New.
184 (PREFIX_0FC3): Renamed to ...
185 (PREFIX_MOD_0_0FC3): This.
186 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
187 (prefix_table): Replace Ma with Ev on movntiS.
188 (mod_table): Add MOD_0FC3.
189
37a42ee9
L		 1902015-07-27 H.J. Lu <hongjiu.lu@intel.com>
191
192 * configure: Regenerated.
193
070fe95d
AM		 1942015-07-23 Alan Modra <amodra@gmail.com>
195
196 PR 18708
197 * i386-dis.c (get64): Avoid signed integer overflow.
198
20c2a615
L		 1992015-07-22 Alexander Fomin <alexander.fomin@intel.com>
200
201 PR binutils/18631
202 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
203 "EXEvexHalfBcstXmmq" for the second operand.
204 (EVEX_W_0F79_P_2): Likewise.
205 (EVEX_W_0F7A_P_2): Likewise.
206 (EVEX_W_0F7B_P_2): Likewise.
207
6f1c2142
AM		 2082015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
209
210 * arm-dis.c (print_insn_coprocessor): Added support for quarter
211 float bitfield format.
212 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
213 quarter float bitfield format.
214
8a643cc3
L		 2152015-07-14 H.J. Lu <hongjiu.lu@intel.com>
216
217 * configure: Regenerated.
218
ef5a96d5
AM		 2192015-07-03 Alan Modra <amodra@gmail.com>
220
221 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
222 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
223 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
224
c8c8175b
SL		 2252015-07-01 Sandra Loosemore <sandra@codesourcery.com>
226 Cesar Philippidis <cesar@codesourcery.com>
227
228 * nios2-dis.c (nios2_extract_opcode): New.
229 (nios2_disassembler_state): New.
230 (nios2_find_opcode_hash): Use mach parameter to select correct
231 disassembler state.
232 (nios2_print_insn_arg): Extend to support new R2 argument letters
233 and formats.
234 (print_insn_nios2): Check for 16-bit instruction at end of memory.
235 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
236 (NIOS2_NUM_OPCODES): Rename to...
237 (NIOS2_NUM_R1_OPCODES): This.
238 (nios2_r2_opcodes): New.
239 (NIOS2_NUM_R2_OPCODES): New.
240 (nios2_num_r2_opcodes): New.
241 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
242 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
243 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
244 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
245 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
246
9916071f
AP		 2472015-06-30 Amit Pawar <Amit.Pawar@amd.com>
248
249 * i386-dis.c (OP_Mwaitx): New.
250 (rm_table): Add monitorx/mwaitx.
251 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
252 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
253 (operand_type_init): Add CpuMWAITX.
254 * i386-opc.h (CpuMWAITX): New.
255 (i386_cpu_flags): Add cpumwaitx.
256 * i386-opc.tbl: Add monitorx and mwaitx.
257 * i386-init.h: Regenerated.
258 * i386-tbl.h: Likewise.
259
7b934113
PB		 2602015-06-22 Peter Bergner <bergner@vnet.ibm.com>
261
262 * ppc-opc.c (insert_ls): Test for invalid LS operands.
263 (insert_esync): New function.
264 (LS, WC): Use insert_ls.
265 (ESYNC): Use insert_esync.
266
bdc4de1b
NC		 2672015-06-22 Nick Clifton <nickc@redhat.com>
268
269 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
270 requested region lies beyond it.
271 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
272 looking for 32-bit insns.
273 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
274 data.
275 * sh-dis.c (print_insn_sh): Likewise.
276 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
277 blocks of instructions.
278 * vax-dis.c (print_insn_vax): Check that the requested address
279 does not clash with the stop_vma.
280
11a0cf2e
PB		 2812015-06-19 Peter Bergner <bergner@vnet.ibm.com>
282
070fe95d 283 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 284 * ppc-opc.c (FXM4): Add non-zero optional value.
285 (TBR): Likewise.
286 (SXL): Likewise.
287 (insert_fxm): Handle new default operand value.
288 (extract_fxm): Likewise.
289 (insert_tbr): Likewise.
290 (extract_tbr): Likewise.
291
bdfa8b95
MW		 2922015-06-16 Matthew Wahab <matthew.wahab@arm.com>
293
294 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
295
24b4cf66
SN		 2962015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
297
298 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
299
99a2c561
PB		 3002015-06-12 Peter Bergner <bergner@vnet.ibm.com>
301
302 * ppc-opc.c: Add comment accidentally removed by old commit.
303 (MTMSRD_L): Delete.
304
40f77f82
AM		 3052015-06-04 Peter Bergner <bergner@vnet.ibm.com>
306
307 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
308
13be46a2
NC		 3092015-06-04 Nick Clifton <nickc@redhat.com>
310
311 PR 18474
312 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
313
ddfded2f
MW		 3142015-06-02 Matthew Wahab <matthew.wahab@arm.com>
315
316 * arm-dis.c (arm_opcodes): Add "setpan".
317 (thumb_opcodes): Add "setpan".
318
1af1dd51
MW		 3192015-06-02 Matthew Wahab <matthew.wahab@arm.com>
320
321 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
322 macros.
323
9e1f0fa7
MW		 3242015-06-02 Matthew Wahab <matthew.wahab@arm.com>
325
326 * aarch64-tbl.h (aarch64_feature_rdma): New.
327 (RDMA): New.
328 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
329 * aarch64-asm-2.c: Regenerate.
330 * aarch64-dis-2.c: Regenerate.
331 * aarch64-opc-2.c: Regenerate.
332
290806fd
MW		 3332015-06-02 Matthew Wahab <matthew.wahab@arm.com>
334
335 * aarch64-tbl.h (aarch64_feature_lor): New.
336 (LOR): New.
337 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
338 "stllrb", "stllrh".
339 * aarch64-asm-2.c: Regenerate.
340 * aarch64-dis-2.c: Regenerate.
341 * aarch64-opc-2.c: Regenerate.
342
f21cce2c
MW		 3432015-06-01 Matthew Wahab <matthew.wahab@arm.com>
344
345 * aarch64-opc.c (F_ARCHEXT): New.
346 (aarch64_sys_regs): Add "pan".
347 (aarch64_sys_reg_supported_p): New.
348 (aarch64_pstatefields): Add "pan".
349 (aarch64_pstatefield_supported_p): New.
350
d194d186
JB		 3512015-06-01 Jan Beulich <jbeulich@suse.com>
352
353 * i386-tbl.h: Regenerate.
354
3a8547d2
JB		 3552015-06-01 Jan Beulich <jbeulich@suse.com>
356
357 * i386-dis.c (print_insn): Swap rounding mode specifier and
358 general purpose register in Intel mode.
359
015c54d5
JB		 3602015-06-01 Jan Beulich <jbeulich@suse.com>
361
362 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
363 * i386-tbl.h: Regenerate.
364
071f0063
L		 3652015-05-18 H.J. Lu <hongjiu.lu@intel.com>
366
367 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
368 * i386-init.h: Regenerated.
369
5db04b09
L		 3702015-05-15 H.J. Lu <hongjiu.lu@intel.com>
371
372 PR binutis/18386
373 * i386-dis.c: Add comments for '@'.
374 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
375 (enum x86_64_isa): New.
376 (isa64): Likewise.
377 (print_i386_disassembler_options): Add amd64 and intel64.
378 (print_insn): Handle amd64 and intel64.
379 (putop): Handle '@'.
380 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
381 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
382 * i386-opc.h (AMD64): New.
383 (CpuIntel64): Likewise.
384 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
385 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
386 Mark direct call/jmp without Disp16|Disp32 as Intel64.
387 * i386-init.h: Regenerated.
388 * i386-tbl.h: Likewise.
389
4bc0608a
PB		 3902015-05-14 Peter Bergner <bergner@vnet.ibm.com>
391
392 * ppc-opc.c (IH) New define.
393 (powerpc_opcodes) <wait>: Do not enable for POWER7.
394 <tlbie>: Add RS operand for POWER7.
395 <slbia>: Add IH operand for POWER6.
396
70cead07
L		 3972015-05-11 H.J. Lu <hongjiu.lu@intel.com>
398
399 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
400 direct branch.
401 (jmp): Likewise.
402 * i386-tbl.h: Regenerated.
403
7b6d09fb
L		 4042015-05-11 H.J. Lu <hongjiu.lu@intel.com>
405
406 * configure.ac: Support bfd_iamcu_arch.
407 * disassemble.c (disassembler): Support bfd_iamcu_arch.
408 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
409 CPU_IAMCU_COMPAT_FLAGS.
410 (cpu_flags): Add CpuIAMCU.
411 * i386-opc.h (CpuIAMCU): New.
412 (i386_cpu_flags): Add cpuiamcu.
413 * configure: Regenerated.
414 * i386-init.h: Likewise.
415 * i386-tbl.h: Likewise.
416
31955f99
L		 4172015-05-08 H.J. Lu <hongjiu.lu@intel.com>
418
419 PR binutis/18386
420 * i386-dis.c (X86_64_E8): New.
421 (X86_64_E9): Likewise.
422 Update comments on 'T', 'U', 'V'. Add comments for '^'.
423 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
424 (x86_64_table): Add X86_64_E8 and X86_64_E9.
425 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
426 (putop): Handle '^'.
427 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
428 REX_W.
429
0952813b
DD		 4302015-04-30 DJ Delorie <dj@redhat.com>
431
432 * disassemble.c (disassembler): Choose suitable disassembler based
433 on E_ABI.
434 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
435 it to decode mul/div insns.
436 * rl78-decode.c: Regenerate.
437 * rl78-dis.c (print_insn_rl78): Rename to...
438 (print_insn_rl78_common): ...this, take ISA parameter.
439 (print_insn_rl78): New.
440 (print_insn_rl78_g10): New.
441 (print_insn_rl78_g13): New.
442 (print_insn_rl78_g14): New.
443 (rl78_get_disassembler): New.
444
f9d3ecaa
NC		 4452015-04-29 Nick Clifton <nickc@redhat.com>
446
447 * po/fr.po: Updated French translation.
448
4fff86c5
PB		 4492015-04-27 Peter Bergner <bergner@vnet.ibm.com>
450
451 * ppc-opc.c (DCBT_EO): New define.
452 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
453 <lharx>: Likewise.
454 <stbcx.>: Likewise.
455 <sthcx.>: Likewise.
456 <waitrsv>: Do not enable for POWER7 and later.
457 <waitimpl>: Likewise.
458 <dcbt>: Default to the two operand form of the instruction for all
459 "old" cpus. For "new" cpus, use the operand ordering that matches
460 whether the cpu is server or embedded.
461 <dcbtst>: Likewise.
462
3b78cfe1
AK		 4632015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
464
465 * s390-opc.c: New instruction type VV0UU2.
466 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
467 and WFC.
468
04d824a4
JB		 4692015-04-23 Jan Beulich <jbeulich@suse.com>
470
471 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
472 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
473 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
474 (vfpclasspd, vfpclassps): Add %XZ.
475
09708981
L		 4762015-04-15 H.J. Lu <hongjiu.lu@intel.com>
477
478 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
479 (PREFIX_UD_REPZ): Likewise.
480 (PREFIX_UD_REPNZ): Likewise.
481 (PREFIX_UD_DATA): Likewise.
482 (PREFIX_UD_ADDR): Likewise.
483 (PREFIX_UD_LOCK): Likewise.
484
3888916d
L		 4852015-04-15 H.J. Lu <hongjiu.lu@intel.com>
486
487 * i386-dis.c (prefix_requirement): Removed.
488 (print_insn): Don't set prefix_requirement. Check
489 dp->prefix_requirement instead of prefix_requirement.
490
f24bcbaa
L		 4912015-04-15 H.J. Lu <hongjiu.lu@intel.com>
492
493 PR binutils/17898
494 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
495 (PREFIX_MOD_0_0FC7_REG_6): This.
496 (PREFIX_MOD_3_0FC7_REG_6): New.
497 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
498 (prefix_table): Replace PREFIX_0FC7_REG_6 with
499 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
500 PREFIX_MOD_3_0FC7_REG_7.
501 (mod_table): Replace PREFIX_0FC7_REG_6 with
502 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
503 PREFIX_MOD_3_0FC7_REG_7.
504
507bd325
L		 5052015-04-15 H.J. Lu <hongjiu.lu@intel.com>
506
507 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
508 (PREFIX_MANDATORY_REPNZ): Likewise.
509 (PREFIX_MANDATORY_DATA): Likewise.
510 (PREFIX_MANDATORY_ADDR): Likewise.
511 (PREFIX_MANDATORY_LOCK): Likewise.
512 (PREFIX_MANDATORY): Likewise.
513 (PREFIX_UD_SHIFT): Set to 8
514 (PREFIX_UD_REPZ): Updated.
515 (PREFIX_UD_REPNZ): Likewise.
516 (PREFIX_UD_DATA): Likewise.
517 (PREFIX_UD_ADDR): Likewise.
518 (PREFIX_UD_LOCK): Likewise.
519 (PREFIX_IGNORED_SHIFT): New.
520 (PREFIX_IGNORED_REPZ): Likewise.
521 (PREFIX_IGNORED_REPNZ): Likewise.
522 (PREFIX_IGNORED_DATA): Likewise.
523 (PREFIX_IGNORED_ADDR): Likewise.
524 (PREFIX_IGNORED_LOCK): Likewise.
525 (PREFIX_OPCODE): Likewise.
526 (PREFIX_IGNORED): Likewise.
527 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
528 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
529 (three_byte_table): Likewise.
530 (mod_table): Likewise.
531 (mandatory_prefix): Renamed to ...
532 (prefix_requirement): This.
533 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
534 Update PREFIX_90 entry.
535 (get_valid_dis386): Check prefix_requirement to see if a prefix
536 should be ignored.
537 (print_insn): Replace mandatory_prefix with prefix_requirement.
538
f0fba320
RL		 5392015-04-15 Renlin Li <renlin.li@arm.com>
540
541 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
542 use it for ssat and ssat16.
543 (print_insn_thumb32): Add handle case for 'D' control code.
544
bf890a93
IT		 5452015-04-06 Ilya Tocar <ilya.tocar@intel.com>
546 H.J. Lu <hongjiu.lu@intel.com>
547
548 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
549 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
550 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
551 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
552 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
553 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
554 Fill prefix_requirement field.
555 (struct dis386): Add prefix_requirement field.
556 (dis386): Fill prefix_requirement field.
557 (dis386_twobyte): Ditto.
558 (twobyte_has_mandatory_prefix_: Remove.
559 (reg_table): Fill prefix_requirement field.
560 (prefix_table): Ditto.
561 (x86_64_table): Ditto.
562 (three_byte_table): Ditto.
563 (xop_table): Ditto.
564 (vex_table): Ditto.
565 (vex_len_table): Ditto.
566 (vex_w_table): Ditto.
567 (mod_table): Ditto.
568 (bad_opcode): Ditto.
569 (print_insn): Use prefix_requirement.
570 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
571 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
572 (float_reg): Ditto.
573
2f783c1f
MF		 5742015-03-30 Mike Frysinger <vapier@gentoo.org>
575
576 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
577
b9d94d62
L		 5782015-03-29 H.J. Lu <hongjiu.lu@intel.com>
579
580 * Makefile.in: Regenerated.
581
27c49e9a
AB		 5822015-03-25 Anton Blanchard <anton@samba.org>
583
584 * ppc-dis.c (disassemble_init_powerpc): Only initialise
585 powerpc_opcd_indices and vle_opcd_indices once.
586
c4e676f1
AB		 5872015-03-25 Anton Blanchard <anton@samba.org>
588
589 * ppc-opc.c (powerpc_opcodes): Add slbfee.
590
823d2571
TG		 5912015-03-24 Terry Guo <terry.guo@arm.com>
592
593 * arm-dis.c (opcode32): Updated to use new arm feature struct.
594 (opcode16): Likewise.
595 (coprocessor_opcodes): Replace bit with feature struct.
596 (neon_opcodes): Likewise.
597 (arm_opcodes): Likewise.
598 (thumb_opcodes): Likewise.
599 (thumb32_opcodes): Likewise.
600 (print_insn_coprocessor): Likewise.
601 (print_insn_arm): Likewise.
602 (select_arm_features): Follow new feature struct.
603
029f3522
GG		 6042015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
605
606 * i386-dis.c (rm_table): Add clzero.
607 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
608 Add CPU_CLZERO_FLAGS.
609 (cpu_flags): Add CpuCLZERO.
610 * i386-opc.h: Add CpuCLZERO.
611 * i386-opc.tbl: Add clzero.
612 * i386-init.h: Re-generated.
613 * i386-tbl.h: Re-generated.
614
6914869a
AB		 6152015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
616
617 * mips-opc.c (decode_mips_operand): Fix constraint issues
618 with u and y operands.
619
21e20815
AB		 6202015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
621
622 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
623
6b1d7593
AK		 6242015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
625
626 * s390-opc.c: Add new IBM z13 instructions.
627 * s390-opc.txt: Likewise.
628
c8f89a34
JW		 6292015-03-10 Renlin Li <renlin.li@arm.com>
630
631 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
632 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
633 related alias.
634 * aarch64-asm-2.c: Regenerate.
635 * aarch64-dis-2.c: Likewise.
636 * aarch64-opc-2.c: Likewise.
637
d8282f0e
JW		 6382015-03-03 Jiong Wang <jiong.wang@arm.com>
639
640 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
641
ac994365
OE		 6422015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
643
644 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
645 arch_sh_up.
646 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
647 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
648
fd63f640
V		 6492015-02-23 Vinay <Vinay.G@kpit.com>
650
651 * rl78-decode.opc (MOV): Added space between two operands for
652 'mov' instruction in index addressing mode.
653 * rl78-decode.c: Regenerate.
654
f63c1776
PA		 6552015-02-19 Pedro Alves <palves@redhat.com>
656
657 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
658
07774fcc
PA		 6592015-02-10 Pedro Alves <palves@redhat.com>
660 Tom Tromey <tromey@redhat.com>
661
662 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
663 microblaze_and, microblaze_xor.
664 * microblaze-opc.h (opcodes): Adjust.
665
3f8107ab
AM		 6662015-01-28 James Bowman <james.bowman@ftdichip.com>
667
668 * Makefile.am: Add FT32 files.
669 * configure.ac: Handle FT32.
670 * disassemble.c (disassembler): Call print_insn_ft32.
671 * ft32-dis.c: New file.
672 * ft32-opc.c: New file.
673 * Makefile.in: Regenerate.
674 * configure: Regenerate.
675 * po/POTFILES.in: Regenerate.
676
e5fe4957
KLC		 6772015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
678
679 * nds32-asm.c (keyword_sr): Add new system registers.
680
1e2e8c52
AK		 6812015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
682
683 * s390-dis.c (s390_extract_operand): Support vector register
684 operands.
685 (s390_print_insn_with_opcode): Support new operands types and add
686 new handling of optional operands.
687 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
688 and include opcode/s390.h instead.
689 (struct op_struct): New field `flags'.
690 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
691 (dumpTable): Dump flags.
692 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
693 string.
694 * s390-opc.c: Add new operands types, instruction formats, and
695 instruction masks.
696 (s390_opformats): Add new formats for .insn.
697 * s390-opc.txt: Add new instructions.
698
b90efa5b 6992015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 700
b90efa5b 701 Update year range in copyright notice of all files.
bffb6004 702
b90efa5b 703For older changes see ChangeLog-2014
252b5132 704\f
b90efa5b 705Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 706
707Copying and distribution of this file, with or without modification,
708are permitted in any medium without royalty provided the copyright
709notice and this notice are preserved.
710
252b5132 711Local Variables:
2f6d2f85
NC		 712mode: change-log
713left-margin: 8
714fill-column: 74
252b5132
RH		 715version-control: never
716End:
GDB Binutils - Deliverables
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