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opcodes/arc: Fix extract for some add_s instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
02f3be19
AB		 12016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
2
3 * arc-opc.c (extract_rhv1): Extract value from insn.
4
6f9f37ed 52016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 6
7 * arc-nps400-tbl.h: Add ldbit instruction.
8 * arc-opc.c: Add flag classes required for ldbit.
9
6f9f37ed 102016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 11
12 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
13 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
14 support the above instructions.
15
6f9f37ed 162016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 17
18 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
19 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
20 csma, cbba, zncv, and hofs.
21 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
22 support the above instructions.
23
242016-06-06 Graham Markall <graham.markall@embecosm.com>
25
26 * arc-nps400-tbl.h: Add andab and orab instructions.
27
282016-06-06 Graham Markall <graham.markall@embecosm.com>
29
30 * arc-nps400-tbl.h: Add addl-like instructions.
31
322016-06-06 Graham Markall <graham.markall@embecosm.com>
33
34 * arc-nps400-tbl.h: Add mxb and imxb instructions.
35
362016-06-06 Graham Markall <graham.markall@embecosm.com>
37
38 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
39 instructions.
40
b2cc3f6f
AK		 412016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
42
43 * s390-dis.c (option_use_insn_len_bits_p): New file scope
44 variable.
45 (init_disasm): Handle new command line option "insnlength".
46 (print_s390_disassembler_options): Mention new option in help
47 output.
48 (print_insn_s390): Use the encoded insn length when dumping
49 unknown instructions.
50
1857fe72
DC		 512016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
52
53 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
54 to the address and set as symbol address for LDS/ STS immediate operands.
55
14b57c7c
AM		 562016-06-07 Alan Modra <amodra@gmail.com>
57
58 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
59 cpu for "vle" to e500.
60 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
61 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
62 (PPCNONE): Delete, substitute throughout.
63 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
64 except for major opcode 4 and 31.
65 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
66
4d1464f2
MW		 672016-06-07 Matthew Wahab <matthew.wahab@arm.com>
68
69 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
70 ARM_EXT_RAS in relevant entries.
71
026122a6
PB		 722016-06-03 Peter Bergner <bergner@vnet.ibm.com>
73
74 PR binutils/20196
75 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
76 opcodes for E6500.
77
07f5af7d
L		 782016-06-03 H.J. Lu <hongjiu.lu@intel.com>
79
80 PR binutis/18386
81 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
82 (indir_v_mode): New.
83 Add comments for '&'.
84 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
85 (putop): Handle '&'.
86 (intel_operand_size): Handle indir_v_mode.
87 (OP_E_register): Likewise.
88 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
89 64-bit indirect call/jmp for AMD64.
90 * i386-tbl.h: Regenerated
91
4eb6f892
AB		 922016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
93
94 * arc-dis.c (struct arc_operand_iterator): New structure.
95 (find_format_from_table): All the old content from find_format,
96 with some minor adjustments, and parameter renaming.
97 (find_format_long_instructions): New function.
98 (find_format): Rewritten.
99 (arc_insn_length): Add LSB parameter.
100 (extract_operand_value): New function.
101 (operand_iterator_next): New function.
102 (print_insn_arc): Use new functions to find opcode, and iterator
103 over operands.
104 * arc-opc.c (insert_nps_3bit_dst_short): New function.
105 (extract_nps_3bit_dst_short): New function.
106 (insert_nps_3bit_src2_short): New function.
107 (extract_nps_3bit_src2_short): New function.
108 (insert_nps_bitop1_size): New function.
109 (extract_nps_bitop1_size): New function.
110 (insert_nps_bitop2_size): New function.
111 (extract_nps_bitop2_size): New function.
112 (insert_nps_bitop_mod4_msb): New function.
113 (extract_nps_bitop_mod4_msb): New function.
114 (insert_nps_bitop_mod4_lsb): New function.
115 (extract_nps_bitop_mod4_lsb): New function.
116 (insert_nps_bitop_dst_pos3_pos4): New function.
117 (extract_nps_bitop_dst_pos3_pos4): New function.
118 (insert_nps_bitop_ins_ext): New function.
119 (extract_nps_bitop_ins_ext): New function.
120 (arc_operands): Add new operands.
121 (arc_long_opcodes): New global array.
122 (arc_num_long_opcodes): New global.
123 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
124
1fe0971e
TS		 1252016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
126
127 * nds32-asm.h: Add extern "C".
128 * sh-opc.h: Likewise.
129
315f180f
GM		 1302016-06-01 Graham Markall <graham.markall@embecosm.com>
131
132 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
133 0,b,limm to the rflt instruction.
134
a2b5fccc
TS		 1352016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
136
137 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
138 constant.
139
0cbd0046
L		 1402016-05-29 H.J. Lu <hongjiu.lu@intel.com>
141
142 PR gas/20145
143 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
144 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
145 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
146 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
147 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
148 * i386-init.h: Regenerated.
149
1848e567
L		 1502016-05-27 H.J. Lu <hongjiu.lu@intel.com>
151
152 PR gas/20145
153 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
154 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
155 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
156 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
157 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
158 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
159 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
160 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
161 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
162 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
163 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
164 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
165 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
166 CpuRegMask for AVX512.
167 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
168 and CpuRegMask.
169 (set_bitfield_from_cpu_flag_init): New function.
170 (set_bitfield): Remove const on f. Call
171 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
172 * i386-opc.h (CpuRegMMX): New.
173 (CpuRegXMM): Likewise.
174 (CpuRegYMM): Likewise.
175 (CpuRegZMM): Likewise.
176 (CpuRegMask): Likewise.
177 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
178 and cpuregmask.
179 * i386-init.h: Regenerated.
180 * i386-tbl.h: Likewise.
181
e92bae62
L		 1822016-05-27 H.J. Lu <hongjiu.lu@intel.com>
183
184 PR gas/20154
185 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
186 (opcode_modifiers): Add AMD64 and Intel64.
187 (main): Properly verify CpuMax.
188 * i386-opc.h (CpuAMD64): Removed.
189 (CpuIntel64): Likewise.
190 (CpuMax): Set to CpuNo64.
191 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
192 (AMD64): New.
193 (Intel64): Likewise.
194 (i386_opcode_modifier): Add amd64 and intel64.
195 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
196 on call and jmp.
197 * i386-init.h: Regenerated.
198 * i386-tbl.h: Likewise.
199
e89c5eaa
L		 2002016-05-27 H.J. Lu <hongjiu.lu@intel.com>
201
202 PR gas/20154
203 * i386-gen.c (main): Fail if CpuMax is incorrect.
204 * i386-opc.h (CpuMax): Set to CpuIntel64.
205 * i386-tbl.h: Regenerated.
206
77d66e7b
NC		 2072016-05-27 Nick Clifton <nickc@redhat.com>
208
209 PR target/20150
210 * msp430-dis.c (msp430dis_read_two_bytes): New function.
211 (msp430dis_opcode_unsigned): New function.
212 (msp430dis_opcode_signed): New function.
213 (msp430_singleoperand): Use the new opcode reading functions.
214 Only disassenmble bytes if they were successfully read.
215 (msp430_doubleoperand): Likewise.
216 (msp430_branchinstr): Likewise.
217 (msp430x_callx_instr): Likewise.
218 (print_insn_msp430): Check that it is safe to read bytes before
219 attempting disassembly. Use the new opcode reading functions.
220
19dfcc89
PB		 2212016-05-26 Peter Bergner <bergner@vnet.ibm.com>
222
223 * ppc-opc.c (CY): New define. Document it.
224 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
225
f3ad7637
L		 2262016-05-25 H.J. Lu <hongjiu.lu@intel.com>
227
228 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
229 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
230 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
231 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
232 CPU_ANY_AVX_FLAGS.
233 * i386-init.h: Regenerated.
234
f1360d58
L		 2352016-05-25 H.J. Lu <hongjiu.lu@intel.com>
236
237 PR gas/20141
238 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
239 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
240 * i386-init.h: Regenerated.
241
293f5f65
L		 2422016-05-25 H.J. Lu <hongjiu.lu@intel.com>
243
244 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
245 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
246 * i386-init.h: Regenerated.
247
d9eca1df
CZ		 2482016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
249
250 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
251 information.
252 (print_insn_arc): Set insn_type information.
253 * arc-opc.c (C_CC): Add F_CLASS_COND.
254 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
255 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
256 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
257 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
258 (brne, brne_s, jeq_s, jne_s): Likewise.
259
87789e08
CZ		 2602016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
261
262 * arc-tbl.h (neg): New instruction variant.
263
c810e0b8
CZ		 2642016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
265
266 * arc-dis.c (find_format, find_format, get_auxreg)
267 (print_insn_arc): Changed.
268 * arc-ext.h (INSERT_XOP): Likewise.
269
3d207518
TS		 2702016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
271
272 * tic54x-dis.c (sprint_mmr): Adjust.
273 * tic54x-opc.c: Likewise.
274
514e58b7
AM		 2752016-05-19 Alan Modra <amodra@gmail.com>
276
277 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
278
e43de63c
AM		 2792016-05-19 Alan Modra <amodra@gmail.com>
280
281 * ppc-opc.c: Formatting.
282 (NSISIGNOPT): Define.
283 (powerpc_opcodes <subis>): Use NSISIGNOPT.
284
1401d2fe
MR		 2852016-05-18 Maciej W. Rozycki <macro@imgtec.com>
286
287 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
288 replacing references to `micromips_ase' throughout.
289 (_print_insn_mips): Don't use file-level microMIPS annotation to
290 determine the disassembly mode with the symbol table.
291
1178da44
PB		 2922016-05-13 Peter Bergner <bergner@vnet.ibm.com>
293
294 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
295
8f4f9071
MF		 2962016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
297
298 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
299 mips64r6.
300 * mips-opc.c (D34): New macro.
301 (mips_builtin_opcodes): Define bposge32c for DSPr3.
302
8bc52696
AF		 3032016-05-10 Alexander Fomin <alexander.fomin@intel.com>
304
305 * i386-dis.c (prefix_table): Add RDPID instruction.
306 * i386-gen.c (cpu_flag_init): Add RDPID flag.
307 (cpu_flags): Add RDPID bitfield.
308 * i386-opc.h (enum): Add RDPID element.
309 (i386_cpu_flags): Add RDPID field.
310 * i386-opc.tbl: Add RDPID instruction.
311 * i386-init.h: Regenerate.
312 * i386-tbl.h: Regenerate.
313
39d911fc
TP		 3142016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
315
316 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
317 branch type of a symbol.
318 (print_insn): Likewise.
319
16a1fa25
TP		 3202016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
321
322 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
323 Mainline Security Extensions instructions.
324 (thumb_opcodes): Add entries for narrow ARMv8-M Security
325 Extensions instructions.
326 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
327 instructions.
328 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
329 special registers.
330
d751b79e
JM		 3312016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
332
333 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
334
945e0f82
CZ		 3352016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
336
337 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
338 (arcExtMap_genOpcode): Likewise.
339 * arc-opc.c (arg_32bit_rc): Define new variable.
340 (arg_32bit_u6): Likewise.
341 (arg_32bit_limm): Likewise.
342
20f55f38
SN		 3432016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
344
345 * aarch64-gen.c (VERIFIER): Define.
346 * aarch64-opc.c (VERIFIER): Define.
347 (verify_ldpsw): Use static linkage.
348 * aarch64-opc.h (verify_ldpsw): Remove.
349 * aarch64-tbl.h: Use VERIFIER for verifiers.
350
4bd13cde
NC		 3512016-04-28 Nick Clifton <nickc@redhat.com>
352
353 PR target/19722
354 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
355 * aarch64-opc.c (verify_ldpsw): New function.
356 * aarch64-opc.h (verify_ldpsw): New prototype.
357 * aarch64-tbl.h: Add initialiser for verifier field.
358 (LDPSW): Set verifier to verify_ldpsw.
359
c0f92bf9
L		 3602016-04-23 H.J. Lu <hongjiu.lu@intel.com>
361
362 PR binutils/19983
363 PR binutils/19984
364 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
365 smaller than address size.
366
e6c7cdec
TS		 3672016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
368
369 * alpha-dis.c: Regenerate.
370 * crx-dis.c: Likewise.
371 * disassemble.c: Likewise.
372 * epiphany-opc.c: Likewise.
373 * fr30-opc.c: Likewise.
374 * frv-opc.c: Likewise.
375 * ip2k-opc.c: Likewise.
376 * iq2000-opc.c: Likewise.
377 * lm32-opc.c: Likewise.
378 * lm32-opinst.c: Likewise.
379 * m32c-opc.c: Likewise.
380 * m32r-opc.c: Likewise.
381 * m32r-opinst.c: Likewise.
382 * mep-opc.c: Likewise.
383 * mt-opc.c: Likewise.
384 * or1k-opc.c: Likewise.
385 * or1k-opinst.c: Likewise.
386 * tic80-opc.c: Likewise.
387 * xc16x-opc.c: Likewise.
388 * xstormy16-opc.c: Likewise.
389
537aefaf
AB		 3902016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
391
392 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
393 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
394 calcsd, and calcxd instructions.
395 * arc-opc.c (insert_nps_bitop_size): Delete.
396 (extract_nps_bitop_size): Delete.
397 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
398 (extract_nps_qcmp_m3): Define.
399 (extract_nps_qcmp_m2): Define.
400 (extract_nps_qcmp_m1): Define.
401 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
402 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
403 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
404 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
405 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
406 NPS_QCMP_M3.
407
c8f785f2
AB		 4082016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
409
410 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
411
6fd8e7c2
L		 4122016-04-15 H.J. Lu <hongjiu.lu@intel.com>
413
414 * Makefile.in: Regenerated with automake 1.11.6.
415 * aclocal.m4: Likewise.
416
4b0c052e
AB		 4172016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
418
419 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
420 instructions.
421 * arc-opc.c (insert_nps_cmem_uimm16): New function.
422 (extract_nps_cmem_uimm16): New function.
423 (arc_operands): Add NPS_XLDST_UIMM16 operand.
424
cb040366
AB		 4252016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
426
427 * arc-dis.c (arc_insn_length): New function.
428 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
429 (find_format): Change insnLen parameter to unsigned.
430
accc0180
NC		 4312016-04-13 Nick Clifton <nickc@redhat.com>
432
433 PR target/19937
434 * v850-opc.c (v850_opcodes): Correct masks for long versions of
435 the LD.B and LD.BU instructions.
436
f36e33da
CZ		 4372016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
438
439 * arc-dis.c (find_format): Check for extension flags.
440 (print_flags): New function.
441 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
442 .extAuxRegister.
443 * arc-ext.c (arcExtMap_coreRegName): Use
444 LAST_EXTENSION_CORE_REGISTER.
445 (arcExtMap_coreReadWrite): Likewise.
446 (dump_ARC_extmap): Update printing.
447 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
448 (arc_aux_regs): Add cpu field.
449 * arc-regs.h: Add cpu field, lower case name aux registers.
450
1c2e355e
CZ		 4512016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
452
453 * arc-tbl.h: Add rtsc, sleep with no arguments.
454
b99747ae
CZ		 4552016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
456
457 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
458 Initialize.
459 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
460 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
461 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
462 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
463 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
464 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
465 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
466 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
467 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
468 (arc_opcode arc_opcodes): Null terminate the array.
469 (arc_num_opcodes): Remove.
470 * arc-ext.h (INSERT_XOP): Define.
471 (extInstruction_t): Likewise.
472 (arcExtMap_instName): Delete.
473 (arcExtMap_insn): New function.
474 (arcExtMap_genOpcode): Likewise.
475 * arc-ext.c (ExtInstruction): Remove.
476 (create_map): Zero initialize instruction fields.
477 (arcExtMap_instName): Remove.
478 (arcExtMap_insn): New function.
479 (dump_ARC_extmap): More info while debuging.
480 (arcExtMap_genOpcode): New function.
481 * arc-dis.c (find_format): New function.
482 (print_insn_arc): Use find_format.
483 (arc_get_disassembler): Enable dump_ARC_extmap only when
484 debugging.
485
92708cec
MR		 4862016-04-11 Maciej W. Rozycki <macro@imgtec.com>
487
488 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
489 instruction bits out.
490
a42a4f84
AB		 4912016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
492
493 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
494 * arc-opc.c (arc_flag_operands): Add new flags.
495 (arc_flag_classes): Add new classes.
496
1328504b
AB		 4972016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
498
499 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
500
820f03ff
AB		 5012016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
502
503 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
504 encode1, rflt, crc16, and crc32 instructions.
505 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
506 (arc_flag_classes): Add C_NPS_R.
507 (insert_nps_bitop_size_2b): New function.
508 (extract_nps_bitop_size_2b): Likewise.
509 (insert_nps_bitop_uimm8): Likewise.
510 (extract_nps_bitop_uimm8): Likewise.
511 (arc_operands): Add new operand entries.
512
8ddf6b2a
CZ		 5132016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
514
b99747ae
CZ		 515 * arc-regs.h: Add a new subclass field. Add double assist
516 accumulator register values.
517 * arc-tbl.h: Use DPA subclass to mark the double assist
518 instructions. Use DPX/SPX subclas to mark the FPX instructions.
519 * arc-opc.c (RSP): Define instead of SP.
520 (arc_aux_regs): Add the subclass field.
8ddf6b2a 521
589a7d88
JW		 5222016-04-05 Jiong Wang <jiong.wang@arm.com>
523
524 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
525
0a191de9 5262016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 527
528 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
529 NPS_R_SRC1.
530
0a106562
AB		 5312016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
532
533 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
534 issues. No functional changes.
535
bd05ac5f
CZ		 5362016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
537
b99747ae
CZ		 538 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
539 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
540 (RTT): Remove duplicate.
541 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
542 (PCT_CONFIG*): Remove.
543 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 544
9885948f
CZ		 5452016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
546
b99747ae 547 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 548
f2dd8838
CZ		 5492016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
550
b99747ae
CZ		 551 * arc-tbl.h (invld07): Remove.
552 * arc-ext-tbl.h: New file.
553 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
554 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 555
0d2f91fe
JK		 5562016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
557
558 Fix -Wstack-usage warnings.
559 * aarch64-dis.c (print_operands): Substitute size.
560 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
561
a6b71f42
JM		 5622016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
563
564 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
565 to get a proper diagnostic when an invalid ASR register is used.
566
9780e045
NC		 5672016-03-22 Nick Clifton <nickc@redhat.com>
568
569 * configure: Regenerate.
570
e23e8ebe
AB		 5712016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
572
573 * arc-nps400-tbl.h: New file.
574 * arc-opc.c: Add top level comment.
575 (insert_nps_3bit_dst): New function.
576 (extract_nps_3bit_dst): New function.
577 (insert_nps_3bit_src2): New function.
578 (extract_nps_3bit_src2): New function.
579 (insert_nps_bitop_size): New function.
580 (extract_nps_bitop_size): New function.
581 (arc_flag_operands): Add nps400 entries.
582 (arc_flag_classes): Add nps400 entries.
583 (arc_operands): Add nps400 entries.
584 (arc_opcodes): Add nps400 include.
585
1ae8ab47
AB		 5862016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
587
588 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
589 the new class enum values.
590
8699fc3e
AB		 5912016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
592
593 * arc-dis.c (print_insn_arc): Handle nps400.
594
24740d83
AB		 5952016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
596
597 * arc-opc.c (BASE): Delete.
598
8678914f
NC		 5992016-03-18 Nick Clifton <nickc@redhat.com>
600
601 PR target/19721
602 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
603 of MOV insn that aliases an ORR insn.
604
cc933301
JW		 6052016-03-16 Jiong Wang <jiong.wang@arm.com>
606
607 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
608
f86f5863
TS		 6092016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
610
611 * mcore-opc.h: Add const qualifiers.
612 * microblaze-opc.h (struct op_code_struct): Likewise.
613 * sh-opc.h: Likewise.
614 * tic4x-dis.c (tic4x_print_indirect): Likewise.
615 (tic4x_print_op): Likewise.
616
62de1c63
AM		 6172016-03-02 Alan Modra <amodra@gmail.com>
618
d11698cd 619 * or1k-desc.h: Regenerate.
62de1c63 620 * fr30-ibld.c: Regenerate.
c697cf0b 621 * rl78-decode.c: Regenerate.
62de1c63 622
020efce5
NC		 6232016-03-01 Nick Clifton <nickc@redhat.com>
624
625 PR target/19747
626 * rl78-dis.c (print_insn_rl78_common): Fix typo.
627
b0c11777
RL		 6282016-02-24 Renlin Li <renlin.li@arm.com>
629
630 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
631 (print_insn_coprocessor): Support fp16 instructions.
632
3e309328
RL		 6332016-02-24 Renlin Li <renlin.li@arm.com>
634
635 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
636 vminnm, vrint(mpna).
637
8afc7bea
RL		 6382016-02-24 Renlin Li <renlin.li@arm.com>
639
640 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
641 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
642
4fd7268a
L		 6432016-02-15 H.J. Lu <hongjiu.lu@intel.com>
644
645 * i386-dis.c (print_insn): Parenthesize expression to prevent
646 truncated addresses.
647 (OP_J): Likewise.
648
4670103e
CZ		 6492016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
650 Janek van Oirschot <jvanoirs@synopsys.com>
651
b99747ae
CZ		 652 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
653 variable.
4670103e 654
c1d9289f
NC		 6552016-02-04 Nick Clifton <nickc@redhat.com>
656
657 PR target/19561
658 * msp430-dis.c (print_insn_msp430): Add a special case for
659 decoding an RRC instruction with the ZC bit set in the extension
660 word.
661
a143b004
AB		 6622016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
663
664 * cgen-ibld.in (insert_normal): Rework calculation of shift.
665 * epiphany-ibld.c: Regenerate.
666 * fr30-ibld.c: Regenerate.
667 * frv-ibld.c: Regenerate.
668 * ip2k-ibld.c: Regenerate.
669 * iq2000-ibld.c: Regenerate.
670 * lm32-ibld.c: Regenerate.
671 * m32c-ibld.c: Regenerate.
672 * m32r-ibld.c: Regenerate.
673 * mep-ibld.c: Regenerate.
674 * mt-ibld.c: Regenerate.
675 * or1k-ibld.c: Regenerate.
676 * xc16x-ibld.c: Regenerate.
677 * xstormy16-ibld.c: Regenerate.
678
b89807c6
AB		 6792016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
680
681 * epiphany-dis.c: Regenerated from latest cpu files.
682
d8c823c8
MM		 6832016-02-01 Michael McConville <mmcco@mykolab.com>
684
685 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
686 test bit.
687
5bc5ae88
RL		 6882016-01-25 Renlin Li <renlin.li@arm.com>
689
690 * arm-dis.c (mapping_symbol_for_insn): New function.
691 (find_ifthen_state): Call mapping_symbol_for_insn().
692
0bff6e2d
MW		 6932016-01-20 Matthew Wahab <matthew.wahab@arm.com>
694
695 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
696 of MSR UAO immediate operand.
697
100b4f2e
MR		 6982016-01-18 Maciej W. Rozycki <macro@imgtec.com>
699
700 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
701 instruction support.
702
5c14705f
AM		 7032016-01-17 Alan Modra <amodra@gmail.com>
704
705 * configure: Regenerate.
706
4d82fe66
NC		 7072016-01-14 Nick Clifton <nickc@redhat.com>
708
709 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
710 instructions that can support stack pointer operations.
711 * rl78-decode.c: Regenerate.
712 * rl78-dis.c: Fix display of stack pointer in MOVW based
713 instructions.
714
651657fa
MW		 7152016-01-14 Matthew Wahab <matthew.wahab@arm.com>
716
717 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
718 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
719 erxtatus_el1 and erxaddr_el1.
720
105bde57
MW		 7212016-01-12 Matthew Wahab <matthew.wahab@arm.com>
722
723 * arm-dis.c (arm_opcodes): Add "esb".
724 (thumb_opcodes): Likewise.
725
afa8d405
PB		 7262016-01-11 Peter Bergner <bergner@vnet.ibm.com>
727
728 * ppc-opc.c <xscmpnedp>: Delete.
729 <xvcmpnedp>: Likewise.
730 <xvcmpnedp.>: Likewise.
731 <xvcmpnesp>: Likewise.
732 <xvcmpnesp.>: Likewise.
733
83c3256e
AS		 7342016-01-08 Andreas Schwab <schwab@linux-m68k.org>
735
736 PR gas/13050
737 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
738 addition to ISA_A.
739
6f2750fe
AM		 7402016-01-01 Alan Modra <amodra@gmail.com>
741
742 Update year range in copyright notice of all files.
743
3499769a
AM		 744For older changes see ChangeLog-2015
745\f
746Copyright (C) 2016 Free Software Foundation, Inc.
747
748Copying and distribution of this file, with or without modification,
749are permitted in any medium without royalty provided the copyright
750notice and this notice are preserved.
751
752Local Variables:
753mode: change-log
754left-margin: 8
755fill-column: 74
756version-control: never
757End:
GDB Binutils - Deliverables
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