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x86-64: don't allow use of %axl as accumulator
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
0645f0a2
JB		 12017-11-15 Jan Beulich <jbeulich@suse.com>
2
3 * i386-reg.tbl (axl): Remove Acc and Byte.
4 * i386-tbl.h: Re-generate.
5
be92cb14
JB		 62017-11-14 Jan Beulich <jbeulich@suse.com>
7
8 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
9 (vex_len_table): Use VPCOM.
10
2645e1d0
JB		 112017-11-14 Jan Beulich <jbeulich@suse.com>
12
13 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
14 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
15 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
16 vpcmpw): Move up.
17 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
18 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
19 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
20 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
21 vpcmpnltuw): New.
22 * i386-tbl.h: Re-generate.
23
df145ef6
JB		 242017-11-14 Jan Beulich <jbeulich@suse.com>
25
26 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
27 smov, ssca, stos, ssto, xlat): Drop Disp*.
28 * i386-tbl.h: Re-generate.
29
897e603c
JB		 302017-11-13 Jan Beulich <jbeulich@suse.com>
31
32 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
33 xsaveopt64): Add No_qSuf.
34 * i386-tbl.h: Re-generate.
35
793a1948
TC		 362017-11-09 Tamar Christina <tamar.christina@arm.com>
37
38 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
39 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
40 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
41 sder32_el2, vncr_el2.
42 (aarch64_sys_reg_supported_p): Likewise.
43 (aarch64_pstatefields): Add dit register.
44 (aarch64_pstatefield_supported_p): Likewise.
45 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
46 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
47 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
48 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
49 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
50 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
51 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
52
1a7ed57c
TC		 532017-11-09 Tamar Christina <tamar.christina@arm.com>
54
55 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
56 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
57 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
58 (QL_STLW, QL_STLX): New.
59
f42f1a1d
TC		 602017-11-09 Tamar Christina <tamar.christina@arm.com>
61
62 * aarch64-asm.h (ins_addr_offset): New.
63 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
64 (aarch64_ins_addr_offset): New.
65 * aarch64-asm-2.c: Regenerate.
66 * aarch64-dis.h (ext_addr_offset): New.
67 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
68 (aarch64_ext_addr_offset): New.
69 * aarch64-dis-2.c: Regenerate.
70 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
71 FLD_imm4_2 and FLD_SM3_imm2.
72 * aarch64-opc.c (fields): Add FLD_imm6_2,
73 FLD_imm4_2 and FLD_SM3_imm2.
74 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
75 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
76 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
77 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
78 * aarch64-tbl.h
79 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
80
b6b9ca0c
TC		 812017-11-09 Tamar Christina <tamar.christina@arm.com>
82
83 * aarch64-tbl.h
84 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
85 (aarch64_feature_sm4, aarch64_feature_sha3): New.
86 (aarch64_feature_fp_16_v8_2): New.
87 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
88 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
89 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
90
c0e7cef7
NC		 912017-11-08 Tamar Christina <tamar.christina@arm.com>
92
93 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
94 (aarch64_feature_sha2, aarch64_feature_aes): New.
95 (SHA2, AES): New.
96 (AES_INSN, SHA2_INSN): New.
97 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
98 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
99 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
100 Change to SHA2_INS.
101
dec41383
JW		 1022017-11-08 Jiong Wang <jiong.wang@arm.com>
103 Tamar Christina <tamar.christina@arm.com>
104
105 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
106 FP16 instructions, including vfmal.f16 and vfmsl.f16.
107
52eab766
AB		 1082017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
109
110 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
111
6003e27e
AM		 1122017-11-07 Alan Modra <amodra@gmail.com>
113
114 * opintl.h: Formatting, comment fixes.
115 (gettext, ngettext): Redefine when ENABLE_NLS.
116 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
117 (_): Define using gettext.
118 (textdomain, bindtextdomain): Use safer "do nothing".
119
fdddd290 1202017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
121
122 * arc-dis.c (print_hex): New variable.
123 (parse_option): Check for hex option.
124 (print_insn_arc): Use hexadecimal representation for short
125 immediate values when requested.
126 (print_arc_disassembler_options): Add hex option to the list.
127
3334eba7 1282017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
129
130 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
131 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
132 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
133 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
134 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
135 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
136 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
137 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
138 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
139 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
140 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
141 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
142 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
143 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
144 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
145 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
146 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
147 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
148 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
149 Changed opcodes.
150 (prealloc, prefetch*): Place them before ld instruction.
151 * arc-opc.c (skip_this_opcode): Add ARITH class.
152
e5d70d6b
AM		 1532017-10-25 Alan Modra <amodra@gmail.com>
154
155 PR 22348
156 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
157 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
158 (imm4flag, size_changed): Likewise.
159 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
160 (words, allWords, processing_argument_number): Likewise.
161 (cst4flag, size_changed): Likewise.
162 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
163 (crx_cst4_maps): Rename from cst4_maps.
164 (crx_no_op_insn): Rename from no_op_insn.
165
63a25ea0
AW		 1662017-10-24 Andrew Waterman <andrew@sifive.com>
167
168 * riscv-opc.c (match_c_addi16sp) : New function.
169 (match_c_addi4spn): New function.
170 (match_c_lui): Don't allow 0-immediate encodings.
171 (riscv_opcodes) <addi>: Use the above functions.
172 <add>: Likewise.
173 <c.addi4spn>: Likewise.
174 <c.addi16sp>: Likewise.
175
fe4e2a3c
IT		 1762017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
177
178 * i386-init.h: Regenerate
179 * i386-tbl.h: Likewise
180
2739ef6d
IT		 1812017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
182
183 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
184 (enum): Add EVEX_W_0F3854_P_2.
185 * i386-dis-evex.h (evex_table): Updated.
186 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
187 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
188 (cpu_flags): Add CpuAVX512_BITALG.
189 * i386-opc.h (enum): Add CpuAVX512_BITALG.
190 (i386_cpu_flags): Add cpuavx512_bitalg..
191 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
192 * i386-init.h: Regenerate.
193 * i386-tbl.h: Likewise.
194
1952017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
196
197 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
198 * i386-dis-evex.h (evex_table): Updated.
199 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
200 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
201 (cpu_flags): Add CpuAVX512_VNNI.
202 * i386-opc.h (enum): Add CpuAVX512_VNNI.
203 (i386_cpu_flags): Add cpuavx512_vnni.
204 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
205 * i386-init.h: Regenerate.
206 * i386-tbl.h: Likewise.
207
2082017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
209
210 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
211 (enum): Remove VEX_LEN_0F3A44_P_2.
212 (vex_len_table): Ditto.
213 (enum): Remove VEX_W_0F3A44_P_2.
214 (vew_w_table): Ditto.
215 (prefix_table): Adjust instructions (see prefixes above).
216 * i386-dis-evex.h (evex_table):
217 Add new instructions (see prefixes above).
218 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
219 (bitfield_cpu_flags): Ditto.
220 * i386-opc.h (enum): Ditto.
221 (i386_cpu_flags): Ditto.
222 (CpuUnused): Comment out to avoid zero-width field problem.
223 * i386-opc.tbl (vpclmulqdq): New instruction.
224 * i386-init.h: Regenerate.
225 * i386-tbl.h: Ditto.
226
2272017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
228
229 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
230 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
231 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
232 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
233 (vex_len_table): Ditto.
234 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
235 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
236 (vew_w_table): Ditto.
237 (prefix_table): Adjust instructions (see prefixes above).
238 * i386-dis-evex.h (evex_table):
239 Add new instructions (see prefixes above).
240 * i386-gen.c (cpu_flag_init): Add VAES.
241 (bitfield_cpu_flags): Ditto.
242 * i386-opc.h (enum): Ditto.
243 (i386_cpu_flags): Ditto.
244 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
245 * i386-init.h: Regenerate.
246 * i386-tbl.h: Ditto.
247
2482017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
249
250 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
251 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
252 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
253 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
254 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
255 (prefix_table): Updated (see prefixes above).
256 (three_byte_table): Likewise.
257 (vex_w_table): Likewise.
258 * i386-dis-evex.h: Likewise.
259 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
260 (cpu_flags): Add CpuGFNI.
261 * i386-opc.h (enum): Add CpuGFNI.
262 (i386_cpu_flags): Add cpugfni.
263 * i386-opc.tbl: Add Intel GFNI instructions.
264 * i386-init.h: Regenerate.
265 * i386-tbl.h: Likewise.
266
2672017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
268
269 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
270 Define EXbScalar and EXwScalar for OP_EX.
271 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
272 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
273 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
274 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
275 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
276 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
277 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
278 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
279 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
280 (OP_E_memory): Likewise.
281 * i386-dis-evex.h: Updated.
282 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
283 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
284 (cpu_flags): Add CpuAVX512_VBMI2.
285 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
286 (i386_cpu_flags): Add cpuavx512_vbmi2.
287 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
288 * i386-init.h: Regenerate.
289 * i386-tbl.h: Likewise.
290
2a6969e1
EB		 2912017-10-18 Eric Botcazou <ebotcazou@adacore.com>
292
293 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
294
3b4b0a62
JB		 2952017-10-12 James Bowman <james.bowman@ftdichip.com>
296
297 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
298 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
299 K15. Add jmpix pattern.
300
8e464506
AK		 3012017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
302
303 * s390-opc.txt (prno, tpei, irbm): New instructions added.
304
ee6767da
AK		 3052017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
306
307 * s390-opc.c (INSTR_SI_RD): New macro.
308 (INSTR_S_RD): Adjust example instruction.
309 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
310 SI_RD.
311
d2e6c9a3
AF		 3122017-10-01 Alexander Fedotov <alfedotov@gmail.com>
313
314 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
315 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
316 VLE multimple load/store instructions. Old e_ldm* variants are
317 kept as aliases.
318 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
319
8e43602e
NC		 3202017-09-27 Nick Clifton <nickc@redhat.com>
321
322 PR 22179
323 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
324 names for the fmv.x.s and fmv.s.x instructions respectively.
325
58a0b827
NC		 3262017-09-26 do <do@nerilex.org>
327
328 PR 22123
329 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
330 be used on CPUs that have emacs support.
331
57a024f4
SDJ		 3322017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
333
334 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
335
4ec521f2
KLC		 3362017-09-09 Kamil Rytarowski <n54@gmx.com>
337
338 * nds32-asm.c: Rename __BIT() to N32_BIT().
339 * nds32-asm.h: Likewise.
340 * nds32-dis.c: Likewise.
341
4e9ac44a
L		 3422017-09-09 H.J. Lu <hongjiu.lu@intel.com>
343
344 * i386-dis.c (last_active_prefix): Removed.
345 (ckprefix): Don't set last_active_prefix.
346 (NOTRACK_Fixup): Don't check last_active_prefix.
347
b55f3386
NC		 3482017-08-31 Nick Clifton <nickc@redhat.com>
349
350 * po/fr.po: Updated French translation.
351
59e8523b
JB		 3522017-08-31 James Bowman <james.bowman@ftdichip.com>
353
354 * ft32-dis.c (print_insn_ft32): Correct display of non-address
355 fields.
356
74081948
AF		 3572017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
358 Edmar Wienskoski <edmar.wienskoski@nxp.com>
359
360 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
361 PPC_OPCODE_EFS2 flag to "e200z4" entry.
362 New entries efs2 and spe2.
363 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
364 (SPE2_OPCD_SEGS): New macro.
365 (spe2_opcd_indices): New.
366 (disassemble_init_powerpc): Handle SPE2 opcodes.
367 (lookup_spe2): New function.
368 (print_insn_powerpc): call lookup_spe2.
369 * ppc-opc.c (insert_evuimm1_ex0): New function.
370 (extract_evuimm1_ex0): Likewise.
371 (insert_evuimm_lt8): Likewise.
372 (extract_evuimm_lt8): Likewise.
373 (insert_off_spe2): Likewise.
374 (extract_off_spe2): Likewise.
375 (insert_Ddd): Likewise.
376 (extract_Ddd): Likewise.
377 (DD): New operand.
378 (EVUIMM_LT8): Likewise.
379 (EVUIMM_LT16): Adjust.
380 (MMMM): New operand.
381 (EVUIMM_1): Likewise.
382 (EVUIMM_1_EX0): Likewise.
383 (EVUIMM_2): Adjust.
384 (NNN): New operand.
385 (VX_OFF_SPE2): Likewise.
386 (BBB): Likewise.
387 (DDD): Likewise.
388 (VX_MASK_DDD): New mask.
389 (HH): New operand.
390 (VX_RA_CONST): New macro.
391 (VX_RA_CONST_MASK): Likewise.
392 (VX_RB_CONST): Likewise.
393 (VX_RB_CONST_MASK): Likewise.
394 (VX_OFF_SPE2_MASK): Likewise.
395 (VX_SPE_CRFD): Likewise.
396 (VX_SPE_CRFD_MASK VX): Likewise.
397 (VX_SPE2_CLR): Likewise.
398 (VX_SPE2_CLR_MASK): Likewise.
399 (VX_SPE2_SPLATB): Likewise.
400 (VX_SPE2_SPLATB_MASK): Likewise.
401 (VX_SPE2_OCTET): Likewise.
402 (VX_SPE2_OCTET_MASK): Likewise.
403 (VX_SPE2_DDHH): Likewise.
404 (VX_SPE2_DDHH_MASK): Likewise.
405 (VX_SPE2_HH): Likewise.
406 (VX_SPE2_HH_MASK): Likewise.
407 (VX_SPE2_EVMAR): Likewise.
408 (VX_SPE2_EVMAR_MASK): Likewise.
409 (PPCSPE2): Likewise.
410 (PPCEFS2): Likewise.
411 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
412 (powerpc_macros): Map old SPE instructions have new names
413 with the same opcodes. Add SPE2 instructions which just are
414 mapped to SPE2.
415 (spe2_opcodes): Add SPE2 opcodes.
416
b80c7270
AM		 4172017-08-23 Alan Modra <amodra@gmail.com>
418
419 * ppc-opc.c: Formatting and comment fixes. Move insert and
420 extract functions earlier, deleting forward declarations.
421 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
422 RA_MASK.
423
67d888f5
PD		 4242017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
425
426 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
427
e3c2f928
AF		 4282017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
429 Edmar Wienskoski <edmar.wienskoski@nxp.com>
430
431 * ppc-opc.c (insert_evuimm2_ex0): New function.
432 (extract_evuimm2_ex0): Likewise.
433 (insert_evuimm4_ex0): Likewise.
434 (extract_evuimm4_ex0): Likewise.
435 (insert_evuimm8_ex0): Likewise.
436 (extract_evuimm8_ex0): Likewise.
437 (insert_evuimm_lt16): Likewise.
438 (extract_evuimm_lt16): Likewise.
439 (insert_rD_rS_even): Likewise.
440 (extract_rD_rS_even): Likewise.
441 (insert_off_lsp): Likewise.
442 (extract_off_lsp): Likewise.
443 (RD_EVEN): New operand.
444 (RS_EVEN): Likewise.
445 (RSQ): Adjust.
446 (EVUIMM_LT16): New operand.
447 (HTM_SI): Adjust.
448 (EVUIMM_2_EX0): New operand.
449 (EVUIMM_4): Adjust.
450 (EVUIMM_4_EX0): New operand.
451 (EVUIMM_8): Adjust.
452 (EVUIMM_8_EX0): New operand.
453 (WS): Adjust.
454 (VX_OFF): New operand.
455 (VX_LSP): New macro.
456 (VX_LSP_MASK): Likewise.
457 (VX_LSP_OFF_MASK): Likewise.
458 (PPC_OPCODE_LSP): Likewise.
459 (vle_opcodes): Add LSP opcodes.
460 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
461
cc4a945a
JW		 4622017-08-09 Jiong Wang <jiong.wang@arm.com>
463
464 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
465 register operands in CRC instructions.
466 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
467 comments.
468
b28b8b5e
L		 4692017-08-07 H.J. Lu <hongjiu.lu@intel.com>
470
471 * disassemble.c (disassembler): Mark big and mach with
472 ATTRIBUTE_UNUSED.
473
e347efc3
MR		 4742017-08-07 Maciej W. Rozycki <macro@imgtec.com>
475
476 * disassemble.c (disassembler): Remove arch/mach/endian
477 assertions.
478
7cbc739c
NC		 4792017-07-25 Nick Clifton <nickc@redhat.com>
480
481 PR 21739
482 * arc-opc.c (insert_rhv2): Use lower case first letter in error
483 message.
484 (insert_r0): Likewise.
485 (insert_r1): Likewise.
486 (insert_r2): Likewise.
487 (insert_r3): Likewise.
488 (insert_sp): Likewise.
489 (insert_gp): Likewise.
490 (insert_pcl): Likewise.
491 (insert_blink): Likewise.
492 (insert_ilink1): Likewise.
493 (insert_ilink2): Likewise.
494 (insert_ras): Likewise.
495 (insert_rbs): Likewise.
496 (insert_rcs): Likewise.
497 (insert_simm3s): Likewise.
498 (insert_rrange): Likewise.
499 (insert_r13el): Likewise.
500 (insert_fpel): Likewise.
501 (insert_blinkel): Likewise.
502 (insert_pclel): Likewise.
503 (insert_nps_bitop_size_2b): Likewise.
504 (insert_nps_imm_offset): Likewise.
505 (insert_nps_imm_entry): Likewise.
506 (insert_nps_size_16bit): Likewise.
507 (insert_nps_##NAME##_pos): Likewise.
508 (insert_nps_##NAME): Likewise.
509 (insert_nps_bitop_ins_ext): Likewise.
510 (insert_nps_##NAME): Likewise.
511 (insert_nps_min_hofs): Likewise.
512 (insert_nps_##NAME): Likewise.
513 (insert_nps_rbdouble_64): Likewise.
514 (insert_nps_misc_imm_offset): Likewise.
515 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
516 option description.
517
7684e580
JW		 5182017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
519 Jiong Wang <jiong.wang@arm.com>
520
521 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
522 correct the print.
523 * aarch64-dis-2.c: Regenerated.
524
47826cdb
AK		 5252017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
526
527 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
528 table.
529
2d2dbad0
NC		 5302017-07-20 Nick Clifton <nickc@redhat.com>
531
532 * po/de.po: Updated German translation.
533
70b448ba 5342017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
535
536 * arc-regs.h (sec_stat): New aux register.
537 (aux_kernel_sp): Likewise.
538 (aux_sec_u_sp): Likewise.
539 (aux_sec_k_sp): Likewise.
540 (sec_vecbase_build): Likewise.
541 (nsc_table_top): Likewise.
542 (nsc_table_base): Likewise.
543 (ersec_stat): Likewise.
544 (aux_sec_except): Likewise.
545
7179e0e6
CZ		 5462017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
547
548 * arc-opc.c (extract_uimm12_20): New function.
549 (UIMM12_20): New operand.
550 (SIMM3_5_S): Adjust.
551 * arc-tbl.h (sjli): Add new instruction.
552
684d5a10
JEM		 5532017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
554 John Eric Martin <John.Martin@emmicro-us.com>
555
556 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
557 (UIMM3_23): Adjust accordingly.
558 * arc-regs.h: Add/correct jli_base register.
559 * arc-tbl.h (jli_s): Likewise.
560
de194d85
YC		 5612017-07-18 Nick Clifton <nickc@redhat.com>
562
563 PR 21775
564 * aarch64-opc.c: Fix spelling typos.
565 * i386-dis.c: Likewise.
566
0f6329bd
RB		 5672017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
568
569 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
570 max_addr_offset and octets variables to size_t.
571
429d795d
AM		 5722017-07-12 Alan Modra <amodra@gmail.com>
573
574 * po/da.po: Update from translationproject.org/latest/opcodes/.
575 * po/de.po: Likewise.
576 * po/es.po: Likewise.
577 * po/fi.po: Likewise.
578 * po/fr.po: Likewise.
579 * po/id.po: Likewise.
580 * po/it.po: Likewise.
581 * po/nl.po: Likewise.
582 * po/pt_BR.po: Likewise.
583 * po/ro.po: Likewise.
584 * po/sv.po: Likewise.
585 * po/tr.po: Likewise.
586 * po/uk.po: Likewise.
587 * po/vi.po: Likewise.
588 * po/zh_CN.po: Likewise.
589
4162bb66
AM		 5902017-07-11 Yao Qi <yao.qi@linaro.org>
591 Alan Modra <amodra@gmail.com>
592
593 * cgen.sh: Mark generated files read-only.
594 * epiphany-asm.c: Regenerate.
595 * epiphany-desc.c: Regenerate.
596 * epiphany-desc.h: Regenerate.
597 * epiphany-dis.c: Regenerate.
598 * epiphany-ibld.c: Regenerate.
599 * epiphany-opc.c: Regenerate.
600 * epiphany-opc.h: Regenerate.
601 * fr30-asm.c: Regenerate.
602 * fr30-desc.c: Regenerate.
603 * fr30-desc.h: Regenerate.
604 * fr30-dis.c: Regenerate.
605 * fr30-ibld.c: Regenerate.
606 * fr30-opc.c: Regenerate.
607 * fr30-opc.h: Regenerate.
608 * frv-asm.c: Regenerate.
609 * frv-desc.c: Regenerate.
610 * frv-desc.h: Regenerate.
611 * frv-dis.c: Regenerate.
612 * frv-ibld.c: Regenerate.
613 * frv-opc.c: Regenerate.
614 * frv-opc.h: Regenerate.
615 * ip2k-asm.c: Regenerate.
616 * ip2k-desc.c: Regenerate.
617 * ip2k-desc.h: Regenerate.
618 * ip2k-dis.c: Regenerate.
619 * ip2k-ibld.c: Regenerate.
620 * ip2k-opc.c: Regenerate.
621 * ip2k-opc.h: Regenerate.
622 * iq2000-asm.c: Regenerate.
623 * iq2000-desc.c: Regenerate.
624 * iq2000-desc.h: Regenerate.
625 * iq2000-dis.c: Regenerate.
626 * iq2000-ibld.c: Regenerate.
627 * iq2000-opc.c: Regenerate.
628 * iq2000-opc.h: Regenerate.
629 * lm32-asm.c: Regenerate.
630 * lm32-desc.c: Regenerate.
631 * lm32-desc.h: Regenerate.
632 * lm32-dis.c: Regenerate.
633 * lm32-ibld.c: Regenerate.
634 * lm32-opc.c: Regenerate.
635 * lm32-opc.h: Regenerate.
636 * lm32-opinst.c: Regenerate.
637 * m32c-asm.c: Regenerate.
638 * m32c-desc.c: Regenerate.
639 * m32c-desc.h: Regenerate.
640 * m32c-dis.c: Regenerate.
641 * m32c-ibld.c: Regenerate.
642 * m32c-opc.c: Regenerate.
643 * m32c-opc.h: Regenerate.
644 * m32r-asm.c: Regenerate.
645 * m32r-desc.c: Regenerate.
646 * m32r-desc.h: Regenerate.
647 * m32r-dis.c: Regenerate.
648 * m32r-ibld.c: Regenerate.
649 * m32r-opc.c: Regenerate.
650 * m32r-opc.h: Regenerate.
651 * m32r-opinst.c: Regenerate.
652 * mep-asm.c: Regenerate.
653 * mep-desc.c: Regenerate.
654 * mep-desc.h: Regenerate.
655 * mep-dis.c: Regenerate.
656 * mep-ibld.c: Regenerate.
657 * mep-opc.c: Regenerate.
658 * mep-opc.h: Regenerate.
659 * mt-asm.c: Regenerate.
660 * mt-desc.c: Regenerate.
661 * mt-desc.h: Regenerate.
662 * mt-dis.c: Regenerate.
663 * mt-ibld.c: Regenerate.
664 * mt-opc.c: Regenerate.
665 * mt-opc.h: Regenerate.
666 * or1k-asm.c: Regenerate.
667 * or1k-desc.c: Regenerate.
668 * or1k-desc.h: Regenerate.
669 * or1k-dis.c: Regenerate.
670 * or1k-ibld.c: Regenerate.
671 * or1k-opc.c: Regenerate.
672 * or1k-opc.h: Regenerate.
673 * or1k-opinst.c: Regenerate.
674 * xc16x-asm.c: Regenerate.
675 * xc16x-desc.c: Regenerate.
676 * xc16x-desc.h: Regenerate.
677 * xc16x-dis.c: Regenerate.
678 * xc16x-ibld.c: Regenerate.
679 * xc16x-opc.c: Regenerate.
680 * xc16x-opc.h: Regenerate.
681 * xstormy16-asm.c: Regenerate.
682 * xstormy16-desc.c: Regenerate.
683 * xstormy16-desc.h: Regenerate.
684 * xstormy16-dis.c: Regenerate.
685 * xstormy16-ibld.c: Regenerate.
686 * xstormy16-opc.c: Regenerate.
687 * xstormy16-opc.h: Regenerate.
688
7639175c
AM		 6892017-07-07 Alan Modra <amodra@gmail.com>
690
691 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
692 * m32c-dis.c: Regenerate.
693 * mep-dis.c: Regenerate.
694
e4bdd679
BP		 6952017-07-05 Borislav Petkov <bp@suse.de>
696
697 * i386-dis.c: Enable ModRM.reg /6 aliases.
698
60c96dbf
RR		 6992017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
700
701 * opcodes/arm-dis.c: Support MVFR2 in disassembly
702 with vmrs and vmsr.
703
0d702cfe
TG		 7042017-07-04 Tristan Gingold <gingold@adacore.com>
705
706 * configure: Regenerate.
707
15e6ed8c
TG		 7082017-07-03 Tristan Gingold <gingold@adacore.com>
709
710 * po/opcodes.pot: Regenerate.
711
b1d3c886
MR		 7122017-06-30 Maciej W. Rozycki <macro@imgtec.com>
713
714 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
715 entries to the MSA ASE instruction block.
716
909b4e3d
MR		 7172017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
718 Maciej W. Rozycki <macro@imgtec.com>
719
720 * micromips-opc.c (XPA, XPAVZ): New macros.
721 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
722 "mthgc0".
723
f5b2fd52
MR		 7242017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
725 Maciej W. Rozycki <macro@imgtec.com>
726
727 * micromips-opc.c (I36): New macro.
728 (micromips_opcodes): Add "eretnc".
729
9785fc2a
MR		 7302017-06-30 Maciej W. Rozycki <macro@imgtec.com>
731 Andrew Bennett <andrew.bennett@imgtec.com>
732
733 * mips-dis.c (mips_calculate_combination_ases): Handle the
734 ASE_XPA_VIRT flag.
735 (parse_mips_ase_option): New function.
736 (parse_mips_dis_option): Factor out ASE option handling to the
737 new function. Call `mips_calculate_combination_ases'.
738 * mips-opc.c (XPAVZ): New macro.
739 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
740 "mfhgc0", "mthc0" and "mthgc0".
741
60804c53
MR		 7422017-06-29 Maciej W. Rozycki <macro@imgtec.com>
743
744 * mips-dis.c (mips_calculate_combination_ases): New function.
745 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
746 calculation to the new function.
747 (set_default_mips_dis_options): Call the new function.
748
2e74f9dd
AK		 7492017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
750
751 * arc-dis.c (parse_disassembler_options): Use
752 FOR_EACH_DISASSEMBLER_OPTION.
753
e1e94c49
AK		 7542017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
755
756 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
757 disassembler option strings.
758 (parse_cpu_option): Likewise.
759
65a55fbb
TC		 7602017-06-28 Tamar Christina <tamar.christina@arm.com>
761
762 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
763 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
764 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
765 (aarch64_feature_dotprod, DOT_INSN): New.
766 (udot, sdot): New.
767 * aarch64-dis-2.c: Regenerated.
768
c604a79a
JW		 7692017-06-28 Jiong Wang <jiong.wang@arm.com>
770
771 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
772
38bf472a
MR		 7732017-06-28 Maciej W. Rozycki <macro@imgtec.com>
774 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 775 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 776
777 * mips-formats.h (INT_BIAS): New macro.
778 (INT_ADJ): Redefine in INT_BIAS terms.
779 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
780 (mips_print_save_restore): New function.
781 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
782 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
783 call.
784 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
785 (print_mips16_insn_arg): Call `mips_print_save_restore' for
786 OP_SAVE_RESTORE_LIST handling, factored out from here.
787 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
788 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
789 (mips_builtin_opcodes): Add "restore" and "save" entries.
790 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
791 (IAMR2): New macro.
792 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
793
9bdfdbf9
AW		 7942017-06-23 Andrew Waterman <andrew@sifive.com>
795
796 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
797 alias; do not mark SLTI instruction as an alias.
798
2234eee6
L		 7992017-06-21 H.J. Lu <hongjiu.lu@intel.com>
800
801 * i386-dis.c (RM_0FAE_REG_5): Removed.
802 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
803 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
804 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
805 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
806 PREFIX_MOD_3_0F01_REG_5_RM_0.
807 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
808 PREFIX_MOD_3_0FAE_REG_5.
809 (mod_table): Update MOD_0FAE_REG_5.
810 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
811 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
812 * i386-tbl.h: Regenerated.
813
c2f76402
L		 8142017-06-21 H.J. Lu <hongjiu.lu@intel.com>
815
816 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
817 * i386-opc.tbl: Likewise.
818 * i386-tbl.h: Regenerated.
819
9fef80d6
L		 8202017-06-21 H.J. Lu <hongjiu.lu@intel.com>
821
822 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
823 and "jmp{&|}".
824 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
825 prefix.
826
0f6d864d
NC		 8272017-06-19 Nick Clifton <nickc@redhat.com>
828
829 PR binutils/21614
830 * score-dis.c (score_opcodes): Add sentinel.
831
e197589b
AM		 8322017-06-16 Alan Modra <amodra@gmail.com>
833
834 * rx-decode.c: Regenerate.
835
0d96e4df
L		 8362017-06-15 H.J. Lu <hongjiu.lu@intel.com>
837
838 PR binutils/21594
839 * i386-dis.c (OP_E_register): Check valid bnd register.
840 (OP_G): Likewise.
841
cd3ea7c6
NC		 8422017-06-15 Nick Clifton <nickc@redhat.com>
843
844 PR binutils/21595
845 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
846 range value.
847
63323b5b
NC		 8482017-06-15 Nick Clifton <nickc@redhat.com>
849
850 PR binutils/21588
851 * rl78-decode.opc (OP_BUF_LEN): Define.
852 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
853 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
854 array.
855 * rl78-decode.c: Regenerate.
856
08c7881b
NC		 8572017-06-15 Nick Clifton <nickc@redhat.com>
858
859 PR binutils/21586
860 * bfin-dis.c (gregs): Clip index to prevent overflow.
861 (regs): Likewise.
862 (regs_lo): Likewise.
863 (regs_hi): Likewise.
864
e64519d1
NC		 8652017-06-14 Nick Clifton <nickc@redhat.com>
866
867 PR binutils/21576
868 * score7-dis.c (score_opcodes): Add sentinel.
869
6394c606
YQ		 8702017-06-14 Yao Qi <yao.qi@linaro.org>
871
872 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
873 * arm-dis.c: Likewise.
874 * ia64-dis.c: Likewise.
875 * mips-dis.c: Likewise.
876 * spu-dis.c: Likewise.
877 * disassemble.h (print_insn_aarch64): New declaration, moved from
878 include/dis-asm.h.
879 (print_insn_big_arm, print_insn_big_mips): Likewise.
880 (print_insn_i386, print_insn_ia64): Likewise.
881 (print_insn_little_arm, print_insn_little_mips): Likewise.
882
db5fa770
NC		 8832017-06-14 Nick Clifton <nickc@redhat.com>
884
885 PR binutils/21587
886 * rx-decode.opc: Include libiberty.h
887 (GET_SCALE): New macro - validates access to SCALE array.
888 (GET_PSCALE): New macro - validates access to PSCALE array.
889 (DIs, SIs, S2Is, rx_disp): Use new macros.
890 * rx-decode.c: Regenerate.
891
05c966f3
AV		 8922017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
893
894 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
895
10045478
AK		 8962017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
897
898 * arc-dis.c (enforced_isa_mask): Declare.
899 (cpu_types): Likewise.
900 (parse_cpu_option): New function.
901 (parse_disassembler_options): Use it.
902 (print_insn_arc): Use enforced_isa_mask.
903 (print_arc_disassembler_options): Document new options.
904
88c1242d
YQ		 9052017-05-24 Yao Qi <yao.qi@linaro.org>
906
907 * alpha-dis.c: Include disassemble.h, don't include
908 dis-asm.h.
909 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
910 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
911 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
912 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
913 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
914 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
915 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
916 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
917 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
918 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
919 * moxie-dis.c, msp430-dis.c, mt-dis.c:
920 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
921 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
922 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
923 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
924 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
925 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
926 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
927 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
928 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
929 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
930 * z80-dis.c, z8k-dis.c: Likewise.
931 * disassemble.h: New file.
932
ab20fa4a
YQ		 9332017-05-24 Yao Qi <yao.qi@linaro.org>
934
935 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
936 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
937
003ca0fd
YQ		 9382017-05-24 Yao Qi <yao.qi@linaro.org>
939
940 * disassemble.c (disassembler): Add arguments a, big and mach.
941 Use them.
942
04ef582a
L		 9432017-05-22 H.J. Lu <hongjiu.lu@intel.com>
944
945 * i386-dis.c (NOTRACK_Fixup): New.
946 (NOTRACK): Likewise.
947 (NOTRACK_PREFIX): Likewise.
948 (last_active_prefix): Likewise.
949 (reg_table): Use NOTRACK on indirect call and jmp.
950 (ckprefix): Set last_active_prefix.
951 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
952 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
953 * i386-opc.h (NoTrackPrefixOk): New.
954 (i386_opcode_modifier): Add notrackprefixok.
955 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
956 Add notrack.
957 * i386-tbl.h: Regenerated.
958
64517994
JM		 9592017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
960
961 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
962 (X_IMM2): Define.
963 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
964 bfd_mach_sparc_v9m8.
965 (print_insn_sparc): Handle new operand types.
966 * sparc-opc.c (MASK_M8): Define.
967 (v6): Add MASK_M8.
968 (v6notlet): Likewise.
969 (v7): Likewise.
970 (v8): Likewise.
971 (v9): Likewise.
972 (v9a): Likewise.
973 (v9b): Likewise.
974 (v9c): Likewise.
975 (v9d): Likewise.
976 (v9e): Likewise.
977 (v9v): Likewise.
978 (v9m): Likewise.
979 (v9andleon): Likewise.
980 (m8): Define.
981 (HWS_VM8): Define.
982 (HWS2_VM8): Likewise.
983 (sparc_opcode_archs): Add entry for "m8".
984 (sparc_opcodes): Add OSA2017 and M8 instructions
985 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
986 fpx{ll,ra,rl}64x,
987 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
988 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
989 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
990 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
991 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
992 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
993 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
994 ASI_CORE_SELECT_COMMIT_NHT.
995
535b785f
AM		 9962017-05-18 Alan Modra <amodra@gmail.com>
997
998 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
999 * aarch64-dis.c: Likewise.
1000 * aarch64-gen.c: Likewise.
1001 * aarch64-opc.c: Likewise.
1002
25499ac7
MR		 10032017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1004 Matthew Fortune <matthew.fortune@imgtec.com>
1005
1006 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1007 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1008 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1009 (print_insn_arg) <OP_REG28>: Add handler.
1010 (validate_insn_args) <OP_REG28>: Handle.
1011 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1012 32-bit encoding and 9-bit immediates.
1013 (print_insn_mips16): Handle MIPS16 instructions that require
1014 32-bit encoding and MFC0/MTC0 operand decoding.
1015 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1016 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1017 (RD_C0, WR_C0, E2, E2MT): New macros.
1018 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1019 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1020 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1021 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1022 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1023 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1024 instructions, "swl", "swr", "sync" and its "sync_acquire",
1025 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1026 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1027 regular/extended entries for original MIPS16 ISA revision
1028 instructions whose extended forms are subdecoded in the MIPS16e2
1029 ISA revision: "li", "sll" and "srl".
1030
fdfb4752
MR		 10312017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1032
1033 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1034 reference in CP0 move operand decoding.
1035
a4f89915
MR		 10362017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1037
1038 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1039 type to hexadecimal.
1040 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1041
99e2d67a
MR		 10422017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1043
1044 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1045 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1046 "sync_rmb" and "sync_wmb" as aliases.
1047 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1048 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1049
53a346d8
CZ		 10502017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1051
1052 * arc-dis.c (parse_option): Update quarkse_em option..
1053 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1054 QUARKSE1.
1055 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1056
f91d48de
KC		 10572017-05-03 Kito Cheng <kito.cheng@gmail.com>
1058
1059 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1060
43e379d7
MC		 10612017-05-01 Michael Clark <michaeljclark@mac.com>
1062
1063 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1064 register.
1065
a4ddc54e
MR		 10662017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1067
1068 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1069 and branches and not synthetic data instructions.
1070
fe50e98c
BE		 10712017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1072
1073 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1074
126124cc
CZ		 10752017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1076
1077 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1078 * arc-opc.c (insert_r13el): New function.
1079 (R13_EL): Define.
1080 * arc-tbl.h: Add new enter/leave variants.
1081
be6a24d8
CZ		 10822017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1083
1084 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1085
0348fd79
MR		 10862017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1087
1088 * mips-dis.c (print_mips_disassembler_options): Add
1089 `no-aliases'.
1090
6e3d1f07
MR		 10912017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1092
1093 * mips16-opc.c (AL): New macro.
1094 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1095 of "ld" and "lw" as aliases.
1096
957f6b39
TC		 10972017-04-24 Tamar Christina <tamar.christina@arm.com>
1098
1099 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1100 arguments.
1101
a8cc8a54
AM		 11022017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1103 Alan Modra <amodra@gmail.com>
1104
1105 * ppc-opc.c (ELEV): Define.
1106 (vle_opcodes): Add se_rfgi and e_sc.
1107 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1108 for E200Z4.
1109
3ab87b68
JM		 11102017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1111
1112 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1113
792f174f
NC		 11142017-04-21 Nick Clifton <nickc@redhat.com>
1115
1116 PR binutils/21380
1117 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1118 LD3R and LD4R.
1119
42742084
AM		 11202017-04-13 Alan Modra <amodra@gmail.com>
1121
1122 * epiphany-desc.c: Regenerate.
1123 * fr30-desc.c: Regenerate.
1124 * frv-desc.c: Regenerate.
1125 * ip2k-desc.c: Regenerate.
1126 * iq2000-desc.c: Regenerate.
1127 * lm32-desc.c: Regenerate.
1128 * m32c-desc.c: Regenerate.
1129 * m32r-desc.c: Regenerate.
1130 * mep-desc.c: Regenerate.
1131 * mt-desc.c: Regenerate.
1132 * or1k-desc.c: Regenerate.
1133 * xc16x-desc.c: Regenerate.
1134 * xstormy16-desc.c: Regenerate.
1135
9a85b496
AM		 11362017-04-11 Alan Modra <amodra@gmail.com>
1137
ef85eab0 1138 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 1139 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1140 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 1141 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1142 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 1143 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1144 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 1145 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 1146 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 1147
62adc510
AM		 11482017-04-10 Alan Modra <amodra@gmail.com>
1149
1150 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1151 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1152 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1153 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1154
aa808707
PC		 11552017-04-09 Pip Cet <pipcet@gmail.com>
1156
1157 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1158 appropriate floating-point precision directly.
1159
ac8f0f72
AM		 11602017-04-07 Alan Modra <amodra@gmail.com>
1161
1162 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1163 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1164 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1165 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1166 vector instructions with E6500 not PPCVEC2.
1167
62ecb94c
PC		 11682017-04-06 Pip Cet <pipcet@gmail.com>
1169
1170 * Makefile.am: Add wasm32-dis.c.
1171 * configure.ac: Add wasm32-dis.c to wasm32 target.
1172 * disassemble.c: Add wasm32 disassembler code.
1173 * wasm32-dis.c: New file.
1174 * Makefile.in: Regenerate.
1175 * configure: Regenerate.
1176 * po/POTFILES.in: Regenerate.
1177 * po/opcodes.pot: Regenerate.
1178
f995bbe8
PA		 11792017-04-05 Pedro Alves <palves@redhat.com>
1180
1181 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1182 * arm-dis.c (parse_arm_disassembler_options): Constify.
1183 * ppc-dis.c (powerpc_init_dialect): Constify local.
1184 * vax-dis.c (parse_disassembler_options): Constify.
1185
b5292032
PD		 11862017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1187
1188 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1189 RISCV_GP_SYMBOL.
1190
f96bd6c2
PC		 11912017-03-30 Pip Cet <pipcet@gmail.com>
1192
1193 * configure.ac: Add (empty) bfd_wasm32_arch target.
1194 * configure: Regenerate
1195 * po/opcodes.pot: Regenerate.
1196
f7c514a3
JM		 11972017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1198
1199 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1200 OSA2015.
1201 * opcodes/sparc-opc.c (asi_table): New ASIs.
1202
52be03fd
AM		 12032017-03-29 Alan Modra <amodra@gmail.com>
1204
1205 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1206 "raw" option.
1207 (lookup_powerpc): Don't special case -1 dialect. Handle
1208 PPC_OPCODE_RAW.
1209 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1210 lookup_powerpc call, pass it on second.
1211
9b753937
AM		 12122017-03-27 Alan Modra <amodra@gmail.com>
1213
1214 PR 21303
1215 * ppc-dis.c (struct ppc_mopt): Comment.
1216 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1217
c0c31e91
RZ		 12182017-03-27 Rinat Zelig <rinat@mellanox.com>
1219
1220 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1221 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1222 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1223 (insert_nps_misc_imm_offset): New function.
1224 (extract_nps_misc imm_offset): New function.
1225 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1226 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1227
2253c8f0
AK		 12282017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1229
1230 * s390-mkopc.c (main): Remove vx2 check.
1231 * s390-opc.txt: Remove vx2 instruction flags.
1232
645d3342
RZ		 12332017-03-21 Rinat Zelig <rinat@mellanox.com>
1234
1235 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1236 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1237 (insert_nps_imm_offset): New function.
1238 (extract_nps_imm_offset): New function.
1239 (insert_nps_imm_entry): New function.
1240 (extract_nps_imm_entry): New function.
1241
4b94dd2d
AM		 12422017-03-17 Alan Modra <amodra@gmail.com>
1243
1244 PR 21248
1245 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1246 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1247 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1248
b416fe87
KC		 12492017-03-14 Kito Cheng <kito.cheng@gmail.com>
1250
1251 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1252 <c.andi>: Likewise.
1253 <c.addiw> Likewise.
1254
03b039a5
KC		 12552017-03-14 Kito Cheng <kito.cheng@gmail.com>
1256
1257 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1258
2c232b83
AW		 12592017-03-13 Andrew Waterman <andrew@sifive.com>
1260
1261 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1262 <srl> Likewise.
1263 <srai> Likewise.
1264 <sra> Likewise.
1265
86fa6981
L		 12662017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1267
1268 * i386-gen.c (opcode_modifiers): Replace S with Load.
1269 * i386-opc.h (S): Removed.
1270 (Load): New.
1271 (i386_opcode_modifier): Replace s with load.
1272 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1273 and {evex}. Replace S with Load.
1274 * i386-tbl.h: Regenerated.
1275
c1fe188b
L		 12762017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1277
1278 * i386-opc.tbl: Use CpuCET on rdsspq.
1279 * i386-tbl.h: Regenerated.
1280
4b8b687e
PB		 12812017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1282
1283 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1284 <vsx>: Do not use PPC_OPCODE_VSX3;
1285
1437d063
PB		 12862017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1287
1288 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1289
603555e5
L		 12902017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1291
1292 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1293 (MOD_0F1E_PREFIX_1): Likewise.
1294 (MOD_0F38F5_PREFIX_2): Likewise.
1295 (MOD_0F38F6_PREFIX_0): Likewise.
1296 (RM_0F1E_MOD_3_REG_7): Likewise.
1297 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1298 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1299 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1300 (PREFIX_0F1E): Likewise.
1301 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1302 (PREFIX_0F38F5): Likewise.
1303 (dis386_twobyte): Use PREFIX_0F1E.
1304 (reg_table): Add REG_0F1E_MOD_3.
1305 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1306 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1307 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1308 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1309 (three_byte_table): Use PREFIX_0F38F5.
1310 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1311 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1312 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1313 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1314 PREFIX_MOD_3_0F01_REG_5_RM_2.
1315 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1316 (cpu_flags): Add CpuCET.
1317 * i386-opc.h (CpuCET): New enum.
1318 (CpuUnused): Commented out.
1319 (i386_cpu_flags): Add cpucet.
1320 * i386-opc.tbl: Add Intel CET instructions.
1321 * i386-init.h: Regenerated.
1322 * i386-tbl.h: Likewise.
1323
73f07bff
AM		 13242017-03-06 Alan Modra <amodra@gmail.com>
1325
1326 PR 21124
1327 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1328 (extract_raq, extract_ras, extract_rbx): New functions.
1329 (powerpc_operands): Use opposite corresponding insert function.
1330 (Q_MASK): Define.
1331 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1332 register restriction.
1333
65b48a81
PB		 13342017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1335
1336 * disassemble.c Include "safe-ctype.h".
1337 (disassemble_init_for_target): Handle s390 init.
1338 (remove_whitespace_and_extra_commas): New function.
1339 (disassembler_options_cmp): Likewise.
1340 * arm-dis.c: Include "libiberty.h".
1341 (NUM_ELEM): Delete.
1342 (regnames): Use long disassembler style names.
1343 Add force-thumb and no-force-thumb options.
1344 (NUM_ARM_REGNAMES): Rename from this...
1345 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1346 (get_arm_regname_num_options): Delete.
1347 (set_arm_regname_option): Likewise.
1348 (get_arm_regnames): Likewise.
1349 (parse_disassembler_options): Likewise.
1350 (parse_arm_disassembler_option): Rename from this...
1351 (parse_arm_disassembler_options): ...to this. Make static.
1352 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1353 (print_insn): Use parse_arm_disassembler_options.
1354 (disassembler_options_arm): New function.
1355 (print_arm_disassembler_options): Handle updated regnames.
1356 * ppc-dis.c: Include "libiberty.h".
1357 (ppc_opts): Add "32" and "64" entries.
1358 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1359 (powerpc_init_dialect): Add break to switch statement.
1360 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1361 (disassembler_options_powerpc): New function.
1362 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1363 Remove printing of "32" and "64".
1364 * s390-dis.c: Include "libiberty.h".
1365 (init_flag): Remove unneeded variable.
1366 (struct s390_options_t): New structure type.
1367 (options): New structure.
1368 (init_disasm): Rename from this...
1369 (disassemble_init_s390): ...to this. Add initializations for
1370 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1371 (print_insn_s390): Delete call to init_disasm.
1372 (disassembler_options_s390): New function.
1373 (print_s390_disassembler_options): Print using information from
1374 struct 'options'.
1375 * po/opcodes.pot: Regenerate.
1376
15c7c1d8
JB		 13772017-02-28 Jan Beulich <jbeulich@suse.com>
1378
1379 * i386-dis.c (PCMPESTR_Fixup): New.
1380 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1381 (prefix_table): Use PCMPESTR_Fixup.
1382 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1383 PCMPESTR_Fixup.
1384 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1385 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1386 Split 64-bit and non-64-bit variants.
1387 * opcodes/i386-tbl.h: Re-generate.
1388
582e12bf
RS		 13892017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1390
1391 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1392 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1393 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1394 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1395 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1396 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1397 (OP_SVE_V_HSD): New macros.
1398 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1399 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1400 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1401 (aarch64_opcode_table): Add new SVE instructions.
1402 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1403 for rotation operands. Add new SVE operands.
1404 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1405 (ins_sve_quad_index): Likewise.
1406 (ins_imm_rotate): Split into...
1407 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1408 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1409 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1410 functions.
1411 (aarch64_ins_sve_addr_ri_s4): New function.
1412 (aarch64_ins_sve_quad_index): Likewise.
1413 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1414 * aarch64-asm-2.c: Regenerate.
1415 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1416 (ext_sve_quad_index): Likewise.
1417 (ext_imm_rotate): Split into...
1418 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1419 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1420 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1421 functions.
1422 (aarch64_ext_sve_addr_ri_s4): New function.
1423 (aarch64_ext_sve_quad_index): Likewise.
1424 (aarch64_ext_sve_index): Allow quad indices.
1425 (do_misc_decoding): Likewise.
1426 * aarch64-dis-2.c: Regenerate.
1427 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1428 aarch64_field_kinds.
1429 (OPD_F_OD_MASK): Widen by one bit.
1430 (OPD_F_NO_ZR): Bump accordingly.
1431 (get_operand_field_width): New function.
1432 * aarch64-opc.c (fields): Add new SVE fields.
1433 (operand_general_constraint_met_p): Handle new SVE operands.
1434 (aarch64_print_operand): Likewise.
1435 * aarch64-opc-2.c: Regenerate.
1436
f482d304
RS		 14372017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1438
1439 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1440 (aarch64_feature_compnum): ...this.
1441 (SIMD_V8_3): Replace with...
1442 (COMPNUM): ...this.
1443 (CNUM_INSN): New macro.
1444 (aarch64_opcode_table): Use it for the complex number instructions.
1445
7db2c588
JB		 14462017-02-24 Jan Beulich <jbeulich@suse.com>
1447
1448 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1449
1e9d41d4
SL		 14502017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1451
1452 Add support for associating SPARC ASIs with an architecture level.
1453 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1454 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1455 decoding of SPARC ASIs.
1456
53c4d625
JB		 14572017-02-23 Jan Beulich <jbeulich@suse.com>
1458
1459 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1460 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1461
11648de5
JB		 14622017-02-21 Jan Beulich <jbeulich@suse.com>
1463
1464 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1465 1 (instead of to itself). Correct typo.
1466
f98d33be
AW		 14672017-02-14 Andrew Waterman <andrew@sifive.com>
1468
1469 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1470 pseudoinstructions.
1471
773fb663
RS		 14722017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1473
1474 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1475 (aarch64_sys_reg_supported_p): Handle them.
1476
cc07cda6
CZ		 14772017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1478
1479 * arc-opc.c (UIMM6_20R): Define.
1480 (SIMM12_20): Use above.
1481 (SIMM12_20R): Define.
1482 (SIMM3_5_S): Use above.
1483 (UIMM7_A32_11R_S): Define.
1484 (UIMM7_9_S): Use above.
1485 (UIMM3_13R_S): Define.
1486 (SIMM11_A32_7_S): Use above.
1487 (SIMM9_8R): Define.
1488 (UIMM10_A32_8_S): Use above.
1489 (UIMM8_8R_S): Define.
1490 (W6): Use above.
1491 (arc_relax_opcodes): Use all above defines.
1492
66a5a740
VG		 14932017-02-15 Vineet Gupta <vgupta@synopsys.com>
1494
1495 * arc-regs.h: Distinguish some of the registers different on
1496 ARC700 and HS38 cpus.
1497
7e0de605
AM		 14982017-02-14 Alan Modra <amodra@gmail.com>
1499
1500 PR 21118
1501 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1502 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1503
54064fdb
AM		 15042017-02-11 Stafford Horne <shorne@gmail.com>
1505 Alan Modra <amodra@gmail.com>
1506
1507 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1508 Use insn_bytes_value and insn_int_value directly instead. Don't
1509 free allocated memory until function exit.
1510
dce75bf9
NP		 15112017-02-10 Nicholas Piggin <npiggin@gmail.com>
1512
1513 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1514
1b7e3d2f
NC		 15152017-02-03 Nick Clifton <nickc@redhat.com>
1516
1517 PR 21096
1518 * aarch64-opc.c (print_register_list): Ensure that the register
1519 list index will fir into the tb buffer.
1520 (print_register_offset_address): Likewise.
1521 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1522
8ec5cf65
AD		 15232017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1524
1525 PR 21056
1526 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1527 instructions when the previous fetch packet ends with a 32-bit
1528 instruction.
1529
a1aa5e81
DD		 15302017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1531
1532 * pru-opc.c: Remove vague reference to a future GDB port.
1533
add3afb2
NC		 15342017-01-20 Nick Clifton <nickc@redhat.com>
1535
1536 * po/ga.po: Updated Irish translation.
1537
c13a63b0
SN		 15382017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1539
1540 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1541
9608051a
YQ		 15422017-01-13 Yao Qi <yao.qi@linaro.org>
1543
1544 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1545 if FETCH_DATA returns 0.
1546 (m68k_scan_mask): Likewise.
1547 (print_insn_m68k): Update code to handle -1 return value.
1548
f622ea96
YQ		 15492017-01-13 Yao Qi <yao.qi@linaro.org>
1550
1551 * m68k-dis.c (enum print_insn_arg_error): New.
1552 (NEXTBYTE): Replace -3 with
1553 PRINT_INSN_ARG_MEMORY_ERROR.
1554 (NEXTULONG): Likewise.
1555 (NEXTSINGLE): Likewise.
1556 (NEXTDOUBLE): Likewise.
1557 (NEXTDOUBLE): Likewise.
1558 (NEXTPACKED): Likewise.
1559 (FETCH_ARG): Likewise.
1560 (FETCH_DATA): Update comments.
1561 (print_insn_arg): Update comments. Replace magic numbers with
1562 enum.
1563 (match_insn_m68k): Likewise.
1564
620214f7
IT		 15652017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1566
1567 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1568 * i386-dis-evex.h (evex_table): Updated.
1569 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1570 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1571 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1572 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1573 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1574 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1575 * i386-init.h: Regenerate.
1576 * i386-tbl.h: Ditto.
1577
d95014a2
YQ		 15782017-01-12 Yao Qi <yao.qi@linaro.org>
1579
1580 * msp430-dis.c (msp430_singleoperand): Return -1 if
1581 msp430dis_opcode_signed returns false.
1582 (msp430_doubleoperand): Likewise.
1583 (msp430_branchinstr): Return -1 if
1584 msp430dis_opcode_unsigned returns false.
1585 (msp430x_calla_instr): Likewise.
1586 (print_insn_msp430): Likewise.
1587
0ae60c3e
NC		 15882017-01-05 Nick Clifton <nickc@redhat.com>
1589
1590 PR 20946
1591 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1592 could not be matched.
1593 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1594 NULL.
1595
d74d4880
SN		 15962017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1597
1598 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1599 (aarch64_opcode_table): Use RCPC_INSN.
1600
cc917fd9
KC		 16012017-01-03 Kito Cheng <kito.cheng@gmail.com>
1602
1603 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1604 extension.
1605 * riscv-opcodes/all-opcodes: Likewise.
1606
b52d3cfc
DP		 16072017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1608
1609 * riscv-dis.c (print_insn_args): Add fall through comment.
1610
f90c58d5
NC		 16112017-01-03 Nick Clifton <nickc@redhat.com>
1612
1613 * po/sr.po: New Serbian translation.
1614 * configure.ac (ALL_LINGUAS): Add sr.
1615 * configure: Regenerate.
1616
f47b0d4a
AM		 16172017-01-02 Alan Modra <amodra@gmail.com>
1618
1619 * epiphany-desc.h: Regenerate.
1620 * epiphany-opc.h: Regenerate.
1621 * fr30-desc.h: Regenerate.
1622 * fr30-opc.h: Regenerate.
1623 * frv-desc.h: Regenerate.
1624 * frv-opc.h: Regenerate.
1625 * ip2k-desc.h: Regenerate.
1626 * ip2k-opc.h: Regenerate.
1627 * iq2000-desc.h: Regenerate.
1628 * iq2000-opc.h: Regenerate.
1629 * lm32-desc.h: Regenerate.
1630 * lm32-opc.h: Regenerate.
1631 * m32c-desc.h: Regenerate.
1632 * m32c-opc.h: Regenerate.
1633 * m32r-desc.h: Regenerate.
1634 * m32r-opc.h: Regenerate.
1635 * mep-desc.h: Regenerate.
1636 * mep-opc.h: Regenerate.
1637 * mt-desc.h: Regenerate.
1638 * mt-opc.h: Regenerate.
1639 * or1k-desc.h: Regenerate.
1640 * or1k-opc.h: Regenerate.
1641 * xc16x-desc.h: Regenerate.
1642 * xc16x-opc.h: Regenerate.
1643 * xstormy16-desc.h: Regenerate.
1644 * xstormy16-opc.h: Regenerate.
1645
2571583a
AM		 16462017-01-02 Alan Modra <amodra@gmail.com>
1647
1648 Update year range in copyright notice of all files.
1649
5c1ad6b5 1650For older changes see ChangeLog-2016
3499769a 1651\f
5c1ad6b5 1652Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1653
1654Copying and distribution of this file, with or without modification,
1655are permitted in any medium without royalty provided the copyright
1656notice and this notice are preserved.
1657
1658Local Variables:
1659mode: change-log
1660left-margin: 8
1661fill-column: 74
1662version-control: never
1663End:
GDB Binutils - Deliverables
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