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* defs.h (GCC_GENERATED_STDINT_H): Define.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3e126784
L		 12008-09-11 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
4 * i386-tbl.h: Regenerated.
5
ddab3d59
JB		 62008-08-28 Jan Beulich <jbeulich@novell.com>
7
8 * i386-dis.c (dis386): Adjust far return mnemonics.
9 * i386-opc.tbl: Add retf.
10 * i386-tbl.h: Re-generate.
11
b19d5385
JB		 122008-08-28 Jan Beulich <jbeulich@novell.com>
13
14 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
15
1ca35711
L		 162008-08-28 H.J. Lu <hongjiu.lu@intel.com>
17
18 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
19 * ia64-gen.c (lookup_specifier): Likewise.
20
21 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
22 * ia64-raw.tbl: Likewise.
23 * ia64-waw.tbl: Likewise.
24 * ia64-asmtab.c: Regenerated.
25
515c56e7
L		 262008-08-27 H.J. Lu <hongjiu.lu@intel.com>
27
28 * i386-opc.tbl: Correct fidivr operand size.
29
30 * i386-tbl.h: Regenerated.
31
da594c4a
AM		 322008-08-24 Alan Modra <amodra@bigpond.net.au>
33
34 * configure.in: Update a number of obsolete autoconf macros.
35 * aclocal.m4: Regenerate.
36
a5ff0eb2
L		 372008-08-20 H.J. Lu <hongjiu.lu@intel.com>
38
39 AVX Programming Reference (August, 2008)
40 * i386-dis.c (PREFIX_VEX_38DB): New.
41 (PREFIX_VEX_38DC): Likewise.
42 (PREFIX_VEX_38DD): Likewise.
43 (PREFIX_VEX_38DE): Likewise.
44 (PREFIX_VEX_38DF): Likewise.
45 (PREFIX_VEX_3ADF): Likewise.
46 (VEX_LEN_38DB_P_2): Likewise.
47 (VEX_LEN_38DC_P_2): Likewise.
48 (VEX_LEN_38DD_P_2): Likewise.
49 (VEX_LEN_38DE_P_2): Likewise.
50 (VEX_LEN_38DF_P_2): Likewise.
51 (VEX_LEN_3ADF_P_2): Likewise.
52 (PREFIX_VEX_3A04): Updated.
53 (VEX_LEN_3A06_P_2): Likewise.
54 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
55 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
56 (x86_64_table): Likewise.
57 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
58 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
59 VEX_LEN_3ADF_P_2.
60
61 * i386-opc.tbl: Add AES + AVX instructions.
62 * i386-init.h: Regenerated.
63 * i386-tbl.h: Likewise.
64
7dc6076f
AK		 652008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
66
67 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
68 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
69
7357c5b6
AM		 702008-08-15 Alan Modra <amodra@bigpond.net.au>
71
72 PR 6526
73 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
74 * Makefile.in: Regenerate.
75 * aclocal.m4: Regenerate.
76 * config.in: Regenerate.
77 * configure: Regenerate.
78
899d85be
AM		 792008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
80
81 PR 6825
82 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
83
dfb07592
L		 842008-08-12 H.J. Lu <hongjiu.lu@intel.com>
85
86 * i386-opc.tbl: Add syscall and sysret for Cpu64.
87
88 * i386-tbl.h: Regenerated.
89
323ee3f4
AM		 902008-08-04 Alan Modra <amodra@bigpond.net.au>
91
92 * Makefile.am (POTFILES.in): Set LC_ALL=C.
93 * Makefile.in: Regenerate.
94 * po/POTFILES.in: Regenerate.
95
9b4e5766
PB		 962008-08-01 Peter Bergner <bergner@vnet.ibm.com>
97
98 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
99 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
100 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
101 * ppc-opc.c (insert_xt6): New static function.
102 (extract_xt6): Likewise.
103 (insert_xa6): Likewise.
104 (extract_xa6: Likewise.
105 (insert_xb6): Likewise.
106 (extract_xb6): Likewise.
107 (insert_xb6s): Likewise.
108 (extract_xb6s): Likewise.
109 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
110 XX3DM_MASK, PPCVSX): New.
111 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
112 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
113
20fd6e2e
PA		 1142008-08-01 Pedro Alves <pedro@codesourcery.com>
115
116 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
117 * Makefile.in: Regenerate.
118
a656ed5b
L		 1192008-08-01 H.J. Lu <hongjiu.lu@intel.com>
120
121 * i386-reg.tbl: Use Dw2Inval on AVX registers.
122 * i386-tbl.h: Regenerated.
123
081ba1b3
AM		 1242008-07-30 Michael J. Eager <eager@eagercon.com>
125
126 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
127 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
128 (insert_sprg, PPC405): Use PPC_OPCODE_405.
129 (powerpc_opcodes): Add Xilinx APU related opcodes.
130
0af1713e
AM		 1312008-07-30 Alan Modra <amodra@bigpond.net.au>
132
133 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
134
30c09090
RS		 1352008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
136
137 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
138
c27e721e
AN		 1392008-07-07 Adam Nemet <anemet@caviumnetworks.com>
140
141 * mips-opc.c (CP): New macro.
142 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
143 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
144 dmtc2 Octeon instructions.
145
bd2e2557
SS		 1462008-07-07 Stan Shebs <stan@codesourcery.com>
147
148 * dis-init.c (init_disassemble_info): Init endian_code field.
149 * arm-dis.c (print_insn): Disassemble code according to
150 setting of endian_code.
151 (print_insn_big_arm): Detect when BE8 extension flag has been set.
152
6ba2a415
RS		 1532008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
154
155 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
156 for ELF symbols.
157
c8187e15
PB		 1582008-06-25 Peter Bergner <bergner@vnet.ibm.com>
159
160 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
161 (print_ppc_disassembler_options): Likewise.
162 * ppc-opc.c (PPC464): Define.
163 (powerpc_opcodes): Add mfdcrux and mtdcrux.
164
7a283e07
RW		 1652008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
166
167 * configure: Regenerate.
168
fa452fa6
PB		 1692008-06-13 Peter Bergner <bergner@vnet.ibm.com>
170
171 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
172 ppc_cpu_t typedef.
173 (struct dis_private): New.
174 (POWERPC_DIALECT): New define.
175 (powerpc_dialect): Renamed to...
176 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
177 struct dis_private.
178 (print_insn_big_powerpc): Update for using structure in
179 info->private_data.
180 (print_insn_little_powerpc): Likewise.
181 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
182 (skip_optional_operands): Likewise.
183 (print_insn_powerpc): Likewise. Remove initialization of dialect.
184 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
185 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
186 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
187 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
188 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
189 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
190 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
191 param to be of type ppc_cpu_t. Update prototype.
192
bb35fb24
NC		 1932008-06-12 Adam Nemet <anemet@caviumnetworks.com>
194
195 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
196 +s, +S.
197 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
198 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
199 syncw, syncws, vm3mulu, vm0 and vmulu.
200
dd3cbb7e
NC		 201 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
202 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
203 seqi, sne and snei.
204
a5dabbb0
L		 2052008-05-30 H.J. Lu <hongjiu.lu@intel.com>
206
207 * i386-opc.tbl: Add vmovd with 64bit operand.
208 * i386-tbl.h: Regenerated.
209
725a9891
MS		 2102008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
211
212 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
213
cbc80391
L		 2142008-05-22 H.J. Lu <hongjiu.lu@intel.com>
215
216 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
217 * i386-tbl.h: Regenerated.
218
116615c5
L		 2192008-05-22 H.J. Lu <hongjiu.lu@intel.com>
220
221 PR gas/6517
222 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
223 into 32bit and 64bit. Remove Reg64|Qword and add
224 IgnoreSize|No_qSuf on 32bit version.
225 * i386-tbl.h: Regenerated.
226
d9479f2d
L		 2272008-05-21 H.J. Lu <hongjiu.lu@intel.com>
228
229 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
230 * i386-tbl.h: Regenerated.
231
3ce6fddb
NC		 2322008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
233
234 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
235
8944f3c2
AM		 2362008-05-14 Alan Modra <amodra@bigpond.net.au>
237
238 * Makefile.am: Run "make dep-am".
239 * Makefile.in: Regenerate.
240
f1f8f695
L		 2412008-05-02 H.J. Lu <hongjiu.lu@intel.com>
242
243 * i386-dis.c (MOVBE_Fixup): New.
244 (Mo): Likewise.
245 (PREFIX_0F3880): Likewise.
246 (PREFIX_0F3881): Likewise.
247 (PREFIX_0F38F0): Updated.
248 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
249 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
250 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
251
252 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
253 CPU_EPT_FLAGS.
254 (cpu_flags): Add CpuMovbe and CpuEPT.
255
256 * i386-opc.h (CpuMovbe): New.
257 (CpuEPT): Likewise.
258 (CpuLM): Updated.
259 (i386_cpu_flags): Add cpumovbe and cpuept.
260
261 * i386-opc.tbl: Add entries for movbe and EPT instructions.
262 * i386-init.h: Regenerated.
263 * i386-tbl.h: Likewise.
264
89aa3097
AN		 2652008-04-29 Adam Nemet <anemet@caviumnetworks.com>
266
267 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
268 the two drem and the two dremu macros.
269
39c5c168
AN		 2702008-04-28 Adam Nemet <anemet@caviumnetworks.com>
271
272 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
273 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
274 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
275 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
276
f04d18b7
DM		 2772008-04-25 David S. Miller <davem@davemloft.net>
278
279 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
280 instead of %sys_tick_cmpr, as suggested in architecture manuals.
281
6194aaab
L		 2822008-04-23 Paolo Bonzini <bonzini@gnu.org>
283
284 * aclocal.m4: Regenerate.
285 * configure: Regenerate.
286
1a6b486f
DM		 2872008-04-23 David S. Miller <davem@davemloft.net>
288
289 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
290 extended values.
291 (prefetch_table): Add missing values.
292
81f8a913
L		 2932008-04-22 H.J. Lu <hongjiu.lu@intel.com>
294
295 * i386-gen.c (opcode_modifiers): Add NoAVX.
296
297 * i386-opc.h (NoAVX): New.
298 (OldGcc): Updated.
299 (i386_opcode_modifier): Add noavx.
300
301 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
302 instructions which don't have AVX equivalent.
303 * i386-tbl.h: Regenerated.
304
dae39acc
L		 3052008-04-18 H.J. Lu <hongjiu.lu@intel.com>
306
307 * i386-dis.c (OP_VEX_FMA): New.
308 (OP_EX_VexImmW): Likewise.
309 (VexFMA): Likewise.
310 (Vex128FMA): Likewise.
311 (EXVexImmW): Likewise.
312 (get_vex_imm8): Likewise.
313 (OP_EX_VexReg): Likewise.
314 (vex_i4_done): Renamed to ...
315 (vex_w_done): This.
316 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
317 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
318 FMA instructions.
319 (print_insn): Updated.
320 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
321 (OP_REG_VexI4): Check invalid high registers.
322
ce886ab1
DR		 3232008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
324 Michael Meissner <michael.meissner@amd.com>
325
326 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
327 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 328
19a6653c
AM		 3292008-04-14 Edmar Wienskoski <edmar@freescale.com>
330
331 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
332 accept Power E500MC instructions.
333 (print_ppc_disassembler_options): Document -Me500mc.
334 * ppc-opc.c (DUIS, DUI, T): New.
335 (XRT, XRTRA): Likewise.
336 (E500MC): Likewise.
337 (powerpc_opcodes): Add new Power E500MC instructions.
338
112b7c50
AK		 3392008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
340
341 * s390-dis.c (init_disasm): Evaluate disassembler_options.
342 (print_s390_disassembler_options): New function.
343 * disassemble.c (disassembler_usage): Invoke
344 print_s390_disassembler_options.
345
7ff42648
AK		 3462008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
347
348 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
349 of local variables used for mnemonic parsing: prefix, suffix and
350 number.
351
45a5551e
AK		 3522008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
353
354 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
355 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
356 (s390_crb_extensions): New extensions table.
357 (insertExpandedMnemonic): Handle '$' tag.
358 * s390-opc.txt: Remove conditional jump variants which can now
359 be expanded automatically.
360 Replace '*' tag with '$' in the compare and branch instructions.
361
06c8514a
L		 3622008-04-07 H.J. Lu <hongjiu.lu@intel.com>
363
364 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
365 (PREFIX_VEX_3AXX): Likewis.
366
b122c285
L		 3672008-04-07 H.J. Lu <hongjiu.lu@intel.com>
368
369 * i386-opc.tbl: Remove 4 extra blank lines.
370
594ab6a3
L		 3712008-04-04 H.J. Lu <hongjiu.lu@intel.com>
372
373 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
374 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
375 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
376 * i386-opc.tbl: Likewise.
377
378 * i386-opc.h (CpuCLMUL): Renamed to ...
379 (CpuPCLMUL): This.
380 (CpuFMA): Updated.
381 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
382
383 * i386-init.h: Regenerated.
384
c0f3af97
L		 3852008-04-03 H.J. Lu <hongjiu.lu@intel.com>
386
387 * i386-dis.c (OP_E_register): New.
388 (OP_E_memory): Likewise.
389 (OP_VEX): Likewise.
390 (OP_EX_Vex): Likewise.
391 (OP_EX_VexW): Likewise.
392 (OP_XMM_Vex): Likewise.
393 (OP_XMM_VexW): Likewise.
394 (OP_REG_VexI4): Likewise.
395 (PCLMUL_Fixup): Likewise.
396 (VEXI4_Fixup): Likewise.
397 (VZERO_Fixup): Likewise.
398 (VCMP_Fixup): Likewise.
399 (VPERMIL2_Fixup): Likewise.
400 (rex_original): Likewise.
401 (rex_ignored): Likewise.
402 (Mxmm): Likewise.
403 (XMM): Likewise.
404 (EXxmm): Likewise.
405 (EXxmmq): Likewise.
406 (EXymmq): Likewise.
407 (Vex): Likewise.
408 (Vex128): Likewise.
409 (Vex256): Likewise.
410 (VexI4): Likewise.
411 (EXdVex): Likewise.
412 (EXqVex): Likewise.
413 (EXVexW): Likewise.
414 (EXdVexW): Likewise.
415 (EXqVexW): Likewise.
416 (XMVex): Likewise.
417 (XMVexW): Likewise.
418 (XMVexI4): Likewise.
419 (PCLMUL): Likewise.
420 (VZERO): Likewise.
421 (VCMP): Likewise.
422 (VPERMIL2): Likewise.
423 (xmm_mode): Likewise.
424 (xmmq_mode): Likewise.
425 (ymmq_mode): Likewise.
426 (vex_mode): Likewise.
427 (vex128_mode): Likewise.
428 (vex256_mode): Likewise.
429 (USE_VEX_C4_TABLE): Likewise.
430 (USE_VEX_C5_TABLE): Likewise.
431 (USE_VEX_LEN_TABLE): Likewise.
432 (VEX_C4_TABLE): Likewise.
433 (VEX_C5_TABLE): Likewise.
434 (VEX_LEN_TABLE): Likewise.
435 (REG_VEX_XX): Likewise.
436 (MOD_VEX_XXX): Likewise.
437 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
438 (PREFIX_0F3A44): Likewise.
439 (PREFIX_0F3ADF): Likewise.
440 (PREFIX_VEX_XXX): Likewise.
441 (VEX_OF): Likewise.
442 (VEX_OF38): Likewise.
443 (VEX_OF3A): Likewise.
444 (VEX_LEN_XXX): Likewise.
445 (vex): Likewise.
446 (need_vex): Likewise.
447 (need_vex_reg): Likewise.
448 (vex_i4_done): Likewise.
449 (vex_table): Likewise.
450 (vex_len_table): Likewise.
451 (OP_REG_VexI4): Likewise.
452 (vex_cmp_op): Likewise.
453 (pclmul_op): Likewise.
454 (vpermil2_op): Likewise.
455 (m_mode): Updated.
456 (es_reg): Likewise.
457 (PREFIX_0F38F0): Likewise.
458 (PREFIX_0F3A60): Likewise.
459 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
460 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
461 and PREFIX_VEX_XXX entries.
462 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
463 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
464 PREFIX_0F3ADF.
465 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
466 Add MOD_VEX_XXX entries.
467 (ckprefix): Initialize rex_original and rex_ignored. Store the
468 REX byte in rex_original.
469 (get_valid_dis386): Handle the implicit prefix in VEX prefix
470 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
471 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
472 calling get_valid_dis386. Use rex_original and rex_ignored when
473 printing out REX.
474 (putop): Handle "XY".
475 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
476 ymmq_mode.
477 (OP_E_extended): Updated to use OP_E_register and
478 OP_E_memory.
479 (OP_XMM): Handle VEX.
480 (OP_EX): Likewise.
481 (XMM_Fixup): Likewise.
482 (CMP_Fixup): Use ARRAY_SIZE.
483
484 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
485 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
486 (operand_type_init): Add OPERAND_TYPE_REGYMM and
487 OPERAND_TYPE_VEX_IMM4.
488 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
489 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
490 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
491 VexImmExt and SSE2AVX.
492 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
493
494 * i386-opc.h (CpuAVX): New.
495 (CpuAES): Likewise.
496 (CpuCLMUL): Likewise.
497 (CpuFMA): Likewise.
498 (Vex): Likewise.
499 (Vex256): Likewise.
500 (VexNDS): Likewise.
501 (VexNDD): Likewise.
502 (VexW0): Likewise.
503 (VexW1): Likewise.
504 (Vex0F): Likewise.
505 (Vex0F38): Likewise.
506 (Vex0F3A): Likewise.
507 (Vex3Sources): Likewise.
508 (VexImmExt): Likewise.
509 (SSE2AVX): Likewise.
510 (RegYMM): Likewise.
511 (Ymmword): Likewise.
512 (Vex_Imm4): Likewise.
513 (Implicit1stXmm0): Likewise.
514 (CpuXsave): Updated.
515 (CpuLM): Likewise.
516 (ByteOkIntel): Likewise.
517 (OldGcc): Likewise.
518 (Control): Likewise.
519 (Unspecified): Likewise.
520 (OTMax): Likewise.
521 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
522 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
523 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
524 vex3sources, veximmext and sse2avx.
525 (i386_operand_type): Add regymm, ymmword and vex_imm4.
526
527 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
528
529 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
530
531 * i386-init.h: Regenerated.
532 * i386-tbl.h: Likewise.
533
b21c9cb4
BS		 5342008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
535
536 From Robin Getz <robin.getz@analog.com>
537 * bfin-dis.c (bu32): Typedef.
538 (enum const_forms_t): Add c_uimm32 and c_huimm32.
539 (constant_formats[]): Add uimm32 and huimm16.
540 (fmtconst_val): New.
541 (uimm32): Define.
542 (huimm32): Define.
543 (imm16_val): Define.
544 (luimm16_val): Define.
545 (struct saved_state): Define.
546 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
547 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
548 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
549 (get_allreg): New.
550 (decode_LDIMMhalf_0): Print out the whole register value.
551
ee171c8f
BS		 552 From Jie Zhang <jie.zhang@analog.com>
553 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
554 multiply and multiply-accumulate to data register instruction.
555
086134ec
BS		 556 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
557 c_imm32, c_huimm32e): Define.
558 (constant_formats): Add flags for printing decimal, leading spaces, and
559 exact symbols.
560 (comment, parallel): Add global flags in all disassembly.
561 (fmtconst): Take advantage of new flags, and print default in hex.
562 (fmtconst_val): Likewise.
563 (decode_macfunc): Be consistant with spaces, tabs, comments,
564 capitalization in disassembly, fix minor coding style issues.
565 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
566 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
567 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
568 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
569 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
570 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
571 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
572 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
573 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
574 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
575 _print_insn_bfin, print_insn_bfin): Likewise.
576
58c85be7
RW		 5772008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
578
579 * aclocal.m4: Regenerate.
580 * configure: Likewise.
581 * Makefile.in: Likewise.
582
50e7d84b
AM		 5832008-03-13 Alan Modra <amodra@bigpond.net.au>
584
585 * Makefile.am: Run "make dep-am".
586 * Makefile.in: Regenerate.
587 * configure: Regenerate.
588
de866fcc
AM		 5892008-03-07 Alan Modra <amodra@bigpond.net.au>
590
591 * ppc-opc.c (powerpc_opcodes): Order and format.
592
28dbc079
L		 5932008-03-01 H.J. Lu <hongjiu.lu@intel.com>
594
595 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
596 * i386-tbl.h: Regenerated.
597
849830bd
L		 5982008-02-23 H.J. Lu <hongjiu.lu@intel.com>
599
600 * i386-opc.tbl: Disallow 16-bit near indirect branches for
601 x86-64.
602 * i386-tbl.h: Regenerated.
603
743ddb6b
JB		 6042008-02-21 Jan Beulich <jbeulich@novell.com>
605
606 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
607 and Fword for far indirect jmp. Allow Reg16 and Word for near
608 indirect jmp on x86-64. Disallow Fword for lcall.
609 * i386-tbl.h: Re-generate.
610
796d5313
NC		 6112008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
612
613 * cr16-opc.c (cr16_num_optab): Defined
614
65da13b5
L		 6152008-02-16 H.J. Lu <hongjiu.lu@intel.com>
616
617 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
618 * i386-init.h: Regenerated.
619
0e336180
NC		 6202008-02-14 Nick Clifton <nickc@redhat.com>
621
622 PR binutils/5524
623 * configure.in (SHARED_LIBADD): Select the correct host specific
624 file extension for shared libraries.
625 * configure: Regenerate.
626
b7240065
JB		 6272008-02-13 Jan Beulich <jbeulich@novell.com>
628
629 * i386-opc.h (RegFlat): New.
630 * i386-reg.tbl (flat): Add.
631 * i386-tbl.h: Re-generate.
632
34b772a6
JB		 6332008-02-13 Jan Beulich <jbeulich@novell.com>
634
635 * i386-dis.c (a_mode): New.
636 (cond_jump_mode): Adjust.
637 (Ma): Change to a_mode.
638 (intel_operand_size): Handle a_mode.
639 * i386-opc.tbl: Allow Dword and Qword for bound.
640 * i386-tbl.h: Re-generate.
641
a60de03c
JB		 6422008-02-13 Jan Beulich <jbeulich@novell.com>
643
644 * i386-gen.c (process_i386_registers): Process new fields.
645 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
646 unsigned char. Add dw2_regnum and Dw2Inval.
647 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
648 register names.
649 * i386-tbl.h: Re-generate.
650
f03fe4c1
L		 6512008-02-11 H.J. Lu <hongjiu.lu@intel.com>
652
4b6bc8eb 653 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 654 * i386-init.h: Updated.
655
475a2301
L		 6562008-02-11 H.J. Lu <hongjiu.lu@intel.com>
657
658 * i386-gen.c (cpu_flags): Add CpuXsave.
659
660 * i386-opc.h (CpuXsave): New.
4b6bc8eb 661 (CpuLM): Updated.
475a2301
L		 662 (i386_cpu_flags): Add cpuxsave.
663
664 * i386-dis.c (MOD_0FAE_REG_4): New.
665 (RM_0F01_REG_2): Likewise.
666 (MOD_0FAE_REG_5): Updated.
667 (RM_0F01_REG_3): Likewise.
668 (reg_table): Use MOD_0FAE_REG_4.
669 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
670 for xrstor.
671 (rm_table): Add RM_0F01_REG_2.
672
673 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
674 * i386-init.h: Regenerated.
675 * i386-tbl.h: Likewise.
676
595785c6 6772008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 678
595785c6
JB		 679 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
680 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
681 * i386-tbl.h: Re-generate.
682
bb8541b9
L		 6832008-02-04 H.J. Lu <hongjiu.lu@intel.com>
684
685 PR 5715
686 * configure: Regenerated.
687
57b592a3
AN		 6882008-02-04 Adam Nemet <anemet@caviumnetworks.com>
689
690 * mips-dis.c: Update copyright.
691 (mips_arch_choices): Add Octeon.
692 * mips-opc.c: Update copyright.
693 (IOCT): New macro.
694 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
695
930bb4cf
AM		 6962008-01-29 Alan Modra <amodra@bigpond.net.au>
697
698 * ppc-opc.c: Support optional L form mtmsr.
699
82c18208
L		 7002008-01-24 H.J. Lu <hongjiu.lu@intel.com>
701
702 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
703
599121aa
L		 7042008-01-23 H.J. Lu <hongjiu.lu@intel.com>
705
706 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
707 * i386-init.h: Regenerated.
708
80098f51
TG		 7092008-01-23 Tristan Gingold <gingold@adacore.com>
710
711 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
712 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
713
115c7c25
L		 7142008-01-22 H.J. Lu <hongjiu.lu@intel.com>
715
716 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
717 (cpu_flags): Likewise.
718
719 * i386-opc.h (CpuMMX2): Removed.
720 (CpuSSE): Updated.
721
722 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
723 * i386-init.h: Regenerated.
724 * i386-tbl.h: Likewise.
725
6305a203
L		 7262008-01-22 H.J. Lu <hongjiu.lu@intel.com>
727
728 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
729 CPU_SMX_FLAGS.
730 * i386-init.h: Regenerated.
731
fd07a1c8
L		 7322008-01-15 H.J. Lu <hongjiu.lu@intel.com>
733
734 * i386-opc.tbl: Use Qword on movddup.
735 * i386-tbl.h: Regenerated.
736
321fd21e
L		 7372008-01-15 H.J. Lu <hongjiu.lu@intel.com>
738
739 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
740 * i386-tbl.h: Regenerated.
741
4ee52178
L		 7422008-01-15 H.J. Lu <hongjiu.lu@intel.com>
743
744 * i386-dis.c (Mx): New.
745 (PREFIX_0FC3): Likewise.
746 (PREFIX_0FC7_REG_6): Updated.
747 (dis386_twobyte): Use PREFIX_0FC3.
748 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
749 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
750 movntss.
751
5c07affc
L		 7522008-01-14 H.J. Lu <hongjiu.lu@intel.com>
753
754 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
755 (operand_types): Add Mem.
756
757 * i386-opc.h (IntelSyntax): New.
758 * i386-opc.h (Mem): New.
759 (Byte): Updated.
760 (Opcode_Modifier_Max): Updated.
761 (i386_opcode_modifier): Add intelsyntax.
762 (i386_operand_type): Add mem.
763
764 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
765 instructions.
766
767 * i386-reg.tbl: Add size for accumulator.
768
769 * i386-init.h: Regenerated.
770 * i386-tbl.h: Likewise.
771
0d6a2f58
L		 7722008-01-13 H.J. Lu <hongjiu.lu@intel.com>
773
774 * i386-opc.h (Byte): Fix a typo.
775
7d5e4556
L		 7762008-01-12 H.J. Lu <hongjiu.lu@intel.com>
777
778 PR gas/5534
779 * i386-gen.c (operand_type_init): Add Dword to
780 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
781 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
782 Qword and Xmmword.
783 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
784 Xmmword, Unspecified and Anysize.
785 (set_bitfield): Make Mmword an alias of Qword. Make Oword
786 an alias of Xmmword.
787
788 * i386-opc.h (CheckSize): Removed.
789 (Byte): Updated.
790 (Word): Likewise.
791 (Dword): Likewise.
792 (Qword): Likewise.
793 (Xmmword): Likewise.
794 (FWait): Updated.
795 (OTMax): Likewise.
796 (i386_opcode_modifier): Remove checksize, byte, word, dword,
797 qword and xmmword.
798 (Fword): New.
799 (TBYTE): Likewise.
800 (Unspecified): Likewise.
801 (Anysize): Likewise.
802 (i386_operand_type): Add byte, word, dword, fword, qword,
803 tbyte xmmword, unspecified and anysize.
804
805 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
806 Tbyte, Xmmword, Unspecified and Anysize.
807
808 * i386-reg.tbl: Add size for accumulator.
809
810 * i386-init.h: Regenerated.
811 * i386-tbl.h: Likewise.
812
b5b1fc4f
L		 8132008-01-10 H.J. Lu <hongjiu.lu@intel.com>
814
815 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
816 (REG_0F18): Updated.
817 (reg_table): Updated.
818 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
819 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
820
50e8458f
L		 8212008-01-08 H.J. Lu <hongjiu.lu@intel.com>
822
823 * i386-gen.c (set_bitfield): Use fail () on error.
824
3d4d5afa
L		 8252008-01-08 H.J. Lu <hongjiu.lu@intel.com>
826
827 * i386-gen.c (lineno): New.
828 (filename): Likewise.
829 (set_bitfield): Report filename and line numer on error.
830 (process_i386_opcodes): Set filename and update lineno.
831 (process_i386_registers): Likewise.
832
e1d4d893
L		 8332008-01-05 H.J. Lu <hongjiu.lu@intel.com>
834
835 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
836 ATTSyntax.
837
838 * i386-opc.h (IntelMnemonic): Renamed to ..
839 (ATTSyntax): This
840 (Opcode_Modifier_Max): Updated.
841 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
842 and intelsyntax.
843
8944f3c2 844 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 845 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
846 * i386-tbl.h: Regenerated.
847
6f143e4d
L		 8482008-01-04 H.J. Lu <hongjiu.lu@intel.com>
849
850 * i386-gen.c: Update copyright to 2008.
851 * i386-opc.h: Likewise.
852 * i386-opc.tbl: Likewise.
853
854 * i386-init.h: Regenerated.
855 * i386-tbl.h: Likewise.
856
c6add537
L		 8572008-01-04 H.J. Lu <hongjiu.lu@intel.com>
858
859 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
860 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
861 * i386-tbl.h: Regenerated.
862
3629bb00
L		 8632008-01-03 H.J. Lu <hongjiu.lu@intel.com>
864
865 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
866 CpuSSE4_2_Or_ABM.
867 (cpu_flags): Likewise.
868
869 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
870 (CpuSSE4_2_Or_ABM): Likewise.
871 (CpuLM): Updated.
872 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
873
874 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
875 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
876 and CpuPadLock, respectively.
877 * i386-init.h: Regenerated.
878 * i386-tbl.h: Likewise.
879
24995bd6
L		 8802008-01-03 H.J. Lu <hongjiu.lu@intel.com>
881
882 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
883
884 * i386-opc.h (No_xSuf): Removed.
885 (CheckSize): Updated.
886
887 * i386-tbl.h: Regenerated.
888
e0329a22
L		 8892008-01-02 H.J. Lu <hongjiu.lu@intel.com>
890
891 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
892 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
893 CPU_SSE5_FLAGS.
894 (cpu_flags): Add CpuSSE4_2_Or_ABM.
895
896 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
897 (CpuLM): Updated.
898 (i386_cpu_flags): Add cpusse4_2_or_abm.
899
900 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
901 CpuABM|CpuSSE4_2 on popcnt.
902 * i386-init.h: Regenerated.
903 * i386-tbl.h: Likewise.
904
f2a9c676
L		 9052008-01-02 H.J. Lu <hongjiu.lu@intel.com>
906
907 * i386-opc.h: Update comments.
908
d978b5be
L		 9092008-01-02 H.J. Lu <hongjiu.lu@intel.com>
910
911 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
912 * i386-opc.h: Likewise.
913 * i386-opc.tbl: Likewise.
914
582d5edd
L		 9152008-01-02 H.J. Lu <hongjiu.lu@intel.com>
916
917 PR gas/5534
918 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
919 Byte, Word, Dword, QWord and Xmmword.
920
921 * i386-opc.h (No_xSuf): New.
922 (CheckSize): Likewise.
923 (Byte): Likewise.
924 (Word): Likewise.
925 (Dword): Likewise.
926 (QWord): Likewise.
927 (Xmmword): Likewise.
928 (FWait): Updated.
929 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
930 Dword, QWord and Xmmword.
931
932 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
933 used.
934 * i386-tbl.h: Regenerated.
935
3fe15143
MK		 9362008-01-02 Mark Kettenis <kettenis@gnu.org>
937
938 * m88k-dis.c (instructions): Fix fcvt.* instructions.
939 From Miod Vallat.
940
6c7ac64e 941For older changes see ChangeLog-2007
252b5132
RH		 942\f
943Local Variables:
2f6d2f85
NC		 944mode: change-log
945left-margin: 8
946fill-column: 74
252b5132
RH		 947version-control: never
948End:
GDB Binutils - Deliverables
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