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[gdb/testsuite] Remove dependence on tcl_unknown
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
efe30057
L		 12020-06-14 H.J. Lu <hongjiu.lu@intel.com>
2
3 PR gas/26115
4 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
5 * i386-opc.tbl: Likewise.
6 * i386-tbl.h: Regenerated.
7
d8af286f
NC		 82020-06-12 Nelson Chu <nelson.chu@sifive.com>
9
10 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
11
14962256
AC		 122020-06-11 Alex Coplan <alex.coplan@arm.com>
13
14 * aarch64-opc.c (SYSREG): New macro for describing system registers.
15 (SR_CORE): Likewise.
16 (SR_FEAT): Likewise.
17 (SR_RNG): Likewise.
18 (SR_V8_1): Likewise.
19 (SR_V8_2): Likewise.
20 (SR_V8_3): Likewise.
21 (SR_V8_4): Likewise.
22 (SR_PAN): Likewise.
23 (SR_RAS): Likewise.
24 (SR_SSBS): Likewise.
25 (SR_SVE): Likewise.
26 (SR_ID_PFR2): Likewise.
27 (SR_PROFILE): Likewise.
28 (SR_MEMTAG): Likewise.
29 (SR_SCXTNUM): Likewise.
30 (aarch64_sys_regs): Refactor to store feature information in the table.
31 (aarch64_sys_reg_supported_p): Collapse logic for system registers
32 that now describe their own features.
33 (aarch64_pstatefield_supported_p): Likewise.
34
f9630fa6
L		 352020-06-09 H.J. Lu <hongjiu.lu@intel.com>
36
37 * i386-dis.c (prefix_table): Fix a typo in comments.
38
73239888
JB		 392020-06-09 Jan Beulich <jbeulich@suse.com>
40
41 * i386-dis.c (rex_ignored): Delete.
42 (ckprefix): Drop rex_ignored initialization.
43 (get_valid_dis386): Drop setting of rex_ignored.
44 (print_insn): Drop checking of rex_ignored. Don't record data
45 size prefix as used with VEX-and-alike encodings.
46
18897deb
JB		 472020-06-09 Jan Beulich <jbeulich@suse.com>
48
49 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
50 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
51 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
52 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
53 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
54 VEX_0F12, and VEX_0F16.
55 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
56 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
57 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
58 from movlps and movhlps. New MOD_0F12_PREFIX_2,
59 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
60 MOD_VEX_0F16_PREFIX_2 entries.
61
97e6786a
JB		 622020-06-09 Jan Beulich <jbeulich@suse.com>
63
64 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
65 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
66 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
67 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
68 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
69 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
70 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
71 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
72 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
73 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
74 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
75 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
76 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
77 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
78 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
79 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
80 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
81 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
82 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
83 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
84 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
85 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
86 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
87 EVEX_W_0FC6_P_2): Delete.
88 (print_insn): Add EVEX.W vs embedded prefix consistency check
89 to prefix validation.
90 * i386-dis-evex.h (evex_table): Don't further descend for
91 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
92 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
93 and 0F2B.
94 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
95 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
96 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
97 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
98 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
99 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
100 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
101 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
102 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
103 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
104 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
105 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
106 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
107 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
108 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
109 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
110 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
111 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
112 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
113 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
114 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
115 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
116 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
117 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
118 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
119 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
120 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
121
bf926894
JB		 1222020-06-09 Jan Beulich <jbeulich@suse.com>
123
124 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
125 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
126 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
127 vmovmskpX.
128 (print_insn): Drop pointless check against bad_opcode. Split
129 prefix validation into legacy and VEX-and-alike parts.
130 (putop): Re-work 'X' macro handling.
131
a5aaedb9
JB		 1322020-06-09 Jan Beulich <jbeulich@suse.com>
133
134 * i386-dis.c (MOD_0F51): Rename to ...
135 (MOD_0F50): ... this.
136
26417f19
AC		 1372020-06-08 Alex Coplan <alex.coplan@arm.com>
138
139 * arm-dis.c (arm_opcodes): Add dfb.
140 (thumb32_opcodes): Add dfb.
141
8a6fb3f9
JB		 1422020-06-08 Jan Beulich <jbeulich@suse.com>
143
144 * i386-opc.h (reg_entry): Const-qualify reg_name field.
145
1424c35d
AM		 1462020-06-06 Alan Modra <amodra@gmail.com>
147
148 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
149
d3d1cc7b
AM		 1502020-06-05 Alan Modra <amodra@gmail.com>
151
152 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
153 size is large enough.
154
d8740be1
JM		 1552020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
156
157 * disassemble.c (disassemble_init_for_target): Set endian_code for
158 bpf targets.
159 * bpf-desc.c: Regenerate.
160 * bpf-opc.c: Likewise.
161 * bpf-dis.c: Likewise.
162
e9bffec9
JM		 1632020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
164
165 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
166 (cgen_put_insn_value): Likewise.
167 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
168 * cgen-dis.in (print_insn): Likewise.
169 * cgen-ibld.in (insert_1): Likewise.
170 (insert_1): Likewise.
171 (insert_insn_normal): Likewise.
172 (extract_1): Likewise.
173 * bpf-dis.c: Regenerate.
174 * bpf-ibld.c: Likewise.
175 * bpf-ibld.c: Likewise.
176 * cgen-dis.in: Likewise.
177 * cgen-ibld.in: Likewise.
178 * cgen-opc.c: Likewise.
179 * epiphany-dis.c: Likewise.
180 * epiphany-ibld.c: Likewise.
181 * fr30-dis.c: Likewise.
182 * fr30-ibld.c: Likewise.
183 * frv-dis.c: Likewise.
184 * frv-ibld.c: Likewise.
185 * ip2k-dis.c: Likewise.
186 * ip2k-ibld.c: Likewise.
187 * iq2000-dis.c: Likewise.
188 * iq2000-ibld.c: Likewise.
189 * lm32-dis.c: Likewise.
190 * lm32-ibld.c: Likewise.
191 * m32c-dis.c: Likewise.
192 * m32c-ibld.c: Likewise.
193 * m32r-dis.c: Likewise.
194 * m32r-ibld.c: Likewise.
195 * mep-dis.c: Likewise.
196 * mep-ibld.c: Likewise.
197 * mt-dis.c: Likewise.
198 * mt-ibld.c: Likewise.
199 * or1k-dis.c: Likewise.
200 * or1k-ibld.c: Likewise.
201 * xc16x-dis.c: Likewise.
202 * xc16x-ibld.c: Likewise.
203 * xstormy16-dis.c: Likewise.
204 * xstormy16-ibld.c: Likewise.
205
b3db6d07
JM		 2062020-06-04 Jose E. Marchesi <jemarch@gnu.org>
207
208 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
209 (print_insn_): Handle instruction endian.
210 * bpf-dis.c: Regenerate.
211 * bpf-desc.c: Regenerate.
212 * epiphany-dis.c: Likewise.
213 * epiphany-desc.c: Likewise.
214 * fr30-dis.c: Likewise.
215 * fr30-desc.c: Likewise.
216 * frv-dis.c: Likewise.
217 * frv-desc.c: Likewise.
218 * ip2k-dis.c: Likewise.
219 * ip2k-desc.c: Likewise.
220 * iq2000-dis.c: Likewise.
221 * iq2000-desc.c: Likewise.
222 * lm32-dis.c: Likewise.
223 * lm32-desc.c: Likewise.
224 * m32c-dis.c: Likewise.
225 * m32c-desc.c: Likewise.
226 * m32r-dis.c: Likewise.
227 * m32r-desc.c: Likewise.
228 * mep-dis.c: Likewise.
229 * mep-desc.c: Likewise.
230 * mt-dis.c: Likewise.
231 * mt-desc.c: Likewise.
232 * or1k-dis.c: Likewise.
233 * or1k-desc.c: Likewise.
234 * xc16x-dis.c: Likewise.
235 * xc16x-desc.c: Likewise.
236 * xstormy16-dis.c: Likewise.
237 * xstormy16-desc.c: Likewise.
238
4ee4189f
NC		 2392020-06-03 Nick Clifton <nickc@redhat.com>
240
241 * po/sr.po: Updated Serbian translation.
242
44730156
NC		 2432020-06-03 Nelson Chu <nelson.chu@sifive.com>
244
245 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
246 (riscv_get_priv_spec_class): Likewise.
247
3c3d0376
AM		 2482020-06-01 Alan Modra <amodra@gmail.com>
249
250 * bpf-desc.c: Regenerate.
251
78c1c354
JM		 2522020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
253 David Faust <david.faust@oracle.com>
254
255 * bpf-desc.c: Regenerate.
256 * bpf-opc.h: Likewise.
257 * bpf-opc.c: Likewise.
258 * bpf-dis.c: Likewise.
259
efcf5fb5
AM		 2602020-05-28 Alan Modra <amodra@gmail.com>
261
262 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
263 values.
264
ab382d64
AM		 2652020-05-28 Alan Modra <amodra@gmail.com>
266
267 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
268 immediates.
269 (print_insn_ns32k): Revert last change.
270
151f5de4
NC		 2712020-05-28 Nick Clifton <nickc@redhat.com>
272
273 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
274 static.
275
25e1eca8
SL		 2762020-05-26 Sandra Loosemore <sandra@codesourcery.com>
277
278 Fix extraction of signed constants in nios2 disassembler (again).
279
280 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
281 extractions of signed fields.
282
57b17940
SSF		 2832020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
284
285 * s390-opc.txt: Relocate vector load/store instructions with
286 additional alignment parameter and change architecture level
287 constraint from z14 to z13.
288
d96bf37b
AM		 2892020-05-21 Alan Modra <amodra@gmail.com>
290
291 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
292 * sparc-dis.c: Likewise.
293 * tic4x-dis.c: Likewise.
294 * xtensa-dis.c: Likewise.
295 * bpf-desc.c: Regenerate.
296 * epiphany-desc.c: Regenerate.
297 * fr30-desc.c: Regenerate.
298 * frv-desc.c: Regenerate.
299 * ip2k-desc.c: Regenerate.
300 * iq2000-desc.c: Regenerate.
301 * lm32-desc.c: Regenerate.
302 * m32c-desc.c: Regenerate.
303 * m32r-desc.c: Regenerate.
304 * mep-asm.c: Regenerate.
305 * mep-desc.c: Regenerate.
306 * mt-desc.c: Regenerate.
307 * or1k-desc.c: Regenerate.
308 * xc16x-desc.c: Regenerate.
309 * xstormy16-desc.c: Regenerate.
310
8f595e9b
NC		 3112020-05-20 Nelson Chu <nelson.chu@sifive.com>
312
313 * riscv-opc.c (riscv_ext_version_table): The table used to store
314 all information about the supported spec and the corresponding ISA
315 versions. Currently, only Zicsr is supported to verify the
316 correctness of Z sub extension settings. Others will be supported
317 in the future patches.
318 (struct isa_spec_t, isa_specs): List for all supported ISA spec
319 classes and the corresponding strings.
320 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
321 spec class by giving a ISA spec string.
322 * riscv-opc.c (struct priv_spec_t): New structure.
323 (struct priv_spec_t priv_specs): List for all supported privilege spec
324 classes and the corresponding strings.
325 (riscv_get_priv_spec_class): New function. Get the corresponding
326 privilege spec class by giving a spec string.
327 (riscv_get_priv_spec_name): New function. Get the corresponding
328 privilege spec string by giving a CSR version class.
329 * riscv-dis.c: Updated since DECLARE_CSR is changed.
330 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
331 according to the chosen version. Build a hash table riscv_csr_hash to
332 store the valid CSR for the chosen pirv verison. Dump the direct
333 CSR address rather than it's name if it is invalid.
334 (parse_riscv_dis_option_without_args): New function. Parse the options
335 without arguments.
336 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
337 parse the options without arguments first, and then handle the options
338 with arguments. Add the new option -Mpriv-spec, which has argument.
339 * riscv-dis.c (print_riscv_disassembler_options): Add description
340 about the new OBJDUMP option.
341
3d205eb4
PB		 3422020-05-19 Peter Bergner <bergner@linux.ibm.com>
343
344 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
345 WC values on POWER10 sync, dcbf and wait instructions.
346 (insert_pl, extract_pl): New functions.
347 (L2OPT, LS, WC): Use insert_ls and extract_ls.
348 (LS3): New , 3-bit L for sync.
349 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
350 (SC2, PL): New, 2-bit SC and PL for sync and wait.
351 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
352 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
353 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
354 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
355 <wait>: Enable PL operand on POWER10.
356 <dcbf>: Enable L3OPT operand on POWER10.
357 <sync>: Enable SC2 operand on POWER10.
358
a501eb44
SH		 3592020-05-19 Stafford Horne <shorne@gmail.com>
360
361 PR 25184
362 * or1k-asm.c: Regenerate.
363 * or1k-desc.c: Regenerate.
364 * or1k-desc.h: Regenerate.
365 * or1k-dis.c: Regenerate.
366 * or1k-ibld.c: Regenerate.
367 * or1k-opc.c: Regenerate.
368 * or1k-opc.h: Regenerate.
369 * or1k-opinst.c: Regenerate.
370
3b646889
AM		 3712020-05-11 Alan Modra <amodra@gmail.com>
372
373 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
374 xsmaxcqp, xsmincqp.
375
9cc4ce88
AM		 3762020-05-11 Alan Modra <amodra@gmail.com>
377
378 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
379 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
380
5d57bc3f
AM		 3812020-05-11 Alan Modra <amodra@gmail.com>
382
383 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
384
66ef5847
AM		 3852020-05-11 Alan Modra <amodra@gmail.com>
386
387 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
388 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
389
4f3e9537
PB		 3902020-05-11 Peter Bergner <bergner@linux.ibm.com>
391
392 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
393 mnemonics.
394
ec40e91c
AM		 3952020-05-11 Alan Modra <amodra@gmail.com>
396
397 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
398 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
399 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
400 (prefix_opcodes): Add xxeval.
401
d7e97a76
AM		 4022020-05-11 Alan Modra <amodra@gmail.com>
403
404 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
405 xxgenpcvwm, xxgenpcvdm.
406
fdefed7c
AM		 4072020-05-11 Alan Modra <amodra@gmail.com>
408
409 * ppc-opc.c (MP, VXVAM_MASK): Define.
410 (VXVAPS_MASK): Use VXVA_MASK.
411 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
412 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
413 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
414 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
415
aa3c112f
AM		 4162020-05-11 Alan Modra <amodra@gmail.com>
417 Peter Bergner <bergner@linux.ibm.com>
418
419 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
420 New functions.
421 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
422 YMSK2, XA6a, XA6ap, XB6a entries.
423 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
424 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
425 (PPCVSX4): Define.
426 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
427 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
428 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
429 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
430 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
431 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
432 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
433 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
434 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
435 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
436 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
437 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
438 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
439 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
440
6edbfd3b
AM		 4412020-05-11 Alan Modra <amodra@gmail.com>
442
443 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
444 (insert_xts, extract_xts): New functions.
445 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
446 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
447 (VXRC_MASK, VXSH_MASK): Define.
448 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
449 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
450 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
451 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
452 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
453 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
454 xxblendvh, xxblendvw, xxblendvd, xxpermx.
455
c7d7aea2
AM		 4562020-05-11 Alan Modra <amodra@gmail.com>
457
458 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
459 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
460 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
461 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
462 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
463
94ba9882
AM		 4642020-05-11 Alan Modra <amodra@gmail.com>
465
466 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
467 (XTP, DQXP, DQXP_MASK): Define.
468 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
469 (prefix_opcodes): Add plxvp and pstxvp.
470
f4791f1a
AM		 4712020-05-11 Alan Modra <amodra@gmail.com>
472
473 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
474 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
475 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
476
3ff0a5ba
PB		 4772020-05-11 Peter Bergner <bergner@linux.ibm.com>
478
479 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
480
afef4fe9
PB		 4812020-05-11 Peter Bergner <bergner@linux.ibm.com>
482
483 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
484 (L1OPT): Define.
485 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
486
1224c05d
PB		 4872020-05-11 Peter Bergner <bergner@linux.ibm.com>
488
489 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
490
6bbb0c05
AM		 4912020-05-11 Alan Modra <amodra@gmail.com>
492
493 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
494
7c1f4227
AM		 4952020-05-11 Alan Modra <amodra@gmail.com>
496
497 * ppc-dis.c (ppc_opts): Add "power10" entry.
498 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
499 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
500
73199c2b
NC		 5012020-05-11 Nick Clifton <nickc@redhat.com>
502
503 * po/fr.po: Updated French translation.
504
09c1e68a
AC		 5052020-04-30 Alex Coplan <alex.coplan@arm.com>
506
507 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
508 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
509 (operand_general_constraint_met_p): validate
510 AARCH64_OPND_UNDEFINED.
511 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
512 for FLD_imm16_2.
513 * aarch64-asm-2.c: Regenerated.
514 * aarch64-dis-2.c: Regenerated.
515 * aarch64-opc-2.c: Regenerated.
516
9654d51a
NC		 5172020-04-29 Nick Clifton <nickc@redhat.com>
518
519 PR 22699
520 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
521 and SETRC insns.
522
c2e71e57
NC		 5232020-04-29 Nick Clifton <nickc@redhat.com>
524
525 * po/sv.po: Updated Swedish translation.
526
5c936ef5
NC		 5272020-04-29 Nick Clifton <nickc@redhat.com>
528
529 PR 22699
530 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
531 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
532 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
533 IMM0_8U case.
534
bb2a1453
AS		 5352020-04-21 Andreas Schwab <schwab@linux-m68k.org>
536
537 PR 25848
538 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
539 cmpi only on m68020up and cpu32.
540
c2e5c986
SD		 5412020-04-20 Sudakshina Das <sudi.das@arm.com>
542
543 * aarch64-asm.c (aarch64_ins_none): New.
544 * aarch64-asm.h (ins_none): New declaration.
545 * aarch64-dis.c (aarch64_ext_none): New.
546 * aarch64-dis.h (ext_none): New declaration.
547 * aarch64-opc.c (aarch64_print_operand): Update case for
548 AARCH64_OPND_BARRIER_PSB.
549 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
550 (AARCH64_OPERANDS): Update inserter/extracter for
551 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
552 * aarch64-asm-2.c: Regenerated.
553 * aarch64-dis-2.c: Regenerated.
554 * aarch64-opc-2.c: Regenerated.
555
8a6e1d1d
SD		 5562020-04-20 Sudakshina Das <sudi.das@arm.com>
557
558 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
559 (aarch64_feature_ras, RAS): Likewise.
560 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
561 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
562 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
563 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
564 * aarch64-asm-2.c: Regenerated.
565 * aarch64-dis-2.c: Regenerated.
566 * aarch64-opc-2.c: Regenerated.
567
e409955d
FS		 5682020-04-17 Fredrik Strupe <fredrik@strupe.net>
569
570 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
571 (print_insn_neon): Support disassembly of conditional
572 instructions.
573
c54a9b56
DF		 5742020-02-16 David Faust <david.faust@oracle.com>
575
576 * bpf-desc.c: Regenerate.
577 * bpf-desc.h: Likewise.
578 * bpf-opc.c: Regenerate.
579 * bpf-opc.h: Likewise.
580
bb651e8b
CL		 5812020-04-07 Lili Cui <lili.cui@intel.com>
582
583 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
584 (prefix_table): New instructions (see prefixes above).
585 (rm_table): Likewise
586 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
587 CPU_ANY_TSXLDTRK_FLAGS.
588 (cpu_flags): Add CpuTSXLDTRK.
589 * i386-opc.h (enum): Add CpuTSXLDTRK.
590 (i386_cpu_flags): Add cputsxldtrk.
591 * i386-opc.tbl: Add XSUSPLDTRK insns.
592 * i386-init.h: Regenerate.
593 * i386-tbl.h: Likewise.
594
4b27d27c
L		 5952020-04-02 Lili Cui <lili.cui@intel.com>
596
597 * i386-dis.c (prefix_table): New instructions serialize.
598 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
599 CPU_ANY_SERIALIZE_FLAGS.
600 (cpu_flags): Add CpuSERIALIZE.
601 * i386-opc.h (enum): Add CpuSERIALIZE.
602 (i386_cpu_flags): Add cpuserialize.
603 * i386-opc.tbl: Add SERIALIZE insns.
604 * i386-init.h: Regenerate.
605 * i386-tbl.h: Likewise.
606
832a5807
AM		 6072020-03-26 Alan Modra <amodra@gmail.com>
608
609 * disassemble.h (opcodes_assert): Declare.
610 (OPCODES_ASSERT): Define.
611 * disassemble.c: Don't include assert.h. Include opintl.h.
612 (opcodes_assert): New function.
613 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
614 (bfd_h8_disassemble): Reduce size of data array. Correctly
615 calculate maxlen. Omit insn decoding when insn length exceeds
616 maxlen. Exit from nibble loop when looking for E, before
617 accessing next data byte. Move processing of E outside loop.
618 Replace tests of maxlen in loop with assertions.
619
4c4addbe
AM		 6202020-03-26 Alan Modra <amodra@gmail.com>
621
622 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
623
a18cd0ca
AM		 6242020-03-25 Alan Modra <amodra@gmail.com>
625
626 * z80-dis.c (suffix): Init mybuf.
627
57cb32b3
AM		 6282020-03-22 Alan Modra <amodra@gmail.com>
629
630 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
631 successflly read from section.
632
beea5cc1
AM		 6332020-03-22 Alan Modra <amodra@gmail.com>
634
635 * arc-dis.c (find_format): Use ISO C string concatenation rather
636 than line continuation within a string. Don't access needs_limm
637 before testing opcode != NULL.
638
03704c77
AM		 6392020-03-22 Alan Modra <amodra@gmail.com>
640
641 * ns32k-dis.c (print_insn_arg): Update comment.
642 (print_insn_ns32k): Reduce size of index_offset array, and
643 initialize, passing -1 to print_insn_arg for args that are not
644 an index. Don't exit arg loop early. Abort on bad arg number.
645
d1023b5d
AM		 6462020-03-22 Alan Modra <amodra@gmail.com>
647
648 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
649 * s12z-opc.c: Formatting.
650 (operands_f): Return an int.
651 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
652 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
653 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
654 (exg_sex_discrim): Likewise.
655 (create_immediate_operand, create_bitfield_operand),
656 (create_register_operand_with_size, create_register_all_operand),
657 (create_register_all16_operand, create_simple_memory_operand),
658 (create_memory_operand, create_memory_auto_operand): Don't
659 segfault on malloc failure.
660 (z_ext24_decode): Return an int status, negative on fail, zero
661 on success.
662 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
663 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
664 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
665 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
666 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
667 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
668 (loop_primitive_decode, shift_decode, psh_pul_decode),
669 (bit_field_decode): Similarly.
670 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
671 to return value, update callers.
672 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
673 Don't segfault on NULL operand.
674 (decode_operation): Return OP_INVALID on first fail.
675 (decode_s12z): Check all reads, returning -1 on fail.
676
340f3ac8
AM		 6772020-03-20 Alan Modra <amodra@gmail.com>
678
679 * metag-dis.c (print_insn_metag): Don't ignore status from
680 read_memory_func.
681
fe90ae8a
AM		 6822020-03-20 Alan Modra <amodra@gmail.com>
683
684 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
685 Initialize parts of buffer not written when handling a possible
686 2-byte insn at end of section. Don't attempt decoding of such
687 an insn by the 4-byte machinery.
688
833d919c
AM		 6892020-03-20 Alan Modra <amodra@gmail.com>
690
691 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
692 partially filled buffer. Prevent lookup of 4-byte insns when
693 only VLE 2-byte insns are possible due to section size. Print
694 ".word" rather than ".long" for 2-byte leftovers.
695
327ef784
NC		 6962020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
697
698 PR 25641
699 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
700
1673df32
JB		 7012020-03-13 Jan Beulich <jbeulich@suse.com>
702
703 * i386-dis.c (X86_64_0D): Rename to ...
704 (X86_64_0E): ... this.
705
384f3689
L		 7062020-03-09 H.J. Lu <hongjiu.lu@intel.com>
707
708 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
709 * Makefile.in: Regenerated.
710
865e2027
JB		 7112020-03-09 Jan Beulich <jbeulich@suse.com>
712
713 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
714 3-operand pseudos.
715 * i386-tbl.h: Re-generate.
716
2f13234b
JB		 7172020-03-09 Jan Beulich <jbeulich@suse.com>
718
719 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
720 vprot*, vpsha*, and vpshl*.
721 * i386-tbl.h: Re-generate.
722
3fabc179
JB		 7232020-03-09 Jan Beulich <jbeulich@suse.com>
724
725 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
726 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
727 * i386-tbl.h: Re-generate.
728
3677e4c1
JB		 7292020-03-09 Jan Beulich <jbeulich@suse.com>
730
731 * i386-gen.c (set_bitfield): Ignore zero-length field names.
732 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
733 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
734 * i386-tbl.h: Re-generate.
735
4c4898e8
JB		 7362020-03-09 Jan Beulich <jbeulich@suse.com>
737
738 * i386-gen.c (struct template_arg, struct template_instance,
739 struct template_param, struct template, templates,
740 parse_template, expand_templates): New.
741 (process_i386_opcodes): Various local variables moved to
742 expand_templates. Call parse_template and expand_templates.
743 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
744 * i386-tbl.h: Re-generate.
745
bc49bfd8
JB		 7462020-03-06 Jan Beulich <jbeulich@suse.com>
747
748 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
749 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
750 register and memory source templates. Replace VexW= by VexW*
751 where applicable.
752 * i386-tbl.h: Re-generate.
753
4873e243
JB		 7542020-03-06 Jan Beulich <jbeulich@suse.com>
755
756 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
757 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
758 * i386-tbl.h: Re-generate.
759
672a349b
JB		 7602020-03-06 Jan Beulich <jbeulich@suse.com>
761
762 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
763 * i386-tbl.h: Re-generate.
764
4ed21b58
JB		 7652020-03-06 Jan Beulich <jbeulich@suse.com>
766
767 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
768 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
769 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
770 VexW0 on SSE2AVX variants.
771 (vmovq): Drop NoRex64 from XMM/XMM variants.
772 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
773 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
774 applicable use VexW0.
775 * i386-tbl.h: Re-generate.
776
643bb870
JB		 7772020-03-06 Jan Beulich <jbeulich@suse.com>
778
779 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
780 * i386-opc.h (Rex64): Delete.
781 (struct i386_opcode_modifier): Remove rex64 field.
782 * i386-opc.tbl (crc32): Drop Rex64.
783 Replace Rex64 with Size64 everywhere else.
784 * i386-tbl.h: Re-generate.
785
a23b33b3
JB		 7862020-03-06 Jan Beulich <jbeulich@suse.com>
787
788 * i386-dis.c (OP_E_memory): Exclude recording of used address
789 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
790 addressed memory operands for MPX insns.
791
a0497384
JB		 7922020-03-06 Jan Beulich <jbeulich@suse.com>
793
794 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
795 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
796 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
797 (ptwrite): Split into non-64-bit and 64-bit forms.
798 * i386-tbl.h: Re-generate.
799
b630c145
JB		 8002020-03-06 Jan Beulich <jbeulich@suse.com>
801
802 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
803 template.
804 * i386-tbl.h: Re-generate.
805
a847e322
JB		 8062020-03-04 Jan Beulich <jbeulich@suse.com>
807
808 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
809 (prefix_table): Move vmmcall here. Add vmgexit.
810 (rm_table): Replace vmmcall entry by prefix_table[] escape.
811 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
812 (cpu_flags): Add CpuSEV_ES entry.
813 * i386-opc.h (CpuSEV_ES): New.
814 (union i386_cpu_flags): Add cpusev_es field.
815 * i386-opc.tbl (vmgexit): New.
816 * i386-init.h, i386-tbl.h: Re-generate.
817
3cd7f3e3
L		 8182020-03-03 H.J. Lu <hongjiu.lu@intel.com>
819
820 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
821 with MnemonicSize.
822 * i386-opc.h (IGNORESIZE): New.
823 (DEFAULTSIZE): Likewise.
824 (IgnoreSize): Removed.
825 (DefaultSize): Likewise.
826 (MnemonicSize): New.
827 (i386_opcode_modifier): Replace ignoresize/defaultsize with
828 mnemonicsize.
829 * i386-opc.tbl (IgnoreSize): New.
830 (DefaultSize): Likewise.
831 * i386-tbl.h: Regenerated.
832
b8ba1385
SB		 8332020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
834
835 PR 25627
836 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
837 instructions.
838
10d97a0f
L		 8392020-03-03 H.J. Lu <hongjiu.lu@intel.com>
840
841 PR gas/25622
842 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
843 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
844 * i386-tbl.h: Regenerated.
845
dc1e8a47
AM		 8462020-02-26 Alan Modra <amodra@gmail.com>
847
848 * aarch64-asm.c: Indent labels correctly.
849 * aarch64-dis.c: Likewise.
850 * aarch64-gen.c: Likewise.
851 * aarch64-opc.c: Likewise.
852 * alpha-dis.c: Likewise.
853 * i386-dis.c: Likewise.
854 * nds32-asm.c: Likewise.
855 * nfp-dis.c: Likewise.
856 * visium-dis.c: Likewise.
857
265b4673
CZ		 8582020-02-25 Claudiu Zissulescu <claziss@gmail.com>
859
860 * arc-regs.h (int_vector_base): Make it available for all ARC
861 CPUs.
862
bd0cf5a6
NC		 8632020-02-20 Nelson Chu <nelson.chu@sifive.com>
864
865 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
866 changed.
867
fa164239
JW		 8682020-02-19 Nelson Chu <nelson.chu@sifive.com>
869
870 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
871 c.mv/c.li if rs1 is zero.
872
272a84b1
L		 8732020-02-17 H.J. Lu <hongjiu.lu@intel.com>
874
875 * i386-gen.c (cpu_flag_init): Replace CpuABM with
876 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
877 CPU_POPCNT_FLAGS.
878 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
879 * i386-opc.h (CpuABM): Removed.
880 (CpuPOPCNT): New.
881 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
882 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
883 popcnt. Remove CpuABM from lzcnt.
884 * i386-init.h: Regenerated.
885 * i386-tbl.h: Likewise.
886
1f730c46
JB		 8872020-02-17 Jan Beulich <jbeulich@suse.com>
888
889 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
890 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
891 VexW1 instead of open-coding them.
892 * i386-tbl.h: Re-generate.
893
c8f8eebc
JB		 8942020-02-17 Jan Beulich <jbeulich@suse.com>
895
896 * i386-opc.tbl (AddrPrefixOpReg): Define.
897 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
898 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
899 templates. Drop NoRex64.
900 * i386-tbl.h: Re-generate.
901
b9915cbc
JB		 9022020-02-17 Jan Beulich <jbeulich@suse.com>
903
904 PR gas/6518
905 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
906 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
907 into Intel syntax instance (with Unpsecified) and AT&T one
908 (without).
909 (vcvtneps2bf16): Likewise, along with folding the two so far
910 separate ones.
911 * i386-tbl.h: Re-generate.
912
ce504911
L		 9132020-02-16 H.J. Lu <hongjiu.lu@intel.com>
914
915 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
916 CPU_ANY_SSE4A_FLAGS.
917
dabec65d
AM		 9182020-02-17 Alan Modra <amodra@gmail.com>
919
920 * i386-gen.c (cpu_flag_init): Correct last change.
921
af5c13b0
L		 9222020-02-16 H.J. Lu <hongjiu.lu@intel.com>
923
924 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
925 CPU_ANY_SSE4_FLAGS.
926
6867aac0
L		 9272020-02-14 H.J. Lu <hongjiu.lu@intel.com>
928
929 * i386-opc.tbl (movsx): Remove Intel syntax comments.
930 (movzx): Likewise.
931
65fca059
JB		 9322020-02-14 Jan Beulich <jbeulich@suse.com>
933
934 PR gas/25438
935 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
936 destination for Cpu64-only variant.
937 (movzx): Fold patterns.
938 * i386-tbl.h: Re-generate.
939
7deea9aa
JB		 9402020-02-13 Jan Beulich <jbeulich@suse.com>
941
942 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
943 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
944 CPU_ANY_SSE4_FLAGS entry.
945 * i386-init.h: Re-generate.
946
6c0946d0
JB		 9472020-02-12 Jan Beulich <jbeulich@suse.com>
948
949 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
950 with Unspecified, making the present one AT&T syntax only.
951 * i386-tbl.h: Re-generate.
952
ddb56fe6
JB		 9532020-02-12 Jan Beulich <jbeulich@suse.com>
954
955 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
956 * i386-tbl.h: Re-generate.
957
5990e377
JB		 9582020-02-12 Jan Beulich <jbeulich@suse.com>
959
960 PR gas/24546
961 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
962 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
963 Amd64 and Intel64 templates.
964 (call, jmp): Likewise for far indirect variants. Dro
965 Unspecified.
966 * i386-tbl.h: Re-generate.
967
50128d0c
JB		 9682020-02-11 Jan Beulich <jbeulich@suse.com>
969
970 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
971 * i386-opc.h (ShortForm): Delete.
972 (struct i386_opcode_modifier): Remove shortform field.
973 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
974 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
975 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
976 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
977 Drop ShortForm.
978 * i386-tbl.h: Re-generate.
979
1e05b5c4
JB		 9802020-02-11 Jan Beulich <jbeulich@suse.com>
981
982 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
983 fucompi): Drop ShortForm from operand-less templates.
984 * i386-tbl.h: Re-generate.
985
2f5dd314
AM		 9862020-02-11 Alan Modra <amodra@gmail.com>
987
988 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
989 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
990 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
991 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
992 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
993
5aae9ae9
MM		 9942020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
995
996 * arm-dis.c (print_insn_cde): Define 'V' parse character.
997 (cde_opcodes): Add VCX* instructions.
998
4934a27c
MM		 9992020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1000 Matthew Malcomson <matthew.malcomson@arm.com>
1001
1002 * arm-dis.c (struct cdeopcode32): New.
1003 (CDE_OPCODE): New macro.
1004 (cde_opcodes): New disassembly table.
1005 (regnames): New option to table.
1006 (cde_coprocs): New global variable.
1007 (print_insn_cde): New
1008 (print_insn_thumb32): Use print_insn_cde.
1009 (parse_arm_disassembler_options): Parse coprocN args.
1010
4b5aaf5f
L		 10112020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1012
1013 PR gas/25516
1014 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1015 with ISA64.
1016 * i386-opc.h (AMD64): Removed.
1017 (Intel64): Likewose.
1018 (AMD64): New.
1019 (INTEL64): Likewise.
1020 (INTEL64ONLY): Likewise.
1021 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1022 * i386-opc.tbl (Amd64): New.
1023 (Intel64): Likewise.
1024 (Intel64Only): Likewise.
1025 Replace AMD64 with Amd64. Update sysenter/sysenter with
1026 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1027 * i386-tbl.h: Regenerated.
1028
9fc0b501
SB		 10292020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1030
1031 PR 25469
1032 * z80-dis.c: Add support for GBZ80 opcodes.
1033
c5d7be0c
AM		 10342020-02-04 Alan Modra <amodra@gmail.com>
1035
1036 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1037
44e4546f
AM		 10382020-02-03 Alan Modra <amodra@gmail.com>
1039
1040 * m32c-ibld.c: Regenerate.
1041
b2b1453a
AM		 10422020-02-01 Alan Modra <amodra@gmail.com>
1043
1044 * frv-ibld.c: Regenerate.
1045
4102be5c
JB		 10462020-01-31 Jan Beulich <jbeulich@suse.com>
1047
1048 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1049 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1050 (OP_E_memory): Replace xmm_mdq_mode case label by
1051 vex_scalar_w_dq_mode one.
1052 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1053
825bd36c
JB		 10542020-01-31 Jan Beulich <jbeulich@suse.com>
1055
1056 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1057 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1058 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1059 (intel_operand_size): Drop vex_w_dq_mode case label.
1060
c3036ed0
RS		 10612020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1062
1063 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1064 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1065
0c115f84
AM		 10662020-01-30 Alan Modra <amodra@gmail.com>
1067
1068 * m32c-ibld.c: Regenerate.
1069
bd434cc4
JM		 10702020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1071
1072 * bpf-opc.c: Regenerate.
1073
aeab2b26
JB		 10742020-01-30 Jan Beulich <jbeulich@suse.com>
1075
1076 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1077 (dis386): Use them to replace C2/C3 table entries.
1078 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1079 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1080 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1081 * i386-tbl.h: Re-generate.
1082
62b3f548
JB		 10832020-01-30 Jan Beulich <jbeulich@suse.com>
1084
1085 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1086 forms.
1087 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1088 DefaultSize.
1089 * i386-tbl.h: Re-generate.
1090
1bd8ae10
AM		 10912020-01-30 Alan Modra <amodra@gmail.com>
1092
1093 * tic4x-dis.c (tic4x_dp): Make unsigned.
1094
bc31405e
L		 10952020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1096 Jan Beulich <jbeulich@suse.com>
1097
1098 PR binutils/25445
1099 * i386-dis.c (MOVSXD_Fixup): New function.
1100 (movsxd_mode): New enum.
1101 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1102 (intel_operand_size): Handle movsxd_mode.
1103 (OP_E_register): Likewise.
1104 (OP_G): Likewise.
1105 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1106 register on movsxd. Add movsxd with 16-bit destination register
1107 for AMD64 and Intel64 ISAs.
1108 * i386-tbl.h: Regenerated.
1109
7568c93b
TC		 11102020-01-27 Tamar Christina <tamar.christina@arm.com>
1111
1112 PR 25403
1113 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1114 * aarch64-asm-2.c: Regenerate
1115 * aarch64-dis-2.c: Likewise.
1116 * aarch64-opc-2.c: Likewise.
1117
c006a730
JB		 11182020-01-21 Jan Beulich <jbeulich@suse.com>
1119
1120 * i386-opc.tbl (sysret): Drop DefaultSize.
1121 * i386-tbl.h: Re-generate.
1122
c906a69a
JB		 11232020-01-21 Jan Beulich <jbeulich@suse.com>
1124
1125 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1126 Dword.
1127 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1128 * i386-tbl.h: Re-generate.
1129
26916852
NC		 11302020-01-20 Nick Clifton <nickc@redhat.com>
1131
1132 * po/de.po: Updated German translation.
1133 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1134 * po/uk.po: Updated Ukranian translation.
1135
4d6cbb64
AM		 11362020-01-20 Alan Modra <amodra@gmail.com>
1137
1138 * hppa-dis.c (fput_const): Remove useless cast.
1139
2bddb71a
AM		 11402020-01-20 Alan Modra <amodra@gmail.com>
1141
1142 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1143
1b1bb2c6
NC		 11442020-01-18 Nick Clifton <nickc@redhat.com>
1145
1146 * configure: Regenerate.
1147 * po/opcodes.pot: Regenerate.
1148
ae774686
NC		 11492020-01-18 Nick Clifton <nickc@redhat.com>
1150
1151 Binutils 2.34 branch created.
1152
07f1f3aa
CB		 11532020-01-17 Christian Biesinger <cbiesinger@google.com>
1154
1155 * opintl.h: Fix spelling error (seperate).
1156
42e04b36
L		 11572020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1158
1159 * i386-opc.tbl: Add {vex} pseudo prefix.
1160 * i386-tbl.h: Regenerated.
1161
2da2eaf4
AV		 11622020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1163
1164 PR 25376
1165 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1166 (neon_opcodes): Likewise.
1167 (select_arm_features): Make sure we enable MVE bits when selecting
1168 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1169 any architecture.
1170
d0849eed
JB		 11712020-01-16 Jan Beulich <jbeulich@suse.com>
1172
1173 * i386-opc.tbl: Drop stale comment from XOP section.
1174
9cf70a44
JB		 11752020-01-16 Jan Beulich <jbeulich@suse.com>
1176
1177 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1178 (extractps): Add VexWIG to SSE2AVX forms.
1179 * i386-tbl.h: Re-generate.
1180
4814632e
JB		 11812020-01-16 Jan Beulich <jbeulich@suse.com>
1182
1183 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1184 Size64 from and use VexW1 on SSE2AVX forms.
1185 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1186 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1187 * i386-tbl.h: Re-generate.
1188
aad09917
AM		 11892020-01-15 Alan Modra <amodra@gmail.com>
1190
1191 * tic4x-dis.c (tic4x_version): Make unsigned long.
1192 (optab, optab_special, registernames): New file scope vars.
1193 (tic4x_print_register): Set up registernames rather than
1194 malloc'd registertable.
1195 (tic4x_disassemble): Delete optable and optable_special. Use
1196 optab and optab_special instead. Throw away old optab,
1197 optab_special and registernames when info->mach changes.
1198
7a6bf3be
SB		 11992020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1200
1201 PR 25377
1202 * z80-dis.c (suffix): Use .db instruction to generate double
1203 prefix.
1204
ca1eaac0
AM		 12052020-01-14 Alan Modra <amodra@gmail.com>
1206
1207 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1208 values to unsigned before shifting.
1209
1d67fe3b
TT		 12102020-01-13 Thomas Troeger <tstroege@gmx.de>
1211
1212 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1213 flow instructions.
1214 (print_insn_thumb16, print_insn_thumb32): Likewise.
1215 (print_insn): Initialize the insn info.
1216 * i386-dis.c (print_insn): Initialize the insn info fields, and
1217 detect jumps.
1218
5e4f7e05
CZ		 12192012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1220
1221 * arc-opc.c (C_NE): Make it required.
1222
b9fe6b8a
CZ		 12232012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1224
1225 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1226 reserved register name.
1227
90dee485
AM		 12282020-01-13 Alan Modra <amodra@gmail.com>
1229
1230 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1231 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1232
febda64f
AM		 12332020-01-13 Alan Modra <amodra@gmail.com>
1234
1235 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1236 result of wasm_read_leb128 in a uint64_t and check that bits
1237 are not lost when copying to other locals. Use uint32_t for
1238 most locals. Use PRId64 when printing int64_t.
1239
df08b588
AM		 12402020-01-13 Alan Modra <amodra@gmail.com>
1241
1242 * score-dis.c: Formatting.
1243 * score7-dis.c: Formatting.
1244
b2c759ce
AM		 12452020-01-13 Alan Modra <amodra@gmail.com>
1246
1247 * score-dis.c (print_insn_score48): Use unsigned variables for
1248 unsigned values. Don't left shift negative values.
1249 (print_insn_score32): Likewise.
1250 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1251
5496abe1
AM		 12522020-01-13 Alan Modra <amodra@gmail.com>
1253
1254 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1255
202e762b
AM		 12562020-01-13 Alan Modra <amodra@gmail.com>
1257
1258 * fr30-ibld.c: Regenerate.
1259
7ef412cf
AM		 12602020-01-13 Alan Modra <amodra@gmail.com>
1261
1262 * xgate-dis.c (print_insn): Don't left shift signed value.
1263 (ripBits): Formatting, use 1u.
1264
7f578b95
AM		 12652020-01-10 Alan Modra <amodra@gmail.com>
1266
1267 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1268 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1269
441af85b
AM		 12702020-01-10 Alan Modra <amodra@gmail.com>
1271
1272 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1273 and XRREG value earlier to avoid a shift with negative exponent.
1274 * m10200-dis.c (disassemble): Similarly.
1275
bce58db4
NC		 12762020-01-09 Nick Clifton <nickc@redhat.com>
1277
1278 PR 25224
1279 * z80-dis.c (ld_ii_ii): Use correct cast.
1280
40c75bc8
SB		 12812020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1282
1283 PR 25224
1284 * z80-dis.c (ld_ii_ii): Use character constant when checking
1285 opcode byte value.
1286
d835a58b
JB		 12872020-01-09 Jan Beulich <jbeulich@suse.com>
1288
1289 * i386-dis.c (SEP_Fixup): New.
1290 (SEP): Define.
1291 (dis386_twobyte): Use it for sysenter/sysexit.
1292 (enum x86_64_isa): Change amd64 enumerator to value 1.
1293 (OP_J): Compare isa64 against intel64 instead of amd64.
1294 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1295 forms.
1296 * i386-tbl.h: Re-generate.
1297
030a2e78
AM		 12982020-01-08 Alan Modra <amodra@gmail.com>
1299
1300 * z8k-dis.c: Include libiberty.h
1301 (instr_data_s): Make max_fetched unsigned.
1302 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1303 Don't exceed byte_info bounds.
1304 (output_instr): Make num_bytes unsigned.
1305 (unpack_instr): Likewise for nibl_count and loop.
1306 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1307 idx unsigned.
1308 * z8k-opc.h: Regenerate.
1309
bb82aefe
SV		 13102020-01-07 Shahab Vahedi <shahab@synopsys.com>
1311
1312 * arc-tbl.h (llock): Use 'LLOCK' as class.
1313 (llockd): Likewise.
1314 (scond): Use 'SCOND' as class.
1315 (scondd): Likewise.
1316 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1317 (scondd): Likewise.
1318
cc6aa1a6
AM		 13192020-01-06 Alan Modra <amodra@gmail.com>
1320
1321 * m32c-ibld.c: Regenerate.
1322
660e62b1
AM		 13232020-01-06 Alan Modra <amodra@gmail.com>
1324
1325 PR 25344
1326 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1327 Peek at next byte to prevent recursion on repeated prefix bytes.
1328 Ensure uninitialised "mybuf" is not accessed.
1329 (print_insn_z80): Don't zero n_fetch and n_used here,..
1330 (print_insn_z80_buf): ..do it here instead.
1331
c9ae58fe
AM		 13322020-01-04 Alan Modra <amodra@gmail.com>
1333
1334 * m32r-ibld.c: Regenerate.
1335
5f57d4ec
AM		 13362020-01-04 Alan Modra <amodra@gmail.com>
1337
1338 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1339
2c5c1196
AM		 13402020-01-04 Alan Modra <amodra@gmail.com>
1341
1342 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1343
2e98c6c5
AM		 13442020-01-04 Alan Modra <amodra@gmail.com>
1345
1346 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1347
567dfba2
JB		 13482020-01-03 Jan Beulich <jbeulich@suse.com>
1349
5437a02a
JB		 1350 * aarch64-tbl.h (aarch64_opcode_table): Use
1351 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1352
13532020-01-03 Jan Beulich <jbeulich@suse.com>
1354
1355 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1356 forms of SUDOT and USDOT.
1357
8c45011a
JB		 13582020-01-03 Jan Beulich <jbeulich@suse.com>
1359
5437a02a 1360 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1361 uzip{1,2}.
1362 * opcodes/aarch64-dis-2.c: Re-generate.
1363
f4950f76
JB		 13642020-01-03 Jan Beulich <jbeulich@suse.com>
1365
5437a02a 1366 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1367 FMMLA encoding.
1368 * opcodes/aarch64-dis-2.c: Re-generate.
1369
6655dba2
SB		 13702020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1371
1372 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1373
b14ce8bf
AM		 13742020-01-01 Alan Modra <amodra@gmail.com>
1375
1376 Update year range in copyright notice of all files.
1377
0b114740 1378For older changes see ChangeLog-2019
3499769a 1379\f
0b114740 1380Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1381
1382Copying and distribution of this file, with or without modification,
1383are permitted in any medium without royalty provided the copyright
1384notice and this notice are preserved.
1385
1386Local Variables:
1387mode: change-log
1388left-margin: 8
1389fill-column: 74
1390version-control: never
1391End:
GDB Binutils - Deliverables
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