[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

	* riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
	RISCV_GP_SYMBOL.

2017-03-30  Pip Cet  <pipcet@gmail.com>

	* configure.ac: Add (empty) bfd_wasm32_arch target.
	* configure: Regenerate
	* po/opcodes.pot: Regenerate.

2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>

	Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
	OSA2015.
	* opcodes/sparc-opc.c (asi_table): New ASIs.

2017-03-29  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
	"raw" option.
	(lookup_powerpc): Don't special case -1 dialect.  Handle
	PPC_OPCODE_RAW.
	(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
	lookup_powerpc call, pass it on second.

2017-03-27  Alan Modra  <amodra@gmail.com>

	PR 21303
	* ppc-dis.c (struct ppc_mopt): Comment.
	(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.

2017-03-27  Rinat Zelig  <rinat@mellanox.com>

	* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
	* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
	F_NPS_M, F_NPS_CORE, F_NPS_ALL.
	(insert_nps_misc_imm_offset): New function.
	(extract_nps_misc imm_offset): New function.
	(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
	(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-mkopc.c (main): Remove vx2 check.
	* s390-opc.txt: Remove vx2 instruction flags.

2017-03-21  Rinat Zelig  <rinat@mellanox.com>

	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	(insert_nps_imm_offset): New function.
	(extract_nps_imm_offset): New function.
	(insert_nps_imm_entry): New function.
	(extract_nps_imm_entry): New function.

2017-03-17  Alan Modra  <amodra@gmail.com>

	PR 21248
	* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
	mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
	those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.

2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
	<c.andi>: Likewise.
	<c.addiw> Likewise.

2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.

2017-03-13  Andrew Waterman  <andrew@sifive.com>

	* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
	<srl> Likewise.
	<srai> Likewise.
	<sra> Likewise.

2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Replace S with Load.
	* i386-opc.h (S): Removed.
	(Load): New.
	(i386_opcode_modifier): Replace s with load.
	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	and {evex}.  Replace S with Load.
	* i386-tbl.h: Regenerated.

2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Use CpuCET on rdsspq.
	* i386-tbl.h: Regenerated.

2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
	<vsx>: Do not use PPC_OPCODE_VSX3;

2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.

2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	(MOD_0F1E_PREFIX_1): Likewise.
	(MOD_0F38F5_PREFIX_2): Likewise.
	(MOD_0F38F6_PREFIX_0): Likewise.
	(RM_0F1E_MOD_3_REG_7): Likewise.
	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	(PREFIX_0F1E): Likewise.
	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	(PREFIX_0F38F5): Likewise.
	(dis386_twobyte): Use PREFIX_0F1E.
	(reg_table): Add REG_0F1E_MOD_3.
	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	(three_byte_table): Use PREFIX_0F38F5.
	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	PREFIX_MOD_3_0F01_REG_5_RM_2.
	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	(cpu_flags): Add CpuCET.
	* i386-opc.h (CpuCET): New enum.
	(CpuUnused): Commented out.
	(i386_cpu_flags): Add cpucet.
	* i386-opc.tbl: Add Intel CET instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2017-03-06  Alan Modra  <amodra@gmail.com>

	PR 21124
	* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
	(extract_raq, extract_ras, extract_rbx): New functions.
	(powerpc_operands): Use opposite corresponding insert function.
	(Q_MASK): Define.
	(powerpc_opcodes): Apply Q_MASK to all quad insns with even
	register restriction.

2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>

	* disassemble.c Include "safe-ctype.h".
	(disassemble_init_for_target): Handle s390 init.
	(remove_whitespace_and_extra_commas): New function.
	(disassembler_options_cmp): Likewise.
	* arm-dis.c: Include "libiberty.h".
	(NUM_ELEM): Delete.
	(regnames): Use long disassembler style names.
	Add force-thumb and no-force-thumb options.
	(NUM_ARM_REGNAMES): Rename from this...
	(NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
	(get_arm_regname_num_options): Delete.
	(set_arm_regname_option): Likewise.
	(get_arm_regnames): Likewise.
	(parse_disassembler_options): Likewise.
	(parse_arm_disassembler_option): Rename from this...
	(parse_arm_disassembler_options): ...to this.  Make static.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
	(print_insn): Use parse_arm_disassembler_options.
	(disassembler_options_arm): New function.
	(print_arm_disassembler_options): Handle updated regnames.
	* ppc-dis.c: Include "libiberty.h".
	(ppc_opts): Add "32" and "64" entries.
	(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
	(powerpc_init_dialect): Add break to switch statement.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro.
	(disassembler_options_powerpc): New function.
	(print_ppc_disassembler_options): Use ARRAY_SIZE.
	Remove printing of "32" and "64".
	* s390-dis.c: Include "libiberty.h".
	(init_flag): Remove unneeded variable.
	(struct s390_options_t): New structure type.
	(options): New structure.
	(init_disasm): Rename from this...
	(disassemble_init_s390): ...to this.  Add initializations for
	current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
	(print_insn_s390): Delete call to init_disasm.
	(disassembler_options_s390): New function.
	(print_s390_disassembler_options): Print using information from
	struct 'options'.
	* po/opcodes.pot: Regenerate.

2017-02-28  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (PCMPESTR_Fixup): New.
	(VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
	(prefix_table): Use PCMPESTR_Fixup.
	(vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
	PCMPESTR_Fixup.
	(vex_w_table): Delete VPCMPESTR{I,M} entries.
	* i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
	Split 64-bit and non-64-bit variants.
	* opcodes/i386-tbl.h: Re-generate.

2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
	(OP_SVE_V_HSD): New macros.
	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
	(aarch64_opcode_table): Add new SVE instructions.
	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
	for rotation operands.  Add new SVE operands.
	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
	(ins_sve_quad_index): Likewise.
	(ins_imm_rotate): Split into...
	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
	functions.
	(aarch64_ins_sve_addr_ri_s4): New function.
	(aarch64_ins_sve_quad_index): Likewise.
	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
	(ext_sve_quad_index): Likewise.
	(ext_imm_rotate): Split into...
	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
	functions.
	(aarch64_ext_sve_addr_ri_s4): New function.
	(aarch64_ext_sve_quad_index): Likewise.
	(aarch64_ext_sve_index): Allow quad indices.
	(do_misc_decoding): Likewise.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
	aarch64_field_kinds.
	(OPD_F_OD_MASK): Widen by one bit.
	(OPD_F_NO_ZR): Bump accordingly.
	(get_operand_field_width): New function.
	* aarch64-opc.c (fields): Add new SVE fields.
	(operand_general_constraint_met_p): Handle new SVE operands.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.

2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
	(aarch64_feature_compnum): ...this.
	(SIMD_V8_3): Replace with...
	(COMPNUM): ...this.
	(CNUM_INSN): New macro.
	(aarch64_opcode_table): Use it for the complex number instructions.

2017-02-24  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.

2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>

	Add support for associating SPARC ASIs with an architecture level.
	* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
	* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
	decoding of SPARC ASIs.

2017-02-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (get_valid_dis386): Don't special case VEX opcode
	82. For 3-byte VEX only special case opcode 77 in VEX_0F space.

2017-02-21  Jan Beulich  <jbeulich@suse.com>

	* aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
	1 (instead of to itself). Correct typo.

2017-02-14  Andrew Waterman  <andrew@sifive.com>

	* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
	pseudoinstructions.

2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
	(aarch64_sys_reg_supported_p): Handle them.

2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (UIMM6_20R): Define.
	(SIMM12_20): Use above.
	(SIMM12_20R): Define.
	(SIMM3_5_S): Use above.
	(UIMM7_A32_11R_S): Define.
	(UIMM7_9_S): Use above.
	(UIMM3_13R_S): Define.
	(SIMM11_A32_7_S): Use above.
	(SIMM9_8R): Define.
	(UIMM10_A32_8_S): Use above.
	(UIMM8_8R_S): Define.
	(W6): Use above.
	(arc_relax_opcodes): Use all above defines.

2017-02-15  Vineet Gupta <vgupta@synopsys.com>

	* arc-regs.h: Distinguish some of the registers different on
	ARC700 and HS38 cpus.

2017-02-14  Alan Modra  <amodra@gmail.com>

	PR 21118
	* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
	with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.

2017-02-11  Stafford Horne  <shorne@gmail.com>
	    Alan Modra  <amodra@gmail.com>

	* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
	Use insn_bytes_value and insn_int_value directly instead.  Don't
	free allocated memory until function exit.

2017-02-10  Nicholas Piggin  <npiggin@gmail.com>

	* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.

2017-02-03  Nick Clifton  <nickc@redhat.com>

	PR 21096
	* aarch64-opc.c (print_register_list): Ensure that the register
	list index will fir into the tb buffer.
	(print_register_offset_address): Likewise.
	* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.

2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>

	PR 21056
	* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
	instructions when the previous fetch packet ends with a 32-bit
	instruction.

2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>

        * pru-opc.c: Remove vague reference to a future GDB port.

2017-01-20  Nick Clifton  <nickc@redhat.com>

	* po/ga.po: Updated Irish translation.

2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.

2017-01-13  Yao Qi  <yao.qi@linaro.org>

	* m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
	if FETCH_DATA returns 0.
	(m68k_scan_mask): Likewise.
	(print_insn_m68k): Update code to handle -1 return value.

2017-01-13  Yao Qi  <yao.qi@linaro.org>

	* m68k-dis.c (enum print_insn_arg_error): New.
	(NEXTBYTE): Replace -3 with
	PRINT_INSN_ARG_MEMORY_ERROR.
	(NEXTULONG): Likewise.
	(NEXTSINGLE): Likewise.
	(NEXTDOUBLE): Likewise.
	(NEXTDOUBLE): Likewise.
	(NEXTPACKED): Likewise.
	(FETCH_ARG): Likewise.
	(FETCH_DATA): Update comments.
	(print_insn_arg): Update comments. Replace magic numbers with
	enum.
	(match_insn_m68k): Likewise.

2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
	CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
	* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
	(i386_cpu_flags): Add cpuavx512_vpopcntdq.
	* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.

2017-01-12  Yao Qi  <yao.qi@linaro.org>

	* msp430-dis.c (msp430_singleoperand): Return -1 if
	msp430dis_opcode_signed returns false.
	(msp430_doubleoperand): Likewise.
	(msp430_branchinstr): Return -1 if
	msp430dis_opcode_unsigned returns false.
	(msp430x_calla_instr): Likewise.
	(print_insn_msp430): Likewise.

2017-01-05  Nick Clifton  <nickc@redhat.com>

	PR 20946
	* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
	could not be matched.
	(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
	NULL.

2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
	(aarch64_opcode_table): Use RCPC_INSN.

2017-01-03  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
	extension.
	* riscv-opcodes/all-opcodes: Likewise.

2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>

	* riscv-dis.c (print_insn_args): Add fall through comment.

2017-01-03  Nick Clifton  <nickc@redhat.com>

	* po/sr.po: New Serbian translation.
	* configure.ac (ALL_LINGUAS): Add sr.
	* configure: Regenerate.

2017-01-02  Alan Modra  <amodra@gmail.com>

	* epiphany-desc.h: Regenerate.
	* epiphany-opc.h: Regenerate.
	* fr30-desc.h: Regenerate.
	* fr30-opc.h: Regenerate.
	* frv-desc.h: Regenerate.
	* frv-opc.h: Regenerate.
	* ip2k-desc.h: Regenerate.
	* ip2k-opc.h: Regenerate.
	* iq2000-desc.h: Regenerate.
	* iq2000-opc.h: Regenerate.
	* lm32-desc.h: Regenerate.
	* lm32-opc.h: Regenerate.
	* m32c-desc.h: Regenerate.
	* m32c-opc.h: Regenerate.
	* m32r-desc.h: Regenerate.
	* m32r-opc.h: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-opc.h: Regenerate.
	* mt-desc.h: Regenerate.
	* mt-opc.h: Regenerate.
	* or1k-desc.h: Regenerate.
	* or1k-opc.h: Regenerate.
	* xc16x-desc.h: Regenerate.
	* xc16x-opc.h: Regenerate.
	* xstormy16-desc.h: Regenerate.
	* xstormy16-opc.h: Regenerate.

2017-01-02  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2016
\f
Copyright (C) 2017 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
b5292032 PD	1	2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
	2
	3	* riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
	4	RISCV_GP_SYMBOL.
	5
f96bd6c2 PC	6	2017-03-30 Pip Cet <pipcet@gmail.com>
	7
	8	* configure.ac: Add (empty) bfd_wasm32_arch target.
	9	* configure: Regenerate
	10	* po/opcodes.pot: Regenerate.
	11
f7c514a3 JM	12	2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
	13
	14	Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
	15	OSA2015.
	16	* opcodes/sparc-opc.c (asi_table): New ASIs.
	17
52be03fd AM	18	2017-03-29 Alan Modra <amodra@gmail.com>
	19
	20	* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
	21	"raw" option.
	22	(lookup_powerpc): Don't special case -1 dialect. Handle
	23	PPC_OPCODE_RAW.
	24	(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
	25	lookup_powerpc call, pass it on second.
	26
9b753937 AM	27	2017-03-27 Alan Modra <amodra@gmail.com>
	28
	29	PR 21303
	30	* ppc-dis.c (struct ppc_mopt): Comment.
	31	(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
	32
c0c31e91 RZ	33	2017-03-27 Rinat Zelig <rinat@mellanox.com>
	34
	35	* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
	36	* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
	37	F_NPS_M, F_NPS_CORE, F_NPS_ALL.
	38	(insert_nps_misc_imm_offset): New function.
	39	(extract_nps_misc imm_offset): New function.
	40	(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
	41	(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
	42
2253c8f0 AK	43	2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	44
	45	* s390-mkopc.c (main): Remove vx2 check.
	46	* s390-opc.txt: Remove vx2 instruction flags.
	47
645d3342 RZ	48	2017-03-21 Rinat Zelig <rinat@mellanox.com>
	49
	50	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	51	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	52	(insert_nps_imm_offset): New function.
	53	(extract_nps_imm_offset): New function.
	54	(insert_nps_imm_entry): New function.
	55	(extract_nps_imm_entry): New function.
	56
4b94dd2d AM	57	2017-03-17 Alan Modra <amodra@gmail.com>
	58
	59	PR 21248
	60	* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
	61	mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
	62	those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
	63
b416fe87 KC	64	2017-03-14 Kito Cheng <kito.cheng@gmail.com>
	65
	66	* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
	67	<c.andi>: Likewise.
	68	<c.addiw> Likewise.
	69
03b039a5 KC	70	2017-03-14 Kito Cheng <kito.cheng@gmail.com>
	71
	72	* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
	73
2c232b83 AW	74	2017-03-13 Andrew Waterman <andrew@sifive.com>
	75
	76	* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
	77	<srl> Likewise.
	78	<srai> Likewise.
	79	<sra> Likewise.
	80
86fa6981 L	81	2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
	82
	83	* i386-gen.c (opcode_modifiers): Replace S with Load.
	84	* i386-opc.h (S): Removed.
	85	(Load): New.
	86	(i386_opcode_modifier): Replace s with load.
	87	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	88	and {evex}. Replace S with Load.
	89	* i386-tbl.h: Regenerated.
	90
c1fe188b L	91	2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
	92
	93	* i386-opc.tbl: Use CpuCET on rdsspq.
	94	* i386-tbl.h: Regenerated.
	95
4b8b687e PB	96	2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
	97
	98	* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
	99	<vsx>: Do not use PPC_OPCODE_VSX3;
	100
1437d063 PB	101	2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
	102
	103	* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
	104
603555e5 L	105	2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
	106
	107	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	108	(MOD_0F1E_PREFIX_1): Likewise.
	109	(MOD_0F38F5_PREFIX_2): Likewise.
	110	(MOD_0F38F6_PREFIX_0): Likewise.
	111	(RM_0F1E_MOD_3_REG_7): Likewise.
	112	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	113	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	114	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	115	(PREFIX_0F1E): Likewise.
	116	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	117	(PREFIX_0F38F5): Likewise.
	118	(dis386_twobyte): Use PREFIX_0F1E.
	119	(reg_table): Add REG_0F1E_MOD_3.
	120	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	121	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	122	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
	123	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	124	(three_byte_table): Use PREFIX_0F38F5.
	125	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	126	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	127	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	128	RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	129	PREFIX_MOD_3_0F01_REG_5_RM_2.
	130	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	131	(cpu_flags): Add CpuCET.
	132	* i386-opc.h (CpuCET): New enum.
	133	(CpuUnused): Commented out.
	134	(i386_cpu_flags): Add cpucet.
	135	* i386-opc.tbl: Add Intel CET instructions.
	136	* i386-init.h: Regenerated.
	137	* i386-tbl.h: Likewise.
	138
73f07bff AM	139	2017-03-06 Alan Modra <amodra@gmail.com>
	140
	141	PR 21124
	142	* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
	143	(extract_raq, extract_ras, extract_rbx): New functions.
	144	(powerpc_operands): Use opposite corresponding insert function.
	145	(Q_MASK): Define.
	146	(powerpc_opcodes): Apply Q_MASK to all quad insns with even
	147	register restriction.
	148
65b48a81 PB	149	2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
	150
	151	* disassemble.c Include "safe-ctype.h".
	152	(disassemble_init_for_target): Handle s390 init.
	153	(remove_whitespace_and_extra_commas): New function.
	154	(disassembler_options_cmp): Likewise.
	155	* arm-dis.c: Include "libiberty.h".
	156	(NUM_ELEM): Delete.
	157	(regnames): Use long disassembler style names.
	158	Add force-thumb and no-force-thumb options.
	159	(NUM_ARM_REGNAMES): Rename from this...
	160	(NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
	161	(get_arm_regname_num_options): Delete.
	162	(set_arm_regname_option): Likewise.
	163	(get_arm_regnames): Likewise.
	164	(parse_disassembler_options): Likewise.
	165	(parse_arm_disassembler_option): Rename from this...
	166	(parse_arm_disassembler_options): ...to this. Make static.
	167	Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
	168	(print_insn): Use parse_arm_disassembler_options.
	169	(disassembler_options_arm): New function.
	170	(print_arm_disassembler_options): Handle updated regnames.
	171	* ppc-dis.c: Include "libiberty.h".
	172	(ppc_opts): Add "32" and "64" entries.
	173	(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
	174	(powerpc_init_dialect): Add break to switch statement.
	175	Use new FOR_EACH_DISASSEMBLER_OPTION macro.
	176	(disassembler_options_powerpc): New function.
	177	(print_ppc_disassembler_options): Use ARRAY_SIZE.
	178	Remove printing of "32" and "64".
	179	* s390-dis.c: Include "libiberty.h".
	180	(init_flag): Remove unneeded variable.
	181	(struct s390_options_t): New structure type.
	182	(options): New structure.
	183	(init_disasm): Rename from this...
	184	(disassemble_init_s390): ...to this. Add initializations for
	185	current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
	186	(print_insn_s390): Delete call to init_disasm.
	187	(disassembler_options_s390): New function.
	188	(print_s390_disassembler_options): Print using information from
	189	struct 'options'.
	190	* po/opcodes.pot: Regenerate.
	191
15c7c1d8 JB	192	2017-02-28 Jan Beulich <jbeulich@suse.com>
	193
	194	* i386-dis.c (PCMPESTR_Fixup): New.
	195	(VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
	196	(prefix_table): Use PCMPESTR_Fixup.
	197	(vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
	198	PCMPESTR_Fixup.
	199	(vex_w_table): Delete VPCMPESTR{I,M} entries.
	200	* i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
	201	Split 64-bit and non-64-bit variants.
	202	* opcodes/i386-tbl.h: Re-generate.
	203
582e12bf RS	204	2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
	205
	206	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
	207	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
	208	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
	209	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
	210	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
	211	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
	212	(OP_SVE_V_HSD): New macros.
	213	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
	214	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
	215	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
	216	(aarch64_opcode_table): Add new SVE instructions.
	217	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
	218	for rotation operands. Add new SVE operands.
	219	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
	220	(ins_sve_quad_index): Likewise.
	221	(ins_imm_rotate): Split into...
	222	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
	223	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
	224	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
	225	functions.
	226	(aarch64_ins_sve_addr_ri_s4): New function.
	227	(aarch64_ins_sve_quad_index): Likewise.
	228	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
	229	* aarch64-asm-2.c: Regenerate.
	230	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
	231	(ext_sve_quad_index): Likewise.
	232	(ext_imm_rotate): Split into...
	233	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
	234	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
	235	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
	236	functions.
	237	(aarch64_ext_sve_addr_ri_s4): New function.
	238	(aarch64_ext_sve_quad_index): Likewise.
	239	(aarch64_ext_sve_index): Allow quad indices.
	240	(do_misc_decoding): Likewise.
	241	* aarch64-dis-2.c: Regenerate.
	242	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
	243	aarch64_field_kinds.
	244	(OPD_F_OD_MASK): Widen by one bit.
	245	(OPD_F_NO_ZR): Bump accordingly.
	246	(get_operand_field_width): New function.
	247	* aarch64-opc.c (fields): Add new SVE fields.
	248	(operand_general_constraint_met_p): Handle new SVE operands.
	249	(aarch64_print_operand): Likewise.
	250	* aarch64-opc-2.c: Regenerate.
	251
f482d304 RS	252	2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
	253
	254	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
	255	(aarch64_feature_compnum): ...this.
	256	(SIMD_V8_3): Replace with...
	257	(COMPNUM): ...this.
	258	(CNUM_INSN): New macro.
	259	(aarch64_opcode_table): Use it for the complex number instructions.
	260
7db2c588 JB	261	2017-02-24 Jan Beulich <jbeulich@suse.com>
	262
	263	* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
	264
1e9d41d4 SL	265	2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
	266
	267	Add support for associating SPARC ASIs with an architecture level.
	268	* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
	269	* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
	270	decoding of SPARC ASIs.
	271
53c4d625 JB	272	2017-02-23 Jan Beulich <jbeulich@suse.com>
	273
	274	* i386-dis.c (get_valid_dis386): Don't special case VEX opcode
	275	82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
	276
11648de5 JB	277	2017-02-21 Jan Beulich <jbeulich@suse.com>
	278
	279	* aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
	280	1 (instead of to itself). Correct typo.
	281
f98d33be AW	282	2017-02-14 Andrew Waterman <andrew@sifive.com>
	283
	284	* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
	285	pseudoinstructions.
	286
773fb663 RS	287	2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
	288
	289	* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
	290	(aarch64_sys_reg_supported_p): Handle them.
	291
cc07cda6 CZ	292	2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
	293
	294	* arc-opc.c (UIMM6_20R): Define.
	295	(SIMM12_20): Use above.
	296	(SIMM12_20R): Define.
	297	(SIMM3_5_S): Use above.
	298	(UIMM7_A32_11R_S): Define.
	299	(UIMM7_9_S): Use above.
	300	(UIMM3_13R_S): Define.
	301	(SIMM11_A32_7_S): Use above.
	302	(SIMM9_8R): Define.
	303	(UIMM10_A32_8_S): Use above.
	304	(UIMM8_8R_S): Define.
	305	(W6): Use above.
	306	(arc_relax_opcodes): Use all above defines.
	307
66a5a740 VG	308	2017-02-15 Vineet Gupta <vgupta@synopsys.com>
	309
	310	* arc-regs.h: Distinguish some of the registers different on
	311	ARC700 and HS38 cpus.
	312
7e0de605 AM	313	2017-02-14 Alan Modra <amodra@gmail.com>
	314
	315	PR 21118
	316	* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
	317	with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
	318
54064fdb AM	319	2017-02-11 Stafford Horne <shorne@gmail.com>
	320	Alan Modra <amodra@gmail.com>
	321
	322	* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
	323	Use insn_bytes_value and insn_int_value directly instead. Don't
	324	free allocated memory until function exit.
	325
dce75bf9 NP	326	2017-02-10 Nicholas Piggin <npiggin@gmail.com>
	327
	328	* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
	329
1b7e3d2f NC	330	2017-02-03 Nick Clifton <nickc@redhat.com>
	331
	332	PR 21096
	333	* aarch64-opc.c (print_register_list): Ensure that the register
	334	list index will fir into the tb buffer.
	335	(print_register_offset_address): Likewise.
	336	* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
	337
8ec5cf65 AD	338	2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
	339
	340	PR 21056
	341	* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
	342	instructions when the previous fetch packet ends with a 32-bit
	343	instruction.
	344
a1aa5e81 DD	345	2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
	346
	347	* pru-opc.c: Remove vague reference to a future GDB port.
	348
add3afb2 NC	349	2017-01-20 Nick Clifton <nickc@redhat.com>
	350
	351	* po/ga.po: Updated Irish translation.
	352
c13a63b0 SN	353	2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
	354
	355	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
	356
9608051a YQ	357	2017-01-13 Yao Qi <yao.qi@linaro.org>
	358
	359	* m68k-dis.c (match_insn_m68k): Extend comments. Return -1
	360	if FETCH_DATA returns 0.
	361	(m68k_scan_mask): Likewise.
	362	(print_insn_m68k): Update code to handle -1 return value.
	363
f622ea96 YQ	364	2017-01-13 Yao Qi <yao.qi@linaro.org>
	365
	366	* m68k-dis.c (enum print_insn_arg_error): New.
	367	(NEXTBYTE): Replace -3 with
	368	PRINT_INSN_ARG_MEMORY_ERROR.
	369	(NEXTULONG): Likewise.
	370	(NEXTSINGLE): Likewise.
	371	(NEXTDOUBLE): Likewise.
	372	(NEXTDOUBLE): Likewise.
	373	(NEXTPACKED): Likewise.
	374	(FETCH_ARG): Likewise.
	375	(FETCH_DATA): Update comments.
	376	(print_insn_arg): Update comments. Replace magic numbers with
	377	enum.
	378	(match_insn_m68k): Likewise.
	379
620214f7 IT	380	2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
	381
	382	* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
	383	* i386-dis-evex.h (evex_table): Updated.
	384	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
	385	CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	386	(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
	387	* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
	388	(i386_cpu_flags): Add cpuavx512_vpopcntdq.
	389	* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
	390	* i386-init.h: Regenerate.
	391	* i386-tbl.h: Ditto.
	392
d95014a2 YQ	393	2017-01-12 Yao Qi <yao.qi@linaro.org>
	394
	395	* msp430-dis.c (msp430_singleoperand): Return -1 if
	396	msp430dis_opcode_signed returns false.
	397	(msp430_doubleoperand): Likewise.
	398	(msp430_branchinstr): Return -1 if
	399	msp430dis_opcode_unsigned returns false.
	400	(msp430x_calla_instr): Likewise.
	401	(print_insn_msp430): Likewise.
	402
0ae60c3e NC	403	2017-01-05 Nick Clifton <nickc@redhat.com>
	404
	405	PR 20946
	406	* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
	407	could not be matched.
	408	(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
	409	NULL.
	410
d74d4880 SN	411	2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
	412
	413	* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
	414	(aarch64_opcode_table): Use RCPC_INSN.
	415
cc917fd9 KC	416	2017-01-03 Kito Cheng <kito.cheng@gmail.com>
	417
	418	* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
	419	extension.
	420	* riscv-opcodes/all-opcodes: Likewise.
	421
b52d3cfc DP	422	2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
	423
	424	* riscv-dis.c (print_insn_args): Add fall through comment.
	425
f90c58d5 NC	426	2017-01-03 Nick Clifton <nickc@redhat.com>
	427
	428	* po/sr.po: New Serbian translation.
	429	* configure.ac (ALL_LINGUAS): Add sr.
	430	* configure: Regenerate.
	431
f47b0d4a AM	432	2017-01-02 Alan Modra <amodra@gmail.com>
	433
	434	* epiphany-desc.h: Regenerate.
	435	* epiphany-opc.h: Regenerate.
	436	* fr30-desc.h: Regenerate.
	437	* fr30-opc.h: Regenerate.
	438	* frv-desc.h: Regenerate.
	439	* frv-opc.h: Regenerate.
	440	* ip2k-desc.h: Regenerate.
	441	* ip2k-opc.h: Regenerate.
	442	* iq2000-desc.h: Regenerate.
	443	* iq2000-opc.h: Regenerate.
	444	* lm32-desc.h: Regenerate.
	445	* lm32-opc.h: Regenerate.
	446	* m32c-desc.h: Regenerate.
	447	* m32c-opc.h: Regenerate.
	448	* m32r-desc.h: Regenerate.
	449	* m32r-opc.h: Regenerate.
	450	* mep-desc.h: Regenerate.
	451	* mep-opc.h: Regenerate.
	452	* mt-desc.h: Regenerate.
	453	* mt-opc.h: Regenerate.
	454	* or1k-desc.h: Regenerate.
	455	* or1k-opc.h: Regenerate.
	456	* xc16x-desc.h: Regenerate.
	457	* xc16x-opc.h: Regenerate.
	458	* xstormy16-desc.h: Regenerate.
	459	* xstormy16-opc.h: Regenerate.
	460
2571583a AM	461	2017-01-02 Alan Modra <amodra@gmail.com>
	462
	463	Update year range in copyright notice of all files.
	464
5c1ad6b5	465	For older changes see ChangeLog-2016
3499769a	466	\f
5c1ad6b5	467	Copyright (C) 2017 Free Software Foundation, Inc.
3499769a AM	468
	469	Copying and distribution of this file, with or without modification,
	470	are permitted in any medium without royalty provided the copyright
	471	notice and this notice are preserved.
	472
	473	Local Variables:
	474	mode: change-log
	475	left-margin: 8
	476	fill-column: 74
	477	version-control: never
	478	End: