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Silence gcc printf warnings
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
0af1713e
AM		 12008-07-30 Alan Modra <amodra@bigpond.net.au>
2
3 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
4
30c09090
RS		 52008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
6
7 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
8
c27e721e
AN		 92008-07-07 Adam Nemet <anemet@caviumnetworks.com>
10
11 * mips-opc.c (CP): New macro.
12 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
13 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
14 dmtc2 Octeon instructions.
15
bd2e2557
SS		 162008-07-07 Stan Shebs <stan@codesourcery.com>
17
18 * dis-init.c (init_disassemble_info): Init endian_code field.
19 * arm-dis.c (print_insn): Disassemble code according to
20 setting of endian_code.
21 (print_insn_big_arm): Detect when BE8 extension flag has been set.
22
6ba2a415
RS		 232008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
24
25 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
26 for ELF symbols.
27
c8187e15
PB		 282008-06-25 Peter Bergner <bergner@vnet.ibm.com>
29
30 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
31 (print_ppc_disassembler_options): Likewise.
32 * ppc-opc.c (PPC464): Define.
33 (powerpc_opcodes): Add mfdcrux and mtdcrux.
34
7a283e07
RW		 352008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
36
37 * configure: Regenerate.
38
fa452fa6
PB		 392008-06-13 Peter Bergner <bergner@vnet.ibm.com>
40
41 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
42 ppc_cpu_t typedef.
43 (struct dis_private): New.
44 (POWERPC_DIALECT): New define.
45 (powerpc_dialect): Renamed to...
46 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
47 struct dis_private.
48 (print_insn_big_powerpc): Update for using structure in
49 info->private_data.
50 (print_insn_little_powerpc): Likewise.
51 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
52 (skip_optional_operands): Likewise.
53 (print_insn_powerpc): Likewise. Remove initialization of dialect.
54 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
55 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
56 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
57 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
58 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
59 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
60 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
61 param to be of type ppc_cpu_t. Update prototype.
62
bb35fb24
NC		 632008-06-12 Adam Nemet <anemet@caviumnetworks.com>
64
65 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
66 +s, +S.
67 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
68 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
69 syncw, syncws, vm3mulu, vm0 and vmulu.
70
dd3cbb7e
NC		 71 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
72 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
73 seqi, sne and snei.
74
a5dabbb0
L		 752008-05-30 H.J. Lu <hongjiu.lu@intel.com>
76
77 * i386-opc.tbl: Add vmovd with 64bit operand.
78 * i386-tbl.h: Regenerated.
79
725a9891
MS		 802008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
81
82 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
83
cbc80391
L		 842008-05-22 H.J. Lu <hongjiu.lu@intel.com>
85
86 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
87 * i386-tbl.h: Regenerated.
88
116615c5
L		 892008-05-22 H.J. Lu <hongjiu.lu@intel.com>
90
91 PR gas/6517
92 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
93 into 32bit and 64bit. Remove Reg64|Qword and add
94 IgnoreSize|No_qSuf on 32bit version.
95 * i386-tbl.h: Regenerated.
96
d9479f2d
L		 972008-05-21 H.J. Lu <hongjiu.lu@intel.com>
98
99 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
100 * i386-tbl.h: Regenerated.
101
3ce6fddb
NC		 1022008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
103
104 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
105
8944f3c2
AM		 1062008-05-14 Alan Modra <amodra@bigpond.net.au>
107
108 * Makefile.am: Run "make dep-am".
109 * Makefile.in: Regenerate.
110
f1f8f695
L		 1112008-05-02 H.J. Lu <hongjiu.lu@intel.com>
112
113 * i386-dis.c (MOVBE_Fixup): New.
114 (Mo): Likewise.
115 (PREFIX_0F3880): Likewise.
116 (PREFIX_0F3881): Likewise.
117 (PREFIX_0F38F0): Updated.
118 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
119 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
120 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
121
122 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
123 CPU_EPT_FLAGS.
124 (cpu_flags): Add CpuMovbe and CpuEPT.
125
126 * i386-opc.h (CpuMovbe): New.
127 (CpuEPT): Likewise.
128 (CpuLM): Updated.
129 (i386_cpu_flags): Add cpumovbe and cpuept.
130
131 * i386-opc.tbl: Add entries for movbe and EPT instructions.
132 * i386-init.h: Regenerated.
133 * i386-tbl.h: Likewise.
134
89aa3097
AN		 1352008-04-29 Adam Nemet <anemet@caviumnetworks.com>
136
137 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
138 the two drem and the two dremu macros.
139
39c5c168
AN		 1402008-04-28 Adam Nemet <anemet@caviumnetworks.com>
141
142 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
143 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
144 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
145 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
146
f04d18b7
DM		 1472008-04-25 David S. Miller <davem@davemloft.net>
148
149 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
150 instead of %sys_tick_cmpr, as suggested in architecture manuals.
151
6194aaab
L		 1522008-04-23 Paolo Bonzini <bonzini@gnu.org>
153
154 * aclocal.m4: Regenerate.
155 * configure: Regenerate.
156
1a6b486f
DM		 1572008-04-23 David S. Miller <davem@davemloft.net>
158
159 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
160 extended values.
161 (prefetch_table): Add missing values.
162
81f8a913
L		 1632008-04-22 H.J. Lu <hongjiu.lu@intel.com>
164
165 * i386-gen.c (opcode_modifiers): Add NoAVX.
166
167 * i386-opc.h (NoAVX): New.
168 (OldGcc): Updated.
169 (i386_opcode_modifier): Add noavx.
170
171 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
172 instructions which don't have AVX equivalent.
173 * i386-tbl.h: Regenerated.
174
dae39acc
L		 1752008-04-18 H.J. Lu <hongjiu.lu@intel.com>
176
177 * i386-dis.c (OP_VEX_FMA): New.
178 (OP_EX_VexImmW): Likewise.
179 (VexFMA): Likewise.
180 (Vex128FMA): Likewise.
181 (EXVexImmW): Likewise.
182 (get_vex_imm8): Likewise.
183 (OP_EX_VexReg): Likewise.
184 (vex_i4_done): Renamed to ...
185 (vex_w_done): This.
186 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
187 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
188 FMA instructions.
189 (print_insn): Updated.
190 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
191 (OP_REG_VexI4): Check invalid high registers.
192
ce886ab1
DR		 1932008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
194 Michael Meissner <michael.meissner@amd.com>
195
196 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
197 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 198
19a6653c
AM		 1992008-04-14 Edmar Wienskoski <edmar@freescale.com>
200
201 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
202 accept Power E500MC instructions.
203 (print_ppc_disassembler_options): Document -Me500mc.
204 * ppc-opc.c (DUIS, DUI, T): New.
205 (XRT, XRTRA): Likewise.
206 (E500MC): Likewise.
207 (powerpc_opcodes): Add new Power E500MC instructions.
208
112b7c50
AK		 2092008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
210
211 * s390-dis.c (init_disasm): Evaluate disassembler_options.
212 (print_s390_disassembler_options): New function.
213 * disassemble.c (disassembler_usage): Invoke
214 print_s390_disassembler_options.
215
7ff42648
AK		 2162008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
217
218 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
219 of local variables used for mnemonic parsing: prefix, suffix and
220 number.
221
45a5551e
AK		 2222008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
223
224 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
225 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
226 (s390_crb_extensions): New extensions table.
227 (insertExpandedMnemonic): Handle '$' tag.
228 * s390-opc.txt: Remove conditional jump variants which can now
229 be expanded automatically.
230 Replace '*' tag with '$' in the compare and branch instructions.
231
06c8514a
L		 2322008-04-07 H.J. Lu <hongjiu.lu@intel.com>
233
234 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
235 (PREFIX_VEX_3AXX): Likewis.
236
b122c285
L		 2372008-04-07 H.J. Lu <hongjiu.lu@intel.com>
238
239 * i386-opc.tbl: Remove 4 extra blank lines.
240
594ab6a3
L		 2412008-04-04 H.J. Lu <hongjiu.lu@intel.com>
242
243 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
244 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
245 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
246 * i386-opc.tbl: Likewise.
247
248 * i386-opc.h (CpuCLMUL): Renamed to ...
249 (CpuPCLMUL): This.
250 (CpuFMA): Updated.
251 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
252
253 * i386-init.h: Regenerated.
254
c0f3af97
L		 2552008-04-03 H.J. Lu <hongjiu.lu@intel.com>
256
257 * i386-dis.c (OP_E_register): New.
258 (OP_E_memory): Likewise.
259 (OP_VEX): Likewise.
260 (OP_EX_Vex): Likewise.
261 (OP_EX_VexW): Likewise.
262 (OP_XMM_Vex): Likewise.
263 (OP_XMM_VexW): Likewise.
264 (OP_REG_VexI4): Likewise.
265 (PCLMUL_Fixup): Likewise.
266 (VEXI4_Fixup): Likewise.
267 (VZERO_Fixup): Likewise.
268 (VCMP_Fixup): Likewise.
269 (VPERMIL2_Fixup): Likewise.
270 (rex_original): Likewise.
271 (rex_ignored): Likewise.
272 (Mxmm): Likewise.
273 (XMM): Likewise.
274 (EXxmm): Likewise.
275 (EXxmmq): Likewise.
276 (EXymmq): Likewise.
277 (Vex): Likewise.
278 (Vex128): Likewise.
279 (Vex256): Likewise.
280 (VexI4): Likewise.
281 (EXdVex): Likewise.
282 (EXqVex): Likewise.
283 (EXVexW): Likewise.
284 (EXdVexW): Likewise.
285 (EXqVexW): Likewise.
286 (XMVex): Likewise.
287 (XMVexW): Likewise.
288 (XMVexI4): Likewise.
289 (PCLMUL): Likewise.
290 (VZERO): Likewise.
291 (VCMP): Likewise.
292 (VPERMIL2): Likewise.
293 (xmm_mode): Likewise.
294 (xmmq_mode): Likewise.
295 (ymmq_mode): Likewise.
296 (vex_mode): Likewise.
297 (vex128_mode): Likewise.
298 (vex256_mode): Likewise.
299 (USE_VEX_C4_TABLE): Likewise.
300 (USE_VEX_C5_TABLE): Likewise.
301 (USE_VEX_LEN_TABLE): Likewise.
302 (VEX_C4_TABLE): Likewise.
303 (VEX_C5_TABLE): Likewise.
304 (VEX_LEN_TABLE): Likewise.
305 (REG_VEX_XX): Likewise.
306 (MOD_VEX_XXX): Likewise.
307 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
308 (PREFIX_0F3A44): Likewise.
309 (PREFIX_0F3ADF): Likewise.
310 (PREFIX_VEX_XXX): Likewise.
311 (VEX_OF): Likewise.
312 (VEX_OF38): Likewise.
313 (VEX_OF3A): Likewise.
314 (VEX_LEN_XXX): Likewise.
315 (vex): Likewise.
316 (need_vex): Likewise.
317 (need_vex_reg): Likewise.
318 (vex_i4_done): Likewise.
319 (vex_table): Likewise.
320 (vex_len_table): Likewise.
321 (OP_REG_VexI4): Likewise.
322 (vex_cmp_op): Likewise.
323 (pclmul_op): Likewise.
324 (vpermil2_op): Likewise.
325 (m_mode): Updated.
326 (es_reg): Likewise.
327 (PREFIX_0F38F0): Likewise.
328 (PREFIX_0F3A60): Likewise.
329 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
330 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
331 and PREFIX_VEX_XXX entries.
332 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
333 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
334 PREFIX_0F3ADF.
335 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
336 Add MOD_VEX_XXX entries.
337 (ckprefix): Initialize rex_original and rex_ignored. Store the
338 REX byte in rex_original.
339 (get_valid_dis386): Handle the implicit prefix in VEX prefix
340 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
341 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
342 calling get_valid_dis386. Use rex_original and rex_ignored when
343 printing out REX.
344 (putop): Handle "XY".
345 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
346 ymmq_mode.
347 (OP_E_extended): Updated to use OP_E_register and
348 OP_E_memory.
349 (OP_XMM): Handle VEX.
350 (OP_EX): Likewise.
351 (XMM_Fixup): Likewise.
352 (CMP_Fixup): Use ARRAY_SIZE.
353
354 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
355 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
356 (operand_type_init): Add OPERAND_TYPE_REGYMM and
357 OPERAND_TYPE_VEX_IMM4.
358 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
359 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
360 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
361 VexImmExt and SSE2AVX.
362 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
363
364 * i386-opc.h (CpuAVX): New.
365 (CpuAES): Likewise.
366 (CpuCLMUL): Likewise.
367 (CpuFMA): Likewise.
368 (Vex): Likewise.
369 (Vex256): Likewise.
370 (VexNDS): Likewise.
371 (VexNDD): Likewise.
372 (VexW0): Likewise.
373 (VexW1): Likewise.
374 (Vex0F): Likewise.
375 (Vex0F38): Likewise.
376 (Vex0F3A): Likewise.
377 (Vex3Sources): Likewise.
378 (VexImmExt): Likewise.
379 (SSE2AVX): Likewise.
380 (RegYMM): Likewise.
381 (Ymmword): Likewise.
382 (Vex_Imm4): Likewise.
383 (Implicit1stXmm0): Likewise.
384 (CpuXsave): Updated.
385 (CpuLM): Likewise.
386 (ByteOkIntel): Likewise.
387 (OldGcc): Likewise.
388 (Control): Likewise.
389 (Unspecified): Likewise.
390 (OTMax): Likewise.
391 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
392 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
393 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
394 vex3sources, veximmext and sse2avx.
395 (i386_operand_type): Add regymm, ymmword and vex_imm4.
396
397 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
398
399 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
400
401 * i386-init.h: Regenerated.
402 * i386-tbl.h: Likewise.
403
b21c9cb4
BS		 4042008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
405
406 From Robin Getz <robin.getz@analog.com>
407 * bfin-dis.c (bu32): Typedef.
408 (enum const_forms_t): Add c_uimm32 and c_huimm32.
409 (constant_formats[]): Add uimm32 and huimm16.
410 (fmtconst_val): New.
411 (uimm32): Define.
412 (huimm32): Define.
413 (imm16_val): Define.
414 (luimm16_val): Define.
415 (struct saved_state): Define.
416 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
417 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
418 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
419 (get_allreg): New.
420 (decode_LDIMMhalf_0): Print out the whole register value.
421
ee171c8f
BS		 422 From Jie Zhang <jie.zhang@analog.com>
423 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
424 multiply and multiply-accumulate to data register instruction.
425
086134ec
BS		 426 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
427 c_imm32, c_huimm32e): Define.
428 (constant_formats): Add flags for printing decimal, leading spaces, and
429 exact symbols.
430 (comment, parallel): Add global flags in all disassembly.
431 (fmtconst): Take advantage of new flags, and print default in hex.
432 (fmtconst_val): Likewise.
433 (decode_macfunc): Be consistant with spaces, tabs, comments,
434 capitalization in disassembly, fix minor coding style issues.
435 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
436 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
437 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
438 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
439 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
440 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
441 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
442 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
443 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
444 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
445 _print_insn_bfin, print_insn_bfin): Likewise.
446
58c85be7
RW		 4472008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
448
449 * aclocal.m4: Regenerate.
450 * configure: Likewise.
451 * Makefile.in: Likewise.
452
50e7d84b
AM		 4532008-03-13 Alan Modra <amodra@bigpond.net.au>
454
455 * Makefile.am: Run "make dep-am".
456 * Makefile.in: Regenerate.
457 * configure: Regenerate.
458
de866fcc
AM		 4592008-03-07 Alan Modra <amodra@bigpond.net.au>
460
461 * ppc-opc.c (powerpc_opcodes): Order and format.
462
28dbc079
L		 4632008-03-01 H.J. Lu <hongjiu.lu@intel.com>
464
465 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
466 * i386-tbl.h: Regenerated.
467
849830bd
L		 4682008-02-23 H.J. Lu <hongjiu.lu@intel.com>
469
470 * i386-opc.tbl: Disallow 16-bit near indirect branches for
471 x86-64.
472 * i386-tbl.h: Regenerated.
473
743ddb6b
JB		 4742008-02-21 Jan Beulich <jbeulich@novell.com>
475
476 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
477 and Fword for far indirect jmp. Allow Reg16 and Word for near
478 indirect jmp on x86-64. Disallow Fword for lcall.
479 * i386-tbl.h: Re-generate.
480
796d5313
NC		 4812008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
482
483 * cr16-opc.c (cr16_num_optab): Defined
484
65da13b5
L		 4852008-02-16 H.J. Lu <hongjiu.lu@intel.com>
486
487 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
488 * i386-init.h: Regenerated.
489
0e336180
NC		 4902008-02-14 Nick Clifton <nickc@redhat.com>
491
492 PR binutils/5524
493 * configure.in (SHARED_LIBADD): Select the correct host specific
494 file extension for shared libraries.
495 * configure: Regenerate.
496
b7240065
JB		 4972008-02-13 Jan Beulich <jbeulich@novell.com>
498
499 * i386-opc.h (RegFlat): New.
500 * i386-reg.tbl (flat): Add.
501 * i386-tbl.h: Re-generate.
502
34b772a6
JB		 5032008-02-13 Jan Beulich <jbeulich@novell.com>
504
505 * i386-dis.c (a_mode): New.
506 (cond_jump_mode): Adjust.
507 (Ma): Change to a_mode.
508 (intel_operand_size): Handle a_mode.
509 * i386-opc.tbl: Allow Dword and Qword for bound.
510 * i386-tbl.h: Re-generate.
511
a60de03c
JB		 5122008-02-13 Jan Beulich <jbeulich@novell.com>
513
514 * i386-gen.c (process_i386_registers): Process new fields.
515 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
516 unsigned char. Add dw2_regnum and Dw2Inval.
517 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
518 register names.
519 * i386-tbl.h: Re-generate.
520
f03fe4c1
L		 5212008-02-11 H.J. Lu <hongjiu.lu@intel.com>
522
4b6bc8eb 523 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 524 * i386-init.h: Updated.
525
475a2301
L		 5262008-02-11 H.J. Lu <hongjiu.lu@intel.com>
527
528 * i386-gen.c (cpu_flags): Add CpuXsave.
529
530 * i386-opc.h (CpuXsave): New.
4b6bc8eb 531 (CpuLM): Updated.
475a2301
L		 532 (i386_cpu_flags): Add cpuxsave.
533
534 * i386-dis.c (MOD_0FAE_REG_4): New.
535 (RM_0F01_REG_2): Likewise.
536 (MOD_0FAE_REG_5): Updated.
537 (RM_0F01_REG_3): Likewise.
538 (reg_table): Use MOD_0FAE_REG_4.
539 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
540 for xrstor.
541 (rm_table): Add RM_0F01_REG_2.
542
543 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
544 * i386-init.h: Regenerated.
545 * i386-tbl.h: Likewise.
546
595785c6 5472008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 548
595785c6
JB		 549 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
550 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
551 * i386-tbl.h: Re-generate.
552
bb8541b9
L		 5532008-02-04 H.J. Lu <hongjiu.lu@intel.com>
554
555 PR 5715
556 * configure: Regenerated.
557
57b592a3
AN		 5582008-02-04 Adam Nemet <anemet@caviumnetworks.com>
559
560 * mips-dis.c: Update copyright.
561 (mips_arch_choices): Add Octeon.
562 * mips-opc.c: Update copyright.
563 (IOCT): New macro.
564 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
565
930bb4cf
AM		 5662008-01-29 Alan Modra <amodra@bigpond.net.au>
567
568 * ppc-opc.c: Support optional L form mtmsr.
569
82c18208
L		 5702008-01-24 H.J. Lu <hongjiu.lu@intel.com>
571
572 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
573
599121aa
L		 5742008-01-23 H.J. Lu <hongjiu.lu@intel.com>
575
576 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
577 * i386-init.h: Regenerated.
578
80098f51
TG		 5792008-01-23 Tristan Gingold <gingold@adacore.com>
580
581 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
582 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
583
115c7c25
L		 5842008-01-22 H.J. Lu <hongjiu.lu@intel.com>
585
586 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
587 (cpu_flags): Likewise.
588
589 * i386-opc.h (CpuMMX2): Removed.
590 (CpuSSE): Updated.
591
592 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
593 * i386-init.h: Regenerated.
594 * i386-tbl.h: Likewise.
595
6305a203
L		 5962008-01-22 H.J. Lu <hongjiu.lu@intel.com>
597
598 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
599 CPU_SMX_FLAGS.
600 * i386-init.h: Regenerated.
601
fd07a1c8
L		 6022008-01-15 H.J. Lu <hongjiu.lu@intel.com>
603
604 * i386-opc.tbl: Use Qword on movddup.
605 * i386-tbl.h: Regenerated.
606
321fd21e
L		 6072008-01-15 H.J. Lu <hongjiu.lu@intel.com>
608
609 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
610 * i386-tbl.h: Regenerated.
611
4ee52178
L		 6122008-01-15 H.J. Lu <hongjiu.lu@intel.com>
613
614 * i386-dis.c (Mx): New.
615 (PREFIX_0FC3): Likewise.
616 (PREFIX_0FC7_REG_6): Updated.
617 (dis386_twobyte): Use PREFIX_0FC3.
618 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
619 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
620 movntss.
621
5c07affc
L		 6222008-01-14 H.J. Lu <hongjiu.lu@intel.com>
623
624 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
625 (operand_types): Add Mem.
626
627 * i386-opc.h (IntelSyntax): New.
628 * i386-opc.h (Mem): New.
629 (Byte): Updated.
630 (Opcode_Modifier_Max): Updated.
631 (i386_opcode_modifier): Add intelsyntax.
632 (i386_operand_type): Add mem.
633
634 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
635 instructions.
636
637 * i386-reg.tbl: Add size for accumulator.
638
639 * i386-init.h: Regenerated.
640 * i386-tbl.h: Likewise.
641
0d6a2f58
L		 6422008-01-13 H.J. Lu <hongjiu.lu@intel.com>
643
644 * i386-opc.h (Byte): Fix a typo.
645
7d5e4556
L		 6462008-01-12 H.J. Lu <hongjiu.lu@intel.com>
647
648 PR gas/5534
649 * i386-gen.c (operand_type_init): Add Dword to
650 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
651 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
652 Qword and Xmmword.
653 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
654 Xmmword, Unspecified and Anysize.
655 (set_bitfield): Make Mmword an alias of Qword. Make Oword
656 an alias of Xmmword.
657
658 * i386-opc.h (CheckSize): Removed.
659 (Byte): Updated.
660 (Word): Likewise.
661 (Dword): Likewise.
662 (Qword): Likewise.
663 (Xmmword): Likewise.
664 (FWait): Updated.
665 (OTMax): Likewise.
666 (i386_opcode_modifier): Remove checksize, byte, word, dword,
667 qword and xmmword.
668 (Fword): New.
669 (TBYTE): Likewise.
670 (Unspecified): Likewise.
671 (Anysize): Likewise.
672 (i386_operand_type): Add byte, word, dword, fword, qword,
673 tbyte xmmword, unspecified and anysize.
674
675 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
676 Tbyte, Xmmword, Unspecified and Anysize.
677
678 * i386-reg.tbl: Add size for accumulator.
679
680 * i386-init.h: Regenerated.
681 * i386-tbl.h: Likewise.
682
b5b1fc4f
L		 6832008-01-10 H.J. Lu <hongjiu.lu@intel.com>
684
685 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
686 (REG_0F18): Updated.
687 (reg_table): Updated.
688 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
689 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
690
50e8458f
L		 6912008-01-08 H.J. Lu <hongjiu.lu@intel.com>
692
693 * i386-gen.c (set_bitfield): Use fail () on error.
694
3d4d5afa
L		 6952008-01-08 H.J. Lu <hongjiu.lu@intel.com>
696
697 * i386-gen.c (lineno): New.
698 (filename): Likewise.
699 (set_bitfield): Report filename and line numer on error.
700 (process_i386_opcodes): Set filename and update lineno.
701 (process_i386_registers): Likewise.
702
e1d4d893
L		 7032008-01-05 H.J. Lu <hongjiu.lu@intel.com>
704
705 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
706 ATTSyntax.
707
708 * i386-opc.h (IntelMnemonic): Renamed to ..
709 (ATTSyntax): This
710 (Opcode_Modifier_Max): Updated.
711 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
712 and intelsyntax.
713
8944f3c2 714 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 715 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
716 * i386-tbl.h: Regenerated.
717
6f143e4d
L		 7182008-01-04 H.J. Lu <hongjiu.lu@intel.com>
719
720 * i386-gen.c: Update copyright to 2008.
721 * i386-opc.h: Likewise.
722 * i386-opc.tbl: Likewise.
723
724 * i386-init.h: Regenerated.
725 * i386-tbl.h: Likewise.
726
c6add537
L		 7272008-01-04 H.J. Lu <hongjiu.lu@intel.com>
728
729 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
730 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
731 * i386-tbl.h: Regenerated.
732
3629bb00
L		 7332008-01-03 H.J. Lu <hongjiu.lu@intel.com>
734
735 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
736 CpuSSE4_2_Or_ABM.
737 (cpu_flags): Likewise.
738
739 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
740 (CpuSSE4_2_Or_ABM): Likewise.
741 (CpuLM): Updated.
742 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
743
744 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
745 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
746 and CpuPadLock, respectively.
747 * i386-init.h: Regenerated.
748 * i386-tbl.h: Likewise.
749
24995bd6
L		 7502008-01-03 H.J. Lu <hongjiu.lu@intel.com>
751
752 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
753
754 * i386-opc.h (No_xSuf): Removed.
755 (CheckSize): Updated.
756
757 * i386-tbl.h: Regenerated.
758
e0329a22
L		 7592008-01-02 H.J. Lu <hongjiu.lu@intel.com>
760
761 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
762 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
763 CPU_SSE5_FLAGS.
764 (cpu_flags): Add CpuSSE4_2_Or_ABM.
765
766 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
767 (CpuLM): Updated.
768 (i386_cpu_flags): Add cpusse4_2_or_abm.
769
770 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
771 CpuABM|CpuSSE4_2 on popcnt.
772 * i386-init.h: Regenerated.
773 * i386-tbl.h: Likewise.
774
f2a9c676
L		 7752008-01-02 H.J. Lu <hongjiu.lu@intel.com>
776
777 * i386-opc.h: Update comments.
778
d978b5be
L		 7792008-01-02 H.J. Lu <hongjiu.lu@intel.com>
780
781 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
782 * i386-opc.h: Likewise.
783 * i386-opc.tbl: Likewise.
784
582d5edd
L		 7852008-01-02 H.J. Lu <hongjiu.lu@intel.com>
786
787 PR gas/5534
788 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
789 Byte, Word, Dword, QWord and Xmmword.
790
791 * i386-opc.h (No_xSuf): New.
792 (CheckSize): Likewise.
793 (Byte): Likewise.
794 (Word): Likewise.
795 (Dword): Likewise.
796 (QWord): Likewise.
797 (Xmmword): Likewise.
798 (FWait): Updated.
799 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
800 Dword, QWord and Xmmword.
801
802 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
803 used.
804 * i386-tbl.h: Regenerated.
805
3fe15143
MK		 8062008-01-02 Mark Kettenis <kettenis@gnu.org>
807
808 * m88k-dis.c (instructions): Fix fcvt.* instructions.
809 From Miod Vallat.
810
6c7ac64e 811For older changes see ChangeLog-2007
252b5132
RH		 812\f
813Local Variables:
2f6d2f85
NC		 814mode: change-log
815left-margin: 8
816fill-column: 74
252b5132
RH		 817version-control: never
818End:
GDB Binutils - Deliverables
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