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This patch set for the generic BFD a.out backend removes a dead #define and makes...
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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44730156
NC		 12020-06-03 Nelson Chu <nelson.chu@sifive.com>
2
3 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
4 (riscv_get_priv_spec_class): Likewise.
5
3c3d0376
AM		 62020-06-01 Alan Modra <amodra@gmail.com>
7
8 * bpf-desc.c: Regenerate.
9
78c1c354
JM		 102020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
11 David Faust <david.faust@oracle.com>
12
13 * bpf-desc.c: Regenerate.
14 * bpf-opc.h: Likewise.
15 * bpf-opc.c: Likewise.
16 * bpf-dis.c: Likewise.
17
efcf5fb5
AM		 182020-05-28 Alan Modra <amodra@gmail.com>
19
20 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
21 values.
22
ab382d64
AM		 232020-05-28 Alan Modra <amodra@gmail.com>
24
25 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
26 immediates.
27 (print_insn_ns32k): Revert last change.
28
151f5de4
NC		 292020-05-28 Nick Clifton <nickc@redhat.com>
30
31 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
32 static.
33
25e1eca8
SL		 342020-05-26 Sandra Loosemore <sandra@codesourcery.com>
35
36 Fix extraction of signed constants in nios2 disassembler (again).
37
38 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
39 extractions of signed fields.
40
57b17940
SSF		 412020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
42
43 * s390-opc.txt: Relocate vector load/store instructions with
44 additional alignment parameter and change architecture level
45 constraint from z14 to z13.
46
d96bf37b
AM		 472020-05-21 Alan Modra <amodra@gmail.com>
48
49 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
50 * sparc-dis.c: Likewise.
51 * tic4x-dis.c: Likewise.
52 * xtensa-dis.c: Likewise.
53 * bpf-desc.c: Regenerate.
54 * epiphany-desc.c: Regenerate.
55 * fr30-desc.c: Regenerate.
56 * frv-desc.c: Regenerate.
57 * ip2k-desc.c: Regenerate.
58 * iq2000-desc.c: Regenerate.
59 * lm32-desc.c: Regenerate.
60 * m32c-desc.c: Regenerate.
61 * m32r-desc.c: Regenerate.
62 * mep-asm.c: Regenerate.
63 * mep-desc.c: Regenerate.
64 * mt-desc.c: Regenerate.
65 * or1k-desc.c: Regenerate.
66 * xc16x-desc.c: Regenerate.
67 * xstormy16-desc.c: Regenerate.
68
8f595e9b
NC		 692020-05-20 Nelson Chu <nelson.chu@sifive.com>
70
71 * riscv-opc.c (riscv_ext_version_table): The table used to store
72 all information about the supported spec and the corresponding ISA
73 versions. Currently, only Zicsr is supported to verify the
74 correctness of Z sub extension settings. Others will be supported
75 in the future patches.
76 (struct isa_spec_t, isa_specs): List for all supported ISA spec
77 classes and the corresponding strings.
78 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
79 spec class by giving a ISA spec string.
80 * riscv-opc.c (struct priv_spec_t): New structure.
81 (struct priv_spec_t priv_specs): List for all supported privilege spec
82 classes and the corresponding strings.
83 (riscv_get_priv_spec_class): New function. Get the corresponding
84 privilege spec class by giving a spec string.
85 (riscv_get_priv_spec_name): New function. Get the corresponding
86 privilege spec string by giving a CSR version class.
87 * riscv-dis.c: Updated since DECLARE_CSR is changed.
88 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
89 according to the chosen version. Build a hash table riscv_csr_hash to
90 store the valid CSR for the chosen pirv verison. Dump the direct
91 CSR address rather than it's name if it is invalid.
92 (parse_riscv_dis_option_without_args): New function. Parse the options
93 without arguments.
94 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
95 parse the options without arguments first, and then handle the options
96 with arguments. Add the new option -Mpriv-spec, which has argument.
97 * riscv-dis.c (print_riscv_disassembler_options): Add description
98 about the new OBJDUMP option.
99
3d205eb4
PB		 1002020-05-19 Peter Bergner <bergner@linux.ibm.com>
101
102 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
103 WC values on POWER10 sync, dcbf and wait instructions.
104 (insert_pl, extract_pl): New functions.
105 (L2OPT, LS, WC): Use insert_ls and extract_ls.
106 (LS3): New , 3-bit L for sync.
107 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
108 (SC2, PL): New, 2-bit SC and PL for sync and wait.
109 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
110 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
111 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
112 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
113 <wait>: Enable PL operand on POWER10.
114 <dcbf>: Enable L3OPT operand on POWER10.
115 <sync>: Enable SC2 operand on POWER10.
116
a501eb44
SH		 1172020-05-19 Stafford Horne <shorne@gmail.com>
118
119 PR 25184
120 * or1k-asm.c: Regenerate.
121 * or1k-desc.c: Regenerate.
122 * or1k-desc.h: Regenerate.
123 * or1k-dis.c: Regenerate.
124 * or1k-ibld.c: Regenerate.
125 * or1k-opc.c: Regenerate.
126 * or1k-opc.h: Regenerate.
127 * or1k-opinst.c: Regenerate.
128
3b646889
AM		 1292020-05-11 Alan Modra <amodra@gmail.com>
130
131 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
132 xsmaxcqp, xsmincqp.
133
9cc4ce88
AM		 1342020-05-11 Alan Modra <amodra@gmail.com>
135
136 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
137 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
138
5d57bc3f
AM		 1392020-05-11 Alan Modra <amodra@gmail.com>
140
141 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
142
66ef5847
AM		 1432020-05-11 Alan Modra <amodra@gmail.com>
144
145 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
146 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
147
4f3e9537
PB		 1482020-05-11 Peter Bergner <bergner@linux.ibm.com>
149
150 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
151 mnemonics.
152
ec40e91c
AM		 1532020-05-11 Alan Modra <amodra@gmail.com>
154
155 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
156 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
157 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
158 (prefix_opcodes): Add xxeval.
159
d7e97a76
AM		 1602020-05-11 Alan Modra <amodra@gmail.com>
161
162 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
163 xxgenpcvwm, xxgenpcvdm.
164
fdefed7c
AM		 1652020-05-11 Alan Modra <amodra@gmail.com>
166
167 * ppc-opc.c (MP, VXVAM_MASK): Define.
168 (VXVAPS_MASK): Use VXVA_MASK.
169 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
170 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
171 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
172 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
173
aa3c112f
AM		 1742020-05-11 Alan Modra <amodra@gmail.com>
175 Peter Bergner <bergner@linux.ibm.com>
176
177 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
178 New functions.
179 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
180 YMSK2, XA6a, XA6ap, XB6a entries.
181 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
182 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
183 (PPCVSX4): Define.
184 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
185 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
186 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
187 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
188 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
189 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
190 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
191 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
192 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
193 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
194 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
195 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
196 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
197 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
198
6edbfd3b
AM		 1992020-05-11 Alan Modra <amodra@gmail.com>
200
201 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
202 (insert_xts, extract_xts): New functions.
203 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
204 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
205 (VXRC_MASK, VXSH_MASK): Define.
206 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
207 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
208 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
209 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
210 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
211 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
212 xxblendvh, xxblendvw, xxblendvd, xxpermx.
213
c7d7aea2
AM		 2142020-05-11 Alan Modra <amodra@gmail.com>
215
216 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
217 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
218 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
219 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
220 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
221
94ba9882
AM		 2222020-05-11 Alan Modra <amodra@gmail.com>
223
224 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
225 (XTP, DQXP, DQXP_MASK): Define.
226 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
227 (prefix_opcodes): Add plxvp and pstxvp.
228
f4791f1a
AM		 2292020-05-11 Alan Modra <amodra@gmail.com>
230
231 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
232 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
233 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
234
3ff0a5ba
PB		 2352020-05-11 Peter Bergner <bergner@linux.ibm.com>
236
237 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
238
afef4fe9
PB		 2392020-05-11 Peter Bergner <bergner@linux.ibm.com>
240
241 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
242 (L1OPT): Define.
243 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
244
1224c05d
PB		 2452020-05-11 Peter Bergner <bergner@linux.ibm.com>
246
247 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
248
6bbb0c05
AM		 2492020-05-11 Alan Modra <amodra@gmail.com>
250
251 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
252
7c1f4227
AM		 2532020-05-11 Alan Modra <amodra@gmail.com>
254
255 * ppc-dis.c (ppc_opts): Add "power10" entry.
256 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
257 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
258
73199c2b
NC		 2592020-05-11 Nick Clifton <nickc@redhat.com>
260
261 * po/fr.po: Updated French translation.
262
09c1e68a
AC		 2632020-04-30 Alex Coplan <alex.coplan@arm.com>
264
265 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
266 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
267 (operand_general_constraint_met_p): validate
268 AARCH64_OPND_UNDEFINED.
269 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
270 for FLD_imm16_2.
271 * aarch64-asm-2.c: Regenerated.
272 * aarch64-dis-2.c: Regenerated.
273 * aarch64-opc-2.c: Regenerated.
274
9654d51a
NC		 2752020-04-29 Nick Clifton <nickc@redhat.com>
276
277 PR 22699
278 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
279 and SETRC insns.
280
c2e71e57
NC		 2812020-04-29 Nick Clifton <nickc@redhat.com>
282
283 * po/sv.po: Updated Swedish translation.
284
5c936ef5
NC		 2852020-04-29 Nick Clifton <nickc@redhat.com>
286
287 PR 22699
288 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
289 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
290 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
291 IMM0_8U case.
292
bb2a1453
AS		 2932020-04-21 Andreas Schwab <schwab@linux-m68k.org>
294
295 PR 25848
296 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
297 cmpi only on m68020up and cpu32.
298
c2e5c986
SD		 2992020-04-20 Sudakshina Das <sudi.das@arm.com>
300
301 * aarch64-asm.c (aarch64_ins_none): New.
302 * aarch64-asm.h (ins_none): New declaration.
303 * aarch64-dis.c (aarch64_ext_none): New.
304 * aarch64-dis.h (ext_none): New declaration.
305 * aarch64-opc.c (aarch64_print_operand): Update case for
306 AARCH64_OPND_BARRIER_PSB.
307 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
308 (AARCH64_OPERANDS): Update inserter/extracter for
309 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
310 * aarch64-asm-2.c: Regenerated.
311 * aarch64-dis-2.c: Regenerated.
312 * aarch64-opc-2.c: Regenerated.
313
8a6e1d1d
SD		 3142020-04-20 Sudakshina Das <sudi.das@arm.com>
315
316 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
317 (aarch64_feature_ras, RAS): Likewise.
318 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
319 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
320 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
321 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
322 * aarch64-asm-2.c: Regenerated.
323 * aarch64-dis-2.c: Regenerated.
324 * aarch64-opc-2.c: Regenerated.
325
e409955d
FS		 3262020-04-17 Fredrik Strupe <fredrik@strupe.net>
327
328 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
329 (print_insn_neon): Support disassembly of conditional
330 instructions.
331
c54a9b56
DF		 3322020-02-16 David Faust <david.faust@oracle.com>
333
334 * bpf-desc.c: Regenerate.
335 * bpf-desc.h: Likewise.
336 * bpf-opc.c: Regenerate.
337 * bpf-opc.h: Likewise.
338
bb651e8b
CL		 3392020-04-07 Lili Cui <lili.cui@intel.com>
340
341 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
342 (prefix_table): New instructions (see prefixes above).
343 (rm_table): Likewise
344 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
345 CPU_ANY_TSXLDTRK_FLAGS.
346 (cpu_flags): Add CpuTSXLDTRK.
347 * i386-opc.h (enum): Add CpuTSXLDTRK.
348 (i386_cpu_flags): Add cputsxldtrk.
349 * i386-opc.tbl: Add XSUSPLDTRK insns.
350 * i386-init.h: Regenerate.
351 * i386-tbl.h: Likewise.
352
4b27d27c
L		 3532020-04-02 Lili Cui <lili.cui@intel.com>
354
355 * i386-dis.c (prefix_table): New instructions serialize.
356 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
357 CPU_ANY_SERIALIZE_FLAGS.
358 (cpu_flags): Add CpuSERIALIZE.
359 * i386-opc.h (enum): Add CpuSERIALIZE.
360 (i386_cpu_flags): Add cpuserialize.
361 * i386-opc.tbl: Add SERIALIZE insns.
362 * i386-init.h: Regenerate.
363 * i386-tbl.h: Likewise.
364
832a5807
AM		 3652020-03-26 Alan Modra <amodra@gmail.com>
366
367 * disassemble.h (opcodes_assert): Declare.
368 (OPCODES_ASSERT): Define.
369 * disassemble.c: Don't include assert.h. Include opintl.h.
370 (opcodes_assert): New function.
371 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
372 (bfd_h8_disassemble): Reduce size of data array. Correctly
373 calculate maxlen. Omit insn decoding when insn length exceeds
374 maxlen. Exit from nibble loop when looking for E, before
375 accessing next data byte. Move processing of E outside loop.
376 Replace tests of maxlen in loop with assertions.
377
4c4addbe
AM		 3782020-03-26 Alan Modra <amodra@gmail.com>
379
380 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
381
a18cd0ca
AM		 3822020-03-25 Alan Modra <amodra@gmail.com>
383
384 * z80-dis.c (suffix): Init mybuf.
385
57cb32b3
AM		 3862020-03-22 Alan Modra <amodra@gmail.com>
387
388 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
389 successflly read from section.
390
beea5cc1
AM		 3912020-03-22 Alan Modra <amodra@gmail.com>
392
393 * arc-dis.c (find_format): Use ISO C string concatenation rather
394 than line continuation within a string. Don't access needs_limm
395 before testing opcode != NULL.
396
03704c77
AM		 3972020-03-22 Alan Modra <amodra@gmail.com>
398
399 * ns32k-dis.c (print_insn_arg): Update comment.
400 (print_insn_ns32k): Reduce size of index_offset array, and
401 initialize, passing -1 to print_insn_arg for args that are not
402 an index. Don't exit arg loop early. Abort on bad arg number.
403
d1023b5d
AM		 4042020-03-22 Alan Modra <amodra@gmail.com>
405
406 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
407 * s12z-opc.c: Formatting.
408 (operands_f): Return an int.
409 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
410 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
411 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
412 (exg_sex_discrim): Likewise.
413 (create_immediate_operand, create_bitfield_operand),
414 (create_register_operand_with_size, create_register_all_operand),
415 (create_register_all16_operand, create_simple_memory_operand),
416 (create_memory_operand, create_memory_auto_operand): Don't
417 segfault on malloc failure.
418 (z_ext24_decode): Return an int status, negative on fail, zero
419 on success.
420 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
421 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
422 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
423 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
424 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
425 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
426 (loop_primitive_decode, shift_decode, psh_pul_decode),
427 (bit_field_decode): Similarly.
428 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
429 to return value, update callers.
430 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
431 Don't segfault on NULL operand.
432 (decode_operation): Return OP_INVALID on first fail.
433 (decode_s12z): Check all reads, returning -1 on fail.
434
340f3ac8
AM		 4352020-03-20 Alan Modra <amodra@gmail.com>
436
437 * metag-dis.c (print_insn_metag): Don't ignore status from
438 read_memory_func.
439
fe90ae8a
AM		 4402020-03-20 Alan Modra <amodra@gmail.com>
441
442 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
443 Initialize parts of buffer not written when handling a possible
444 2-byte insn at end of section. Don't attempt decoding of such
445 an insn by the 4-byte machinery.
446
833d919c
AM		 4472020-03-20 Alan Modra <amodra@gmail.com>
448
449 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
450 partially filled buffer. Prevent lookup of 4-byte insns when
451 only VLE 2-byte insns are possible due to section size. Print
452 ".word" rather than ".long" for 2-byte leftovers.
453
327ef784
NC		 4542020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
455
456 PR 25641
457 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
458
1673df32
JB		 4592020-03-13 Jan Beulich <jbeulich@suse.com>
460
461 * i386-dis.c (X86_64_0D): Rename to ...
462 (X86_64_0E): ... this.
463
384f3689
L		 4642020-03-09 H.J. Lu <hongjiu.lu@intel.com>
465
466 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
467 * Makefile.in: Regenerated.
468
865e2027
JB		 4692020-03-09 Jan Beulich <jbeulich@suse.com>
470
471 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
472 3-operand pseudos.
473 * i386-tbl.h: Re-generate.
474
2f13234b
JB		 4752020-03-09 Jan Beulich <jbeulich@suse.com>
476
477 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
478 vprot*, vpsha*, and vpshl*.
479 * i386-tbl.h: Re-generate.
480
3fabc179
JB		 4812020-03-09 Jan Beulich <jbeulich@suse.com>
482
483 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
484 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
485 * i386-tbl.h: Re-generate.
486
3677e4c1
JB		 4872020-03-09 Jan Beulich <jbeulich@suse.com>
488
489 * i386-gen.c (set_bitfield): Ignore zero-length field names.
490 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
491 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
492 * i386-tbl.h: Re-generate.
493
4c4898e8
JB		 4942020-03-09 Jan Beulich <jbeulich@suse.com>
495
496 * i386-gen.c (struct template_arg, struct template_instance,
497 struct template_param, struct template, templates,
498 parse_template, expand_templates): New.
499 (process_i386_opcodes): Various local variables moved to
500 expand_templates. Call parse_template and expand_templates.
501 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
502 * i386-tbl.h: Re-generate.
503
bc49bfd8
JB		 5042020-03-06 Jan Beulich <jbeulich@suse.com>
505
506 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
507 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
508 register and memory source templates. Replace VexW= by VexW*
509 where applicable.
510 * i386-tbl.h: Re-generate.
511
4873e243
JB		 5122020-03-06 Jan Beulich <jbeulich@suse.com>
513
514 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
515 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
516 * i386-tbl.h: Re-generate.
517
672a349b
JB		 5182020-03-06 Jan Beulich <jbeulich@suse.com>
519
520 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
521 * i386-tbl.h: Re-generate.
522
4ed21b58
JB		 5232020-03-06 Jan Beulich <jbeulich@suse.com>
524
525 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
526 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
527 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
528 VexW0 on SSE2AVX variants.
529 (vmovq): Drop NoRex64 from XMM/XMM variants.
530 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
531 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
532 applicable use VexW0.
533 * i386-tbl.h: Re-generate.
534
643bb870
JB		 5352020-03-06 Jan Beulich <jbeulich@suse.com>
536
537 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
538 * i386-opc.h (Rex64): Delete.
539 (struct i386_opcode_modifier): Remove rex64 field.
540 * i386-opc.tbl (crc32): Drop Rex64.
541 Replace Rex64 with Size64 everywhere else.
542 * i386-tbl.h: Re-generate.
543
a23b33b3
JB		 5442020-03-06 Jan Beulich <jbeulich@suse.com>
545
546 * i386-dis.c (OP_E_memory): Exclude recording of used address
547 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
548 addressed memory operands for MPX insns.
549
a0497384
JB		 5502020-03-06 Jan Beulich <jbeulich@suse.com>
551
552 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
553 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
554 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
555 (ptwrite): Split into non-64-bit and 64-bit forms.
556 * i386-tbl.h: Re-generate.
557
b630c145
JB		 5582020-03-06 Jan Beulich <jbeulich@suse.com>
559
560 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
561 template.
562 * i386-tbl.h: Re-generate.
563
a847e322
JB		 5642020-03-04 Jan Beulich <jbeulich@suse.com>
565
566 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
567 (prefix_table): Move vmmcall here. Add vmgexit.
568 (rm_table): Replace vmmcall entry by prefix_table[] escape.
569 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
570 (cpu_flags): Add CpuSEV_ES entry.
571 * i386-opc.h (CpuSEV_ES): New.
572 (union i386_cpu_flags): Add cpusev_es field.
573 * i386-opc.tbl (vmgexit): New.
574 * i386-init.h, i386-tbl.h: Re-generate.
575
3cd7f3e3
L		 5762020-03-03 H.J. Lu <hongjiu.lu@intel.com>
577
578 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
579 with MnemonicSize.
580 * i386-opc.h (IGNORESIZE): New.
581 (DEFAULTSIZE): Likewise.
582 (IgnoreSize): Removed.
583 (DefaultSize): Likewise.
584 (MnemonicSize): New.
585 (i386_opcode_modifier): Replace ignoresize/defaultsize with
586 mnemonicsize.
587 * i386-opc.tbl (IgnoreSize): New.
588 (DefaultSize): Likewise.
589 * i386-tbl.h: Regenerated.
590
b8ba1385
SB		 5912020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
592
593 PR 25627
594 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
595 instructions.
596
10d97a0f
L		 5972020-03-03 H.J. Lu <hongjiu.lu@intel.com>
598
599 PR gas/25622
600 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
601 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
602 * i386-tbl.h: Regenerated.
603
dc1e8a47
AM		 6042020-02-26 Alan Modra <amodra@gmail.com>
605
606 * aarch64-asm.c: Indent labels correctly.
607 * aarch64-dis.c: Likewise.
608 * aarch64-gen.c: Likewise.
609 * aarch64-opc.c: Likewise.
610 * alpha-dis.c: Likewise.
611 * i386-dis.c: Likewise.
612 * nds32-asm.c: Likewise.
613 * nfp-dis.c: Likewise.
614 * visium-dis.c: Likewise.
615
265b4673
CZ		 6162020-02-25 Claudiu Zissulescu <claziss@gmail.com>
617
618 * arc-regs.h (int_vector_base): Make it available for all ARC
619 CPUs.
620
bd0cf5a6
NC		 6212020-02-20 Nelson Chu <nelson.chu@sifive.com>
622
623 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
624 changed.
625
fa164239
JW		 6262020-02-19 Nelson Chu <nelson.chu@sifive.com>
627
628 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
629 c.mv/c.li if rs1 is zero.
630
272a84b1
L		 6312020-02-17 H.J. Lu <hongjiu.lu@intel.com>
632
633 * i386-gen.c (cpu_flag_init): Replace CpuABM with
634 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
635 CPU_POPCNT_FLAGS.
636 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
637 * i386-opc.h (CpuABM): Removed.
638 (CpuPOPCNT): New.
639 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
640 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
641 popcnt. Remove CpuABM from lzcnt.
642 * i386-init.h: Regenerated.
643 * i386-tbl.h: Likewise.
644
1f730c46
JB		 6452020-02-17 Jan Beulich <jbeulich@suse.com>
646
647 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
648 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
649 VexW1 instead of open-coding them.
650 * i386-tbl.h: Re-generate.
651
c8f8eebc
JB		 6522020-02-17 Jan Beulich <jbeulich@suse.com>
653
654 * i386-opc.tbl (AddrPrefixOpReg): Define.
655 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
656 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
657 templates. Drop NoRex64.
658 * i386-tbl.h: Re-generate.
659
b9915cbc
JB		 6602020-02-17 Jan Beulich <jbeulich@suse.com>
661
662 PR gas/6518
663 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
664 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
665 into Intel syntax instance (with Unpsecified) and AT&T one
666 (without).
667 (vcvtneps2bf16): Likewise, along with folding the two so far
668 separate ones.
669 * i386-tbl.h: Re-generate.
670
ce504911
L		 6712020-02-16 H.J. Lu <hongjiu.lu@intel.com>
672
673 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
674 CPU_ANY_SSE4A_FLAGS.
675
dabec65d
AM		 6762020-02-17 Alan Modra <amodra@gmail.com>
677
678 * i386-gen.c (cpu_flag_init): Correct last change.
679
af5c13b0
L		 6802020-02-16 H.J. Lu <hongjiu.lu@intel.com>
681
682 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
683 CPU_ANY_SSE4_FLAGS.
684
6867aac0
L		 6852020-02-14 H.J. Lu <hongjiu.lu@intel.com>
686
687 * i386-opc.tbl (movsx): Remove Intel syntax comments.
688 (movzx): Likewise.
689
65fca059
JB		 6902020-02-14 Jan Beulich <jbeulich@suse.com>
691
692 PR gas/25438
693 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
694 destination for Cpu64-only variant.
695 (movzx): Fold patterns.
696 * i386-tbl.h: Re-generate.
697
7deea9aa
JB		 6982020-02-13 Jan Beulich <jbeulich@suse.com>
699
700 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
701 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
702 CPU_ANY_SSE4_FLAGS entry.
703 * i386-init.h: Re-generate.
704
6c0946d0
JB		 7052020-02-12 Jan Beulich <jbeulich@suse.com>
706
707 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
708 with Unspecified, making the present one AT&T syntax only.
709 * i386-tbl.h: Re-generate.
710
ddb56fe6
JB		 7112020-02-12 Jan Beulich <jbeulich@suse.com>
712
713 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
714 * i386-tbl.h: Re-generate.
715
5990e377
JB		 7162020-02-12 Jan Beulich <jbeulich@suse.com>
717
718 PR gas/24546
719 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
720 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
721 Amd64 and Intel64 templates.
722 (call, jmp): Likewise for far indirect variants. Dro
723 Unspecified.
724 * i386-tbl.h: Re-generate.
725
50128d0c
JB		 7262020-02-11 Jan Beulich <jbeulich@suse.com>
727
728 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
729 * i386-opc.h (ShortForm): Delete.
730 (struct i386_opcode_modifier): Remove shortform field.
731 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
732 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
733 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
734 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
735 Drop ShortForm.
736 * i386-tbl.h: Re-generate.
737
1e05b5c4
JB		 7382020-02-11 Jan Beulich <jbeulich@suse.com>
739
740 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
741 fucompi): Drop ShortForm from operand-less templates.
742 * i386-tbl.h: Re-generate.
743
2f5dd314
AM		 7442020-02-11 Alan Modra <amodra@gmail.com>
745
746 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
747 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
748 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
749 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
750 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
751
5aae9ae9
MM		 7522020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
753
754 * arm-dis.c (print_insn_cde): Define 'V' parse character.
755 (cde_opcodes): Add VCX* instructions.
756
4934a27c
MM		 7572020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
758 Matthew Malcomson <matthew.malcomson@arm.com>
759
760 * arm-dis.c (struct cdeopcode32): New.
761 (CDE_OPCODE): New macro.
762 (cde_opcodes): New disassembly table.
763 (regnames): New option to table.
764 (cde_coprocs): New global variable.
765 (print_insn_cde): New
766 (print_insn_thumb32): Use print_insn_cde.
767 (parse_arm_disassembler_options): Parse coprocN args.
768
4b5aaf5f
L		 7692020-02-10 H.J. Lu <hongjiu.lu@intel.com>
770
771 PR gas/25516
772 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
773 with ISA64.
774 * i386-opc.h (AMD64): Removed.
775 (Intel64): Likewose.
776 (AMD64): New.
777 (INTEL64): Likewise.
778 (INTEL64ONLY): Likewise.
779 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
780 * i386-opc.tbl (Amd64): New.
781 (Intel64): Likewise.
782 (Intel64Only): Likewise.
783 Replace AMD64 with Amd64. Update sysenter/sysenter with
784 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
785 * i386-tbl.h: Regenerated.
786
9fc0b501
SB		 7872020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
788
789 PR 25469
790 * z80-dis.c: Add support for GBZ80 opcodes.
791
c5d7be0c
AM		 7922020-02-04 Alan Modra <amodra@gmail.com>
793
794 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
795
44e4546f
AM		 7962020-02-03 Alan Modra <amodra@gmail.com>
797
798 * m32c-ibld.c: Regenerate.
799
b2b1453a
AM		 8002020-02-01 Alan Modra <amodra@gmail.com>
801
802 * frv-ibld.c: Regenerate.
803
4102be5c
JB		 8042020-01-31 Jan Beulich <jbeulich@suse.com>
805
806 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
807 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
808 (OP_E_memory): Replace xmm_mdq_mode case label by
809 vex_scalar_w_dq_mode one.
810 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
811
825bd36c
JB		 8122020-01-31 Jan Beulich <jbeulich@suse.com>
813
814 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
815 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
816 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
817 (intel_operand_size): Drop vex_w_dq_mode case label.
818
c3036ed0
RS		 8192020-01-31 Richard Sandiford <richard.sandiford@arm.com>
820
821 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
822 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
823
0c115f84
AM		 8242020-01-30 Alan Modra <amodra@gmail.com>
825
826 * m32c-ibld.c: Regenerate.
827
bd434cc4
JM		 8282020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
829
830 * bpf-opc.c: Regenerate.
831
aeab2b26
JB		 8322020-01-30 Jan Beulich <jbeulich@suse.com>
833
834 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
835 (dis386): Use them to replace C2/C3 table entries.
836 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
837 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
838 ones. Use Size64 instead of DefaultSize on Intel64 ones.
839 * i386-tbl.h: Re-generate.
840
62b3f548
JB		 8412020-01-30 Jan Beulich <jbeulich@suse.com>
842
843 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
844 forms.
845 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
846 DefaultSize.
847 * i386-tbl.h: Re-generate.
848
1bd8ae10
AM		 8492020-01-30 Alan Modra <amodra@gmail.com>
850
851 * tic4x-dis.c (tic4x_dp): Make unsigned.
852
bc31405e
L		 8532020-01-27 H.J. Lu <hongjiu.lu@intel.com>
854 Jan Beulich <jbeulich@suse.com>
855
856 PR binutils/25445
857 * i386-dis.c (MOVSXD_Fixup): New function.
858 (movsxd_mode): New enum.
859 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
860 (intel_operand_size): Handle movsxd_mode.
861 (OP_E_register): Likewise.
862 (OP_G): Likewise.
863 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
864 register on movsxd. Add movsxd with 16-bit destination register
865 for AMD64 and Intel64 ISAs.
866 * i386-tbl.h: Regenerated.
867
7568c93b
TC		 8682020-01-27 Tamar Christina <tamar.christina@arm.com>
869
870 PR 25403
871 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
872 * aarch64-asm-2.c: Regenerate
873 * aarch64-dis-2.c: Likewise.
874 * aarch64-opc-2.c: Likewise.
875
c006a730
JB		 8762020-01-21 Jan Beulich <jbeulich@suse.com>
877
878 * i386-opc.tbl (sysret): Drop DefaultSize.
879 * i386-tbl.h: Re-generate.
880
c906a69a
JB		 8812020-01-21 Jan Beulich <jbeulich@suse.com>
882
883 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
884 Dword.
885 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
886 * i386-tbl.h: Re-generate.
887
26916852
NC		 8882020-01-20 Nick Clifton <nickc@redhat.com>
889
890 * po/de.po: Updated German translation.
891 * po/pt_BR.po: Updated Brazilian Portuguese translation.
892 * po/uk.po: Updated Ukranian translation.
893
4d6cbb64
AM		 8942020-01-20 Alan Modra <amodra@gmail.com>
895
896 * hppa-dis.c (fput_const): Remove useless cast.
897
2bddb71a
AM		 8982020-01-20 Alan Modra <amodra@gmail.com>
899
900 * arm-dis.c (print_insn_arm): Wrap 'T' value.
901
1b1bb2c6
NC		 9022020-01-18 Nick Clifton <nickc@redhat.com>
903
904 * configure: Regenerate.
905 * po/opcodes.pot: Regenerate.
906
ae774686
NC		 9072020-01-18 Nick Clifton <nickc@redhat.com>
908
909 Binutils 2.34 branch created.
910
07f1f3aa
CB		 9112020-01-17 Christian Biesinger <cbiesinger@google.com>
912
913 * opintl.h: Fix spelling error (seperate).
914
42e04b36
L		 9152020-01-17 H.J. Lu <hongjiu.lu@intel.com>
916
917 * i386-opc.tbl: Add {vex} pseudo prefix.
918 * i386-tbl.h: Regenerated.
919
2da2eaf4
AV		 9202020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
921
922 PR 25376
923 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
924 (neon_opcodes): Likewise.
925 (select_arm_features): Make sure we enable MVE bits when selecting
926 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
927 any architecture.
928
d0849eed
JB		 9292020-01-16 Jan Beulich <jbeulich@suse.com>
930
931 * i386-opc.tbl: Drop stale comment from XOP section.
932
9cf70a44
JB		 9332020-01-16 Jan Beulich <jbeulich@suse.com>
934
935 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
936 (extractps): Add VexWIG to SSE2AVX forms.
937 * i386-tbl.h: Re-generate.
938
4814632e
JB		 9392020-01-16 Jan Beulich <jbeulich@suse.com>
940
941 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
942 Size64 from and use VexW1 on SSE2AVX forms.
943 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
944 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
945 * i386-tbl.h: Re-generate.
946
aad09917
AM		 9472020-01-15 Alan Modra <amodra@gmail.com>
948
949 * tic4x-dis.c (tic4x_version): Make unsigned long.
950 (optab, optab_special, registernames): New file scope vars.
951 (tic4x_print_register): Set up registernames rather than
952 malloc'd registertable.
953 (tic4x_disassemble): Delete optable and optable_special. Use
954 optab and optab_special instead. Throw away old optab,
955 optab_special and registernames when info->mach changes.
956
7a6bf3be
SB		 9572020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
958
959 PR 25377
960 * z80-dis.c (suffix): Use .db instruction to generate double
961 prefix.
962
ca1eaac0
AM		 9632020-01-14 Alan Modra <amodra@gmail.com>
964
965 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
966 values to unsigned before shifting.
967
1d67fe3b
TT		 9682020-01-13 Thomas Troeger <tstroege@gmx.de>
969
970 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
971 flow instructions.
972 (print_insn_thumb16, print_insn_thumb32): Likewise.
973 (print_insn): Initialize the insn info.
974 * i386-dis.c (print_insn): Initialize the insn info fields, and
975 detect jumps.
976
5e4f7e05
CZ		 9772012-01-13 Claudiu Zissulescu <claziss@gmail.com>
978
979 * arc-opc.c (C_NE): Make it required.
980
b9fe6b8a
CZ		 9812012-01-13 Claudiu Zissulescu <claziss@gmail.com>
982
983 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
984 reserved register name.
985
90dee485
AM		 9862020-01-13 Alan Modra <amodra@gmail.com>
987
988 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
989 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
990
febda64f
AM		 9912020-01-13 Alan Modra <amodra@gmail.com>
992
993 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
994 result of wasm_read_leb128 in a uint64_t and check that bits
995 are not lost when copying to other locals. Use uint32_t for
996 most locals. Use PRId64 when printing int64_t.
997
df08b588
AM		 9982020-01-13 Alan Modra <amodra@gmail.com>
999
1000 * score-dis.c: Formatting.
1001 * score7-dis.c: Formatting.
1002
b2c759ce
AM		 10032020-01-13 Alan Modra <amodra@gmail.com>
1004
1005 * score-dis.c (print_insn_score48): Use unsigned variables for
1006 unsigned values. Don't left shift negative values.
1007 (print_insn_score32): Likewise.
1008 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1009
5496abe1
AM		 10102020-01-13 Alan Modra <amodra@gmail.com>
1011
1012 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1013
202e762b
AM		 10142020-01-13 Alan Modra <amodra@gmail.com>
1015
1016 * fr30-ibld.c: Regenerate.
1017
7ef412cf
AM		 10182020-01-13 Alan Modra <amodra@gmail.com>
1019
1020 * xgate-dis.c (print_insn): Don't left shift signed value.
1021 (ripBits): Formatting, use 1u.
1022
7f578b95
AM		 10232020-01-10 Alan Modra <amodra@gmail.com>
1024
1025 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1026 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1027
441af85b
AM		 10282020-01-10 Alan Modra <amodra@gmail.com>
1029
1030 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1031 and XRREG value earlier to avoid a shift with negative exponent.
1032 * m10200-dis.c (disassemble): Similarly.
1033
bce58db4
NC		 10342020-01-09 Nick Clifton <nickc@redhat.com>
1035
1036 PR 25224
1037 * z80-dis.c (ld_ii_ii): Use correct cast.
1038
40c75bc8
SB		 10392020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1040
1041 PR 25224
1042 * z80-dis.c (ld_ii_ii): Use character constant when checking
1043 opcode byte value.
1044
d835a58b
JB		 10452020-01-09 Jan Beulich <jbeulich@suse.com>
1046
1047 * i386-dis.c (SEP_Fixup): New.
1048 (SEP): Define.
1049 (dis386_twobyte): Use it for sysenter/sysexit.
1050 (enum x86_64_isa): Change amd64 enumerator to value 1.
1051 (OP_J): Compare isa64 against intel64 instead of amd64.
1052 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1053 forms.
1054 * i386-tbl.h: Re-generate.
1055
030a2e78
AM		 10562020-01-08 Alan Modra <amodra@gmail.com>
1057
1058 * z8k-dis.c: Include libiberty.h
1059 (instr_data_s): Make max_fetched unsigned.
1060 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1061 Don't exceed byte_info bounds.
1062 (output_instr): Make num_bytes unsigned.
1063 (unpack_instr): Likewise for nibl_count and loop.
1064 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1065 idx unsigned.
1066 * z8k-opc.h: Regenerate.
1067
bb82aefe
SV		 10682020-01-07 Shahab Vahedi <shahab@synopsys.com>
1069
1070 * arc-tbl.h (llock): Use 'LLOCK' as class.
1071 (llockd): Likewise.
1072 (scond): Use 'SCOND' as class.
1073 (scondd): Likewise.
1074 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1075 (scondd): Likewise.
1076
cc6aa1a6
AM		 10772020-01-06 Alan Modra <amodra@gmail.com>
1078
1079 * m32c-ibld.c: Regenerate.
1080
660e62b1
AM		 10812020-01-06 Alan Modra <amodra@gmail.com>
1082
1083 PR 25344
1084 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1085 Peek at next byte to prevent recursion on repeated prefix bytes.
1086 Ensure uninitialised "mybuf" is not accessed.
1087 (print_insn_z80): Don't zero n_fetch and n_used here,..
1088 (print_insn_z80_buf): ..do it here instead.
1089
c9ae58fe
AM		 10902020-01-04 Alan Modra <amodra@gmail.com>
1091
1092 * m32r-ibld.c: Regenerate.
1093
5f57d4ec
AM		 10942020-01-04 Alan Modra <amodra@gmail.com>
1095
1096 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1097
2c5c1196
AM		 10982020-01-04 Alan Modra <amodra@gmail.com>
1099
1100 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1101
2e98c6c5
AM		 11022020-01-04 Alan Modra <amodra@gmail.com>
1103
1104 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1105
567dfba2
JB		 11062020-01-03 Jan Beulich <jbeulich@suse.com>
1107
5437a02a
JB		 1108 * aarch64-tbl.h (aarch64_opcode_table): Use
1109 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1110
11112020-01-03 Jan Beulich <jbeulich@suse.com>
1112
1113 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1114 forms of SUDOT and USDOT.
1115
8c45011a
JB		 11162020-01-03 Jan Beulich <jbeulich@suse.com>
1117
5437a02a 1118 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1119 uzip{1,2}.
1120 * opcodes/aarch64-dis-2.c: Re-generate.
1121
f4950f76
JB		 11222020-01-03 Jan Beulich <jbeulich@suse.com>
1123
5437a02a 1124 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1125 FMMLA encoding.
1126 * opcodes/aarch64-dis-2.c: Re-generate.
1127
6655dba2
SB		 11282020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1129
1130 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1131
b14ce8bf
AM		 11322020-01-01 Alan Modra <amodra@gmail.com>
1133
1134 Update year range in copyright notice of all files.
1135
0b114740 1136For older changes see ChangeLog-2019
3499769a 1137\f
0b114740 1138Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1139
1140Copying and distribution of this file, with or without modification,
1141are permitted in any medium without royalty provided the copyright
1142notice and this notice are preserved.
1143
1144Local Variables:
1145mode: change-log
1146left-margin: 8
1147fill-column: 74
1148version-control: never
1149End:
GDB Binutils - Deliverables
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