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Add --decompress option to readelf to decompress sections before they are dumped.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4bc0608a
PB		 12015-05-14 Peter Bergner <bergner@vnet.ibm.com>
2
3 * ppc-opc.c (IH) New define.
4 (powerpc_opcodes) <wait>: Do not enable for POWER7.
5 <tlbie>: Add RS operand for POWER7.
6 <slbia>: Add IH operand for POWER6.
7
70cead07
L		 82015-05-11 H.J. Lu <hongjiu.lu@intel.com>
9
10 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
11 direct branch.
12 (jmp): Likewise.
13 * i386-tbl.h: Regenerated.
14
7b6d09fb
L		 152015-05-11 H.J. Lu <hongjiu.lu@intel.com>
16
17 * configure.ac: Support bfd_iamcu_arch.
18 * disassemble.c (disassembler): Support bfd_iamcu_arch.
19 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
20 CPU_IAMCU_COMPAT_FLAGS.
21 (cpu_flags): Add CpuIAMCU.
22 * i386-opc.h (CpuIAMCU): New.
23 (i386_cpu_flags): Add cpuiamcu.
24 * configure: Regenerated.
25 * i386-init.h: Likewise.
26 * i386-tbl.h: Likewise.
27
31955f99
L		 282015-05-08 H.J. Lu <hongjiu.lu@intel.com>
29
30 PR binutis/18386
31 * i386-dis.c (X86_64_E8): New.
32 (X86_64_E9): Likewise.
33 Update comments on 'T', 'U', 'V'. Add comments for '^'.
34 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
35 (x86_64_table): Add X86_64_E8 and X86_64_E9.
36 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
37 (putop): Handle '^'.
38 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
39 REX_W.
40
0952813b
DD		 412015-04-30 DJ Delorie <dj@redhat.com>
42
43 * disassemble.c (disassembler): Choose suitable disassembler based
44 on E_ABI.
45 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
46 it to decode mul/div insns.
47 * rl78-decode.c: Regenerate.
48 * rl78-dis.c (print_insn_rl78): Rename to...
49 (print_insn_rl78_common): ...this, take ISA parameter.
50 (print_insn_rl78): New.
51 (print_insn_rl78_g10): New.
52 (print_insn_rl78_g13): New.
53 (print_insn_rl78_g14): New.
54 (rl78_get_disassembler): New.
55
f9d3ecaa
NC		 562015-04-29 Nick Clifton <nickc@redhat.com>
57
58 * po/fr.po: Updated French translation.
59
4fff86c5
PB		 602015-04-27 Peter Bergner <bergner@vnet.ibm.com>
61
62 * ppc-opc.c (DCBT_EO): New define.
63 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
64 <lharx>: Likewise.
65 <stbcx.>: Likewise.
66 <sthcx.>: Likewise.
67 <waitrsv>: Do not enable for POWER7 and later.
68 <waitimpl>: Likewise.
69 <dcbt>: Default to the two operand form of the instruction for all
70 "old" cpus. For "new" cpus, use the operand ordering that matches
71 whether the cpu is server or embedded.
72 <dcbtst>: Likewise.
73
3b78cfe1
AK		 742015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
75
76 * s390-opc.c: New instruction type VV0UU2.
77 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
78 and WFC.
79
04d824a4
JB		 802015-04-23 Jan Beulich <jbeulich@suse.com>
81
82 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
83 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
84 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
85 (vfpclasspd, vfpclassps): Add %XZ.
86
09708981
L		 872015-04-15 H.J. Lu <hongjiu.lu@intel.com>
88
89 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
90 (PREFIX_UD_REPZ): Likewise.
91 (PREFIX_UD_REPNZ): Likewise.
92 (PREFIX_UD_DATA): Likewise.
93 (PREFIX_UD_ADDR): Likewise.
94 (PREFIX_UD_LOCK): Likewise.
95
3888916d
L		 962015-04-15 H.J. Lu <hongjiu.lu@intel.com>
97
98 * i386-dis.c (prefix_requirement): Removed.
99 (print_insn): Don't set prefix_requirement. Check
100 dp->prefix_requirement instead of prefix_requirement.
101
f24bcbaa
L		 1022015-04-15 H.J. Lu <hongjiu.lu@intel.com>
103
104 PR binutils/17898
105 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
106 (PREFIX_MOD_0_0FC7_REG_6): This.
107 (PREFIX_MOD_3_0FC7_REG_6): New.
108 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
109 (prefix_table): Replace PREFIX_0FC7_REG_6 with
110 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
111 PREFIX_MOD_3_0FC7_REG_7.
112 (mod_table): Replace PREFIX_0FC7_REG_6 with
113 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
114 PREFIX_MOD_3_0FC7_REG_7.
115
507bd325
L		 1162015-04-15 H.J. Lu <hongjiu.lu@intel.com>
117
118 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
119 (PREFIX_MANDATORY_REPNZ): Likewise.
120 (PREFIX_MANDATORY_DATA): Likewise.
121 (PREFIX_MANDATORY_ADDR): Likewise.
122 (PREFIX_MANDATORY_LOCK): Likewise.
123 (PREFIX_MANDATORY): Likewise.
124 (PREFIX_UD_SHIFT): Set to 8
125 (PREFIX_UD_REPZ): Updated.
126 (PREFIX_UD_REPNZ): Likewise.
127 (PREFIX_UD_DATA): Likewise.
128 (PREFIX_UD_ADDR): Likewise.
129 (PREFIX_UD_LOCK): Likewise.
130 (PREFIX_IGNORED_SHIFT): New.
131 (PREFIX_IGNORED_REPZ): Likewise.
132 (PREFIX_IGNORED_REPNZ): Likewise.
133 (PREFIX_IGNORED_DATA): Likewise.
134 (PREFIX_IGNORED_ADDR): Likewise.
135 (PREFIX_IGNORED_LOCK): Likewise.
136 (PREFIX_OPCODE): Likewise.
137 (PREFIX_IGNORED): Likewise.
138 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
139 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
140 (three_byte_table): Likewise.
141 (mod_table): Likewise.
142 (mandatory_prefix): Renamed to ...
143 (prefix_requirement): This.
144 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
145 Update PREFIX_90 entry.
146 (get_valid_dis386): Check prefix_requirement to see if a prefix
147 should be ignored.
148 (print_insn): Replace mandatory_prefix with prefix_requirement.
149
f0fba320
RL		 1502015-04-15 Renlin Li <renlin.li@arm.com>
151
152 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
153 use it for ssat and ssat16.
154 (print_insn_thumb32): Add handle case for 'D' control code.
155
bf890a93
IT		 1562015-04-06 Ilya Tocar <ilya.tocar@intel.com>
157 H.J. Lu <hongjiu.lu@intel.com>
158
159 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
160 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
161 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
162 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
163 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
164 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
165 Fill prefix_requirement field.
166 (struct dis386): Add prefix_requirement field.
167 (dis386): Fill prefix_requirement field.
168 (dis386_twobyte): Ditto.
169 (twobyte_has_mandatory_prefix_: Remove.
170 (reg_table): Fill prefix_requirement field.
171 (prefix_table): Ditto.
172 (x86_64_table): Ditto.
173 (three_byte_table): Ditto.
174 (xop_table): Ditto.
175 (vex_table): Ditto.
176 (vex_len_table): Ditto.
177 (vex_w_table): Ditto.
178 (mod_table): Ditto.
179 (bad_opcode): Ditto.
180 (print_insn): Use prefix_requirement.
181 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
182 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
183 (float_reg): Ditto.
184
2f783c1f
MF		 1852015-03-30 Mike Frysinger <vapier@gentoo.org>
186
187 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
188
b9d94d62
L		 1892015-03-29 H.J. Lu <hongjiu.lu@intel.com>
190
191 * Makefile.in: Regenerated.
192
27c49e9a
AB		 1932015-03-25 Anton Blanchard <anton@samba.org>
194
195 * ppc-dis.c (disassemble_init_powerpc): Only initialise
196 powerpc_opcd_indices and vle_opcd_indices once.
197
c4e676f1
AB		 1982015-03-25 Anton Blanchard <anton@samba.org>
199
200 * ppc-opc.c (powerpc_opcodes): Add slbfee.
201
823d2571
TG		 2022015-03-24 Terry Guo <terry.guo@arm.com>
203
204 * arm-dis.c (opcode32): Updated to use new arm feature struct.
205 (opcode16): Likewise.
206 (coprocessor_opcodes): Replace bit with feature struct.
207 (neon_opcodes): Likewise.
208 (arm_opcodes): Likewise.
209 (thumb_opcodes): Likewise.
210 (thumb32_opcodes): Likewise.
211 (print_insn_coprocessor): Likewise.
212 (print_insn_arm): Likewise.
213 (select_arm_features): Follow new feature struct.
214
029f3522
GG		 2152015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
216
217 * i386-dis.c (rm_table): Add clzero.
218 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
219 Add CPU_CLZERO_FLAGS.
220 (cpu_flags): Add CpuCLZERO.
221 * i386-opc.h: Add CpuCLZERO.
222 * i386-opc.tbl: Add clzero.
223 * i386-init.h: Re-generated.
224 * i386-tbl.h: Re-generated.
225
6914869a
AB		 2262015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
227
228 * mips-opc.c (decode_mips_operand): Fix constraint issues
229 with u and y operands.
230
21e20815
AB		 2312015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
232
233 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
234
6b1d7593
AK		 2352015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
236
237 * s390-opc.c: Add new IBM z13 instructions.
238 * s390-opc.txt: Likewise.
239
c8f89a34
JW		 2402015-03-10 Renlin Li <renlin.li@arm.com>
241
242 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
243 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
244 related alias.
245 * aarch64-asm-2.c: Regenerate.
246 * aarch64-dis-2.c: Likewise.
247 * aarch64-opc-2.c: Likewise.
248
d8282f0e
JW		 2492015-03-03 Jiong Wang <jiong.wang@arm.com>
250
251 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
252
ac994365
OE		 2532015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
254
255 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
256 arch_sh_up.
257 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
258 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
259
fd63f640
V		 2602015-02-23 Vinay <Vinay.G@kpit.com>
261
262 * rl78-decode.opc (MOV): Added space between two operands for
263 'mov' instruction in index addressing mode.
264 * rl78-decode.c: Regenerate.
265
f63c1776
PA		 2662015-02-19 Pedro Alves <palves@redhat.com>
267
268 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
269
07774fcc
PA		 2702015-02-10 Pedro Alves <palves@redhat.com>
271 Tom Tromey <tromey@redhat.com>
272
273 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
274 microblaze_and, microblaze_xor.
275 * microblaze-opc.h (opcodes): Adjust.
276
3f8107ab
AM		 2772015-01-28 James Bowman <james.bowman@ftdichip.com>
278
279 * Makefile.am: Add FT32 files.
280 * configure.ac: Handle FT32.
281 * disassemble.c (disassembler): Call print_insn_ft32.
282 * ft32-dis.c: New file.
283 * ft32-opc.c: New file.
284 * Makefile.in: Regenerate.
285 * configure: Regenerate.
286 * po/POTFILES.in: Regenerate.
287
e5fe4957
KLC		 2882015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
289
290 * nds32-asm.c (keyword_sr): Add new system registers.
291
1e2e8c52
AK		 2922015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
293
294 * s390-dis.c (s390_extract_operand): Support vector register
295 operands.
296 (s390_print_insn_with_opcode): Support new operands types and add
297 new handling of optional operands.
298 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
299 and include opcode/s390.h instead.
300 (struct op_struct): New field `flags'.
301 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
302 (dumpTable): Dump flags.
303 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
304 string.
305 * s390-opc.c: Add new operands types, instruction formats, and
306 instruction masks.
307 (s390_opformats): Add new formats for .insn.
308 * s390-opc.txt: Add new instructions.
309
b90efa5b 3102015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 311
b90efa5b 312 Update year range in copyright notice of all files.
bffb6004 313
b90efa5b 314For older changes see ChangeLog-2014
252b5132 315\f
b90efa5b 316Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 317
318Copying and distribution of this file, with or without modification,
319are permitted in any medium without royalty provided the copyright
320notice and this notice are preserved.
321
252b5132 322Local Variables:
2f6d2f85
NC		 323mode: change-log
324left-margin: 8
325fill-column: 74
252b5132
RH		 326version-control: never
327End:
GDB Binutils - Deliverables
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