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ubsan: hppa: left shift of negative value
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
15d2859f
AM		 12019-12-20 Alan Modra <amodra@gmail.com>
2
3 * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
4 unsigned variables.
5
000fe1a7
AM		 62019-12-20 Alan Modra <amodra@gmail.com>
7
8 * m68hc11-dis.c (read_memory): Delete forward decls.
9 (print_indexed_operand, print_insn): Likewise.
10 (print_indexed_operand): Formatting. Don't rely on short being
11 exactly 16 bits, make sign extension explicit.
12 (print_insn): Likewise. Avoid signed overflow.
13
f0090188
AM		 142019-12-19 Alan Modra <amodra@gmail.com>
15
16 * vax-dis.c (print_insn_mode): Stop index mode recursion.
17
1d29ab86
DF		 182019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
19
20 PR 25277
21 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
22 fdiv with "mbi_".
23 * microblaze-opc.h (opcodes): Adjust to suit.
24
2480b6fa
AM		 252019-12-18 Alan Modra <amodra@gmail.com>
26
27 * alpha-opc.c (OP): Avoid signed overflow.
28 * arm-dis.c (print_insn): Likewise.
29 * mcore-dis.c (print_insn_mcore): Likewise.
30 * pj-dis.c (get_int): Likewise.
31 * ppc-opc.c (EBD15, EBD15BI): Likewise.
32 * score7-dis.c (s7_print_insn): Likewise.
33 * tic30-dis.c (print_insn_tic30): Likewise.
34 * v850-opc.c (insert_SELID): Likewise.
35 * vax-dis.c (print_insn_vax): Likewise.
36 * arc-ext.c (create_map): Likewise.
37 (struct ExtAuxRegister): Make "address" field unsigned int.
38 (arcExtMap_auxRegName): Pass unsigned address.
39 (dump_ARC_extmap): Adjust.
40 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
41
eb7b5046
AM		 422019-12-17 Alan Modra <amodra@gmail.com>
43
44 * visium-dis.c (print_insn_visium): Avoid signed overflow.
45
29298bf6
AM		 462019-12-17 Alan Modra <amodra@gmail.com>
47
48 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
49 (value_fit_unsigned_field_p): Likewise.
50 (aarch64_wide_constant_p): Likewise.
51 (operand_general_constraint_met_p): Likewise.
52 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
53
e46d79a7
AM		 542019-12-17 Alan Modra <amodra@gmail.com>
55
56 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
57 (print_insn_nds32): Use uint64_t for "given" and "given1".
58
5b660084
AM		 592019-12-17 Alan Modra <amodra@gmail.com>
60
61 * tic80-dis.c: Delete file.
62 * tic80-opc.c: Delete file.
63 * disassemble.c: Remove tic80 support.
64 * disassemble.h: Likewise.
65 * Makefile.am: Likewise.
66 * configure.ac: Likewise.
67 * Makefile.in: Regenerate.
68 * configure: Regenerate.
69 * po/POTFILES.in: Regenerate.
70
62e65990
AM		 712019-12-17 Alan Modra <amodra@gmail.com>
72
73 * bpf-ibld.c: Regenerate.
74
f81e7e2d
AM		 752019-12-16 Alan Modra <amodra@gmail.com>
76
77 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
78 conditional.
79 (aarch64_ext_imm): Avoid signed overflow.
80
488d02fe
AM		 812019-12-16 Alan Modra <amodra@gmail.com>
82
83 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
84
8a92faab
AM		 852019-12-16 Alan Modra <amodra@gmail.com>
86
87 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
88
e6ced26a
AM		 892019-12-16 Alan Modra <amodra@gmail.com>
90
91 * xstormy16-ibld.c: Regenerate.
92
84e098cd
AM		 932019-12-16 Alan Modra <amodra@gmail.com>
94
95 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
96 value adjustment so that it doesn't affect reg field too.
97
36bd8ea7
AM		 982019-12-16 Alan Modra <amodra@gmail.com>
99
100 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
101 (get_number_of_operands, getargtype, getbits, getregname),
102 (getcopregname, getprocregname, gettrapstring, getcinvstring),
103 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
104 (powerof2, match_opcode, make_instruction, print_arguments),
105 (print_arg): Delete forward declarations, moving static to..
106 (getregname, getcopregname, getregliststring): ..these definitions.
107 (build_mask): Return unsigned int mask.
108 (match_opcode): Use unsigned int vars.
109
cedfc774
AM		 1102019-12-16 Alan Modra <amodra@gmail.com>
111
112 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
113
4bdb25fe
AM		 1142019-12-16 Alan Modra <amodra@gmail.com>
115
116 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
117 (struct objdump_disasm_info): Delete.
118 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
119 N32_IMMS to unsigned before shifting left.
120
cf950fd4
AM		 1212019-12-16 Alan Modra <amodra@gmail.com>
122
123 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
124 (print_insn_moxie): Remove unnecessary cast.
125
967354c3
AM		 1262019-12-12 Alan Modra <amodra@gmail.com>
127
128 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
129 mask.
130
1d61b032
AM		 1312019-12-11 Alan Modra <amodra@gmail.com>
132
133 * arc-dis.c (BITS): Don't truncate high bits with shifts.
134 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
135 * tic54x-dis.c (print_instruction): Likewise.
136 * tilegx-opc.c (parse_insn_tilegx): Likewise.
137 * tilepro-opc.c (parse_insn_tilepro): Likewise.
138 * visium-dis.c (disassem_class0): Likewise.
139 * pdp11-dis.c (sign_extend): Likewise.
140 (SIGN_BITS): Delete.
141 * epiphany-ibld.c: Regenerate.
142 * lm32-ibld.c: Regenerate.
143 * m32c-ibld.c: Regenerate.
144
5afa80e9
AM		 1452019-12-11 Alan Modra <amodra@gmail.com>
146
147 * ns32k-dis.c (sign_extend): Correct last patch.
148
5c05618a
AM		 1492019-12-11 Alan Modra <amodra@gmail.com>
150
151 * vax-dis.c (NEXTLONG): Avoid signed overflow.
152
2a81ccbb
AM		 1532019-12-11 Alan Modra <amodra@gmail.com>
154
155 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
156 sign extend using shifts.
157
b84f6152
AM		 1582019-12-11 Alan Modra <amodra@gmail.com>
159
160 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
161
66152f16
AM		 1622019-12-11 Alan Modra <amodra@gmail.com>
163
164 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
165 on NULL registertable entry.
166 (tic4x_hash_opcode): Use unsigned arithmetic.
167
205c426a
AM		 1682019-12-11 Alan Modra <amodra@gmail.com>
169
170 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
171
fb4cb4e2
AM		 1722019-12-11 Alan Modra <amodra@gmail.com>
173
174 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
175 (bit_extract_simple, sign_extend): Likewise.
176
96f1f604
AM		 1772019-12-11 Alan Modra <amodra@gmail.com>
178
179 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
180
8c9b4171
AM		 1812019-12-11 Alan Modra <amodra@gmail.com>
182
183 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
184
334175b6
AM		 1852019-12-11 Alan Modra <amodra@gmail.com>
186
187 * m68k-dis.c (COERCE32): Cast value first.
188 (NEXTLONG, NEXTULONG): Avoid signed overflow.
189
f8a87c78
AM		 1902019-12-11 Alan Modra <amodra@gmail.com>
191
192 * h8300-dis.c (extract_immediate): Avoid signed overflow.
193 (bfd_h8_disassemble): Likewise.
194
159653d8
AM		 1952019-12-11 Alan Modra <amodra@gmail.com>
196
197 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
198 past end of operands array.
199
d93bba9e
AM		 2002019-12-11 Alan Modra <amodra@gmail.com>
201
202 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
203 overflow when collecting bytes of a number.
204
c202f69e
AM		 2052019-12-11 Alan Modra <amodra@gmail.com>
206
207 * cris-dis.c (print_with_operands): Avoid signed integer
208 overflow when collecting bytes of a 32-bit integer.
209
0ef562a4
AM		 2102019-12-11 Alan Modra <amodra@gmail.com>
211
212 * cr16-dis.c (EXTRACT, SBM): Rewrite.
213 (cr16_match_opcode): Delete duplicate bcond test.
214
2fd2b153
AM		 2152019-12-11 Alan Modra <amodra@gmail.com>
216
217 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
218 (SIGNBIT): New.
219 (MASKBITS, SIGNEXTEND): Rewrite.
220 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
221 unsigned arithmetic, instead assign result of SIGNEXTEND back
222 to x.
223 (fmtconst_val): Use 1u in shift expression.
224
a11db3e9
AM		 2252019-12-11 Alan Modra <amodra@gmail.com>
226
227 * arc-dis.c (find_format_from_table): Use ull constant when
228 shifting by up to 32.
229
9d48687b
AM		 2302019-12-11 Alan Modra <amodra@gmail.com>
231
232 PR 25270
233 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
234 false when field is zero for sve_size_tsz_bhs.
235
b8e61daa
AM		 2362019-12-11 Alan Modra <amodra@gmail.com>
237
238 * epiphany-ibld.c: Regenerate.
239
20135676
AM		 2402019-12-10 Alan Modra <amodra@gmail.com>
241
242 PR 24960
243 * disassemble.c (disassemble_free_target): New function.
244
103ebbc3
AM		 2452019-12-10 Alan Modra <amodra@gmail.com>
246
247 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
248 * disassemble.c (disassemble_init_for_target): Likewise.
249 * bpf-dis.c: Regenerate.
250 * epiphany-dis.c: Regenerate.
251 * fr30-dis.c: Regenerate.
252 * frv-dis.c: Regenerate.
253 * ip2k-dis.c: Regenerate.
254 * iq2000-dis.c: Regenerate.
255 * lm32-dis.c: Regenerate.
256 * m32c-dis.c: Regenerate.
257 * m32r-dis.c: Regenerate.
258 * mep-dis.c: Regenerate.
259 * mt-dis.c: Regenerate.
260 * or1k-dis.c: Regenerate.
261 * xc16x-dis.c: Regenerate.
262 * xstormy16-dis.c: Regenerate.
263
6f0e0752
AM		 2642019-12-10 Alan Modra <amodra@gmail.com>
265
266 * ppc-dis.c (private): Delete variable.
267 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
268 (powerpc_init_dialect): Don't use global private.
269
e7c22a69
AM		 2702019-12-10 Alan Modra <amodra@gmail.com>
271
272 * s12z-opc.c: Formatting.
273
0a6aef6b
AM		 2742019-12-08 Alan Modra <amodra@gmail.com>
275
276 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
277 registers.
278
2dc4b12f
JB		 2792019-12-05 Jan Beulich <jbeulich@suse.com>
280
281 * aarch64-tbl.h (aarch64_feature_crypto,
282 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
283 CRYPTO_V8_2_INSN): Delete.
284
378fd436
AM		 2852019-12-05 Alan Modra <amodra@gmail.com>
286
287 PR 25249
288 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
289 (struct string_buf): New.
290 (strbuf): New function.
291 (get_field): Use strbuf rather than strdup of local temp.
292 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
293 (get_field_rfsl, get_field_imm15): Likewise.
294 (get_field_rd, get_field_r1, get_field_r2): Update macros.
295 (get_field_special): Likewise. Don't strcpy spr. Formatting.
296 (print_insn_microblaze): Formatting. Init and pass string_buf to
297 get_field functions.
298
0ba59a29
JB		 2992019-12-04 Jan Beulich <jbeulich@suse.com>
300
301 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
302 * i386-tbl.h: Re-generate.
303
77ad8092
JB		 3042019-12-04 Jan Beulich <jbeulich@suse.com>
305
306 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
307
3036c899
JB		 3082019-12-04 Jan Beulich <jbeulich@suse.com>
309
310 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
311 forms.
312 (xbegin): Drop DefaultSize.
313 * i386-tbl.h: Re-generate.
314
8b301fbb
MI		 3152019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
316
317 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
318 Change the coproc CRC conditions to use the extension
319 feature set, second word, base on ARM_EXT2_CRC.
320
6aa385b9
JB		 3212019-11-14 Jan Beulich <jbeulich@suse.com>
322
323 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
324 * i386-tbl.h: Re-generate.
325
0cfa3eb3
JB		 3262019-11-14 Jan Beulich <jbeulich@suse.com>
327
328 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
329 JumpInterSegment, and JumpAbsolute entries.
330 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
331 JUMP_ABSOLUTE): Define.
332 (struct i386_opcode_modifier): Extend jump field to 3 bits.
333 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
334 fields.
335 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
336 JumpInterSegment): Define.
337 * i386-tbl.h: Re-generate.
338
6f2f06be
JB		 3392019-11-14 Jan Beulich <jbeulich@suse.com>
340
341 * i386-gen.c (operand_type_init): Remove
342 OPERAND_TYPE_JUMPABSOLUTE entry.
343 (opcode_modifiers): Add JumpAbsolute entry.
344 (operand_types): Remove JumpAbsolute entry.
345 * i386-opc.h (JumpAbsolute): Move between enums.
346 (struct i386_opcode_modifier): Add jumpabsolute field.
347 (union i386_operand_type): Remove jumpabsolute field.
348 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
349 * i386-init.h, i386-tbl.h: Re-generate.
350
601e8564
JB		 3512019-11-14 Jan Beulich <jbeulich@suse.com>
352
353 * i386-gen.c (opcode_modifiers): Add AnySize entry.
354 (operand_types): Remove AnySize entry.
355 * i386-opc.h (AnySize): Move between enums.
356 (struct i386_opcode_modifier): Add anysize field.
357 (OTUnused): Un-comment.
358 (union i386_operand_type): Remove anysize field.
359 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
360 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
361 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
362 AnySize.
363 * i386-tbl.h: Re-generate.
364
7722d40a
JW		 3652019-11-12 Nelson Chu <nelson.chu@sifive.com>
366
367 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
368 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
369 use the floating point register (FPR).
370
ce760a76
MI		 3712019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
372
373 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
374 cmode 1101.
375 (is_mve_encoding_conflict): Update cmode conflict checks for
376 MVE_VMVN_IMM.
377
51c8edf6
JB		 3782019-11-12 Jan Beulich <jbeulich@suse.com>
379
380 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
381 entry.
382 (operand_types): Remove EsSeg entry.
383 (main): Replace stale use of OTMax.
384 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
385 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
386 (EsSeg): Delete.
387 (OTUnused): Comment out.
388 (union i386_operand_type): Remove esseg field.
389 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
390 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
391 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
392 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
393 * i386-init.h, i386-tbl.h: Re-generate.
394
474da251
JB		 3952019-11-12 Jan Beulich <jbeulich@suse.com>
396
397 * i386-gen.c (operand_instances): Add RegB entry.
398 * i386-opc.h (enum operand_instance): Add RegB.
399 * i386-opc.tbl (RegC, RegD, RegB): Define.
400 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
401 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
402 monitorx, mwaitx): Drop ImmExt and convert encodings
403 accordingly.
404 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
405 (edx, rdx): Add Instance=RegD.
406 (ebx, rbx): Add Instance=RegB.
407 * i386-tbl.h: Re-generate.
408
75e5731b
JB		 4092019-11-12 Jan Beulich <jbeulich@suse.com>
410
411 * i386-gen.c (operand_type_init): Adjust
412 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
413 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
414 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
415 (operand_instances): New.
416 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
417 (output_operand_type): New parameter "instance". Process it.
418 (process_i386_operand_type): New local variable "instance".
419 (main): Adjust static assertions.
420 * i386-opc.h (INSTANCE_WIDTH): Define.
421 (enum operand_instance): New.
422 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
423 (union i386_operand_type): Replace acc, inoutportreg, and
424 shiftcount by instance.
425 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
426 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
427 Add Instance=.
428 * i386-init.h, i386-tbl.h: Re-generate.
429
91802f3c
JB		 4302019-11-11 Jan Beulich <jbeulich@suse.com>
431
432 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
433 smaxp/sminp entries' "tied_operand" field to 2.
434
4f5fc85d
JB		 4352019-11-11 Jan Beulich <jbeulich@suse.com>
436
437 * aarch64-opc.c (operand_general_constraint_met_p): Replace
438 "index" local variable by that of the already existing "num".
439
dc2be329
L		 4402019-11-08 H.J. Lu <hongjiu.lu@intel.com>
441
442 PR gas/25167
443 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
444 * i386-tbl.h: Regenerated.
445
f74a6307
JB		 4462019-11-08 Jan Beulich <jbeulich@suse.com>
447
448 * i386-gen.c (operand_type_init): Add Class= to
449 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
450 OPERAND_TYPE_REGBND entry.
451 (operand_classes): Add RegMask and RegBND entries.
452 (operand_types): Drop RegMask and RegBND entry.
453 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
454 (RegMask, RegBND): Delete.
455 (union i386_operand_type): Remove regmask and regbnd fields.
456 * i386-opc.tbl (RegMask, RegBND): Define.
457 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
458 Class=RegBND.
459 * i386-init.h, i386-tbl.h: Re-generate.
460
3528c362
JB		 4612019-11-08 Jan Beulich <jbeulich@suse.com>
462
463 * i386-gen.c (operand_type_init): Add Class= to
464 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
465 OPERAND_TYPE_REGZMM entries.
466 (operand_classes): Add RegMMX and RegSIMD entries.
467 (operand_types): Drop RegMMX and RegSIMD entries.
468 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
469 (RegMMX, RegSIMD): Delete.
470 (union i386_operand_type): Remove regmmx and regsimd fields.
471 * i386-opc.tbl (RegMMX): Define.
472 (RegXMM, RegYMM, RegZMM): Add Class=.
473 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
474 Class=RegSIMD.
475 * i386-init.h, i386-tbl.h: Re-generate.
476
4a5c67ed
JB		 4772019-11-08 Jan Beulich <jbeulich@suse.com>
478
479 * i386-gen.c (operand_type_init): Add Class= to
480 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
481 entries.
482 (operand_classes): Add RegCR, RegDR, and RegTR entries.
483 (operand_types): Drop Control, Debug, and Test entries.
484 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
485 (Control, Debug, Test): Delete.
486 (union i386_operand_type): Remove control, debug, and test
487 fields.
488 * i386-opc.tbl (Control, Debug, Test): Define.
489 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
490 Class=RegDR, and Test by Class=RegTR.
491 * i386-init.h, i386-tbl.h: Re-generate.
492
00cee14f
JB		 4932019-11-08 Jan Beulich <jbeulich@suse.com>
494
495 * i386-gen.c (operand_type_init): Add Class= to
496 OPERAND_TYPE_SREG entry.
497 (operand_classes): Add SReg entry.
498 (operand_types): Drop SReg entry.
499 * i386-opc.h (enum operand_class): Add SReg.
500 (SReg): Delete.
501 (union i386_operand_type): Remove sreg field.
502 * i386-opc.tbl (SReg): Define.
503 * i386-reg.tbl: Replace SReg by Class=SReg.
504 * i386-init.h, i386-tbl.h: Re-generate.
505
bab6aec1
JB		 5062019-11-08 Jan Beulich <jbeulich@suse.com>
507
508 * i386-gen.c (operand_type_init): Add Class=. New
509 OPERAND_TYPE_ANYIMM entry.
510 (operand_classes): New.
511 (operand_types): Drop Reg entry.
512 (output_operand_type): New parameter "class". Process it.
513 (process_i386_operand_type): New local variable "class".
514 (main): Adjust static assertions.
515 * i386-opc.h (CLASS_WIDTH): Define.
516 (enum operand_class): New.
517 (Reg): Replace by Class. Adjust comment.
518 (union i386_operand_type): Replace reg by class.
519 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
520 Class=.
521 * i386-reg.tbl: Replace Reg by Class=Reg.
522 * i386-init.h: Re-generate.
523
1f4cd317
MM		 5242019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
525
526 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
527 (aarch64_opcode_table): Add data gathering hint mnemonic.
528 * opcodes/aarch64-dis-2.c: Account for new instruction.
529
616ce08e
MM		 5302019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
531
532 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
533
534
8382113f
MM		 5352019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
536
537 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
538 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
539 aarch64_feature_f64mm): New feature sets.
540 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
541 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
542 instructions.
543 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
544 macros.
545 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
546 (OP_SVE_QQQ): New qualifier.
547 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
548 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
549 the movprfx constraint.
550 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
551 (aarch64_opcode_table): Define new instructions smmla,
552 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
553 uzip{1/2}, trn{1/2}.
554 * aarch64-opc.c (operand_general_constraint_met_p): Handle
555 AARCH64_OPND_SVE_ADDR_RI_S4x32.
556 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
557 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
558 Account for new instructions.
559 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
560 S4x32 operand.
561 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
562
aab2c27d
MM		 5632019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5642019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
565
566 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
567 Armv8.6-A.
568 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
569 (neon_opcodes): Add bfloat SIMD instructions.
570 (print_insn_coprocessor): Add new control character %b to print
571 condition code without checking cp_num.
572 (print_insn_neon): Account for BFloat16 instructions that have no
573 special top-byte handling.
574
33593eaf
MM		 5752019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5762019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
577
578 * arm-dis.c (print_insn_coprocessor,
579 print_insn_generic_coprocessor): Create wrapper functions around
580 the implementation of the print_insn_coprocessor control codes.
581 (print_insn_coprocessor_1): Original print_insn_coprocessor
582 function that now takes which array to look at as an argument.
583 (print_insn_arm): Use both print_insn_coprocessor and
584 print_insn_generic_coprocessor.
585 (print_insn_thumb32): As above.
586
df678013
MM		 5872019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5882019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
589
590 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
591 in reglane special case.
592 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
593 aarch64_find_next_opcode): Account for new instructions.
594 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
595 in reglane special case.
596 * aarch64-opc.c (struct operand_qualifier_data): Add data for
597 new AARCH64_OPND_QLF_S_2H qualifier.
598 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
599 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
600 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
601 sets.
602 (BFLOAT_SVE, BFLOAT): New feature set macros.
603 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
604 instructions.
605 (aarch64_opcode_table): Define new instructions bfdot,
606 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
607 bfcvtn2, bfcvt.
608
8ae2d3d9
MM		 6092019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6102019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
611
612 * aarch64-tbl.h (ARMV8_6): New macro.
613
142861df
JB		 6142019-11-07 Jan Beulich <jbeulich@suse.com>
615
616 * i386-dis.c (prefix_table): Add mcommit.
617 (rm_table): Add rdpru.
618 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
619 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
620 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
621 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
622 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
623 * i386-opc.tbl (mcommit, rdpru): New.
624 * i386-init.h, i386-tbl.h: Re-generate.
625
081e283f
JB		 6262019-11-07 Jan Beulich <jbeulich@suse.com>
627
628 * i386-dis.c (OP_Mwait): Drop local variable "names", use
629 "names32" instead.
630 (OP_Monitor): Drop local variable "op1_names", re-purpose
631 "names" for it instead, and replace former "names" uses by
632 "names32" ones.
633
c050c89a
JB		 6342019-11-07 Jan Beulich <jbeulich@suse.com>
635
636 PR/gas 25167
637 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
638 operand-less forms.
639 * opcodes/i386-tbl.h: Re-generate.
640
7abb8d81
JB		 6412019-11-05 Jan Beulich <jbeulich@suse.com>
642
643 * i386-dis.c (OP_Mwaitx): Delete.
644 (prefix_table): Use OP_Mwait for mwaitx entry.
645 (OP_Mwait): Also handle mwaitx.
646
267b8516
JB		 6472019-11-05 Jan Beulich <jbeulich@suse.com>
648
649 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
650 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
651 (prefix_table): Add respective entries.
652 (rm_table): Link to those entries.
653
f8687e93
JB		 6542019-11-05 Jan Beulich <jbeulich@suse.com>
655
656 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
657 (REG_0F1C_P_0_MOD_0): ... this.
658 (REG_0F1E_MOD_3): Rename to ...
659 (REG_0F1E_P_1_MOD_3): ... this.
660 (RM_0F01_REG_5): Rename to ...
661 (RM_0F01_REG_5_MOD_3): ... this.
662 (RM_0F01_REG_7): Rename to ...
663 (RM_0F01_REG_7_MOD_3): ... this.
664 (RM_0F1E_MOD_3_REG_7): Rename to ...
665 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
666 (RM_0FAE_REG_6): Rename to ...
667 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
668 (RM_0FAE_REG_7): Rename to ...
669 (RM_0FAE_REG_7_MOD_3): ... this.
670 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
671 (PREFIX_0F01_REG_5_MOD_0): ... this.
672 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
673 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
674 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
675 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
676 (PREFIX_0FAE_REG_0): Rename to ...
677 (PREFIX_0FAE_REG_0_MOD_3): ... this.
678 (PREFIX_0FAE_REG_1): Rename to ...
679 (PREFIX_0FAE_REG_1_MOD_3): ... this.
680 (PREFIX_0FAE_REG_2): Rename to ...
681 (PREFIX_0FAE_REG_2_MOD_3): ... this.
682 (PREFIX_0FAE_REG_3): Rename to ...
683 (PREFIX_0FAE_REG_3_MOD_3): ... this.
684 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
685 (PREFIX_0FAE_REG_4_MOD_0): ... this.
686 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
687 (PREFIX_0FAE_REG_4_MOD_3): ... this.
688 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
689 (PREFIX_0FAE_REG_5_MOD_0): ... this.
690 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
691 (PREFIX_0FAE_REG_5_MOD_3): ... this.
692 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
693 (PREFIX_0FAE_REG_6_MOD_0): ... this.
694 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
695 (PREFIX_0FAE_REG_6_MOD_3): ... this.
696 (PREFIX_0FAE_REG_7): Rename to ...
697 (PREFIX_0FAE_REG_7_MOD_0): ... this.
698 (PREFIX_MOD_0_0FC3): Rename to ...
699 (PREFIX_0FC3_MOD_0): ... this.
700 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
701 (PREFIX_0FC7_REG_6_MOD_0): ... this.
702 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
703 (PREFIX_0FC7_REG_6_MOD_3): ... this.
704 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
705 (PREFIX_0FC7_REG_7_MOD_3): ... this.
706 (reg_table, prefix_table, mod_table, rm_table): Adjust
707 accordingly.
708
5103274f
NC		 7092019-11-04 Nick Clifton <nickc@redhat.com>
710
711 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
712 of a v850 system register. Move the v850_sreg_names array into
713 this function.
714 (get_v850_reg_name): Likewise for ordinary register names.
715 (get_v850_vreg_name): Likewise for vector register names.
716 (get_v850_cc_name): Likewise for condition codes.
717 * get_v850_float_cc_name): Likewise for floating point condition
718 codes.
719 (get_v850_cacheop_name): Likewise for cache-ops.
720 (get_v850_prefop_name): Likewise for pref-ops.
721 (disassemble): Use the new accessor functions.
722
1820262b
DB		 7232019-10-30 Delia Burduv <delia.burduv@arm.com>
724
725 * aarch64-opc.c (print_immediate_offset_address): Don't print the
726 immediate for the writeback form of ldraa/ldrab if it is 0.
727 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
728 * aarch64-opc-2.c: Regenerated.
729
3cc17af5
JB		 7302019-10-30 Jan Beulich <jbeulich@suse.com>
731
732 * i386-gen.c (operand_type_shorthands): Delete.
733 (operand_type_init): Expand previous shorthands.
734 (set_bitfield_from_shorthand): Rename back to ...
735 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
736 of operand_type_init[].
737 (set_bitfield): Adjust call to the above function.
738 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
739 RegXMM, RegYMM, RegZMM): Define.
740 * i386-reg.tbl: Expand prior shorthands.
741
a2cebd03
JB		 7422019-10-30 Jan Beulich <jbeulich@suse.com>
743
744 * i386-gen.c (output_i386_opcode): Change order of fields
745 emitted to output.
746 * i386-opc.h (struct insn_template): Move operands field.
747 Convert extension_opcode field to unsigned short.
748 * i386-tbl.h: Re-generate.
749
507916b8
JB		 7502019-10-30 Jan Beulich <jbeulich@suse.com>
751
752 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
753 of W.
754 * i386-opc.h (W): Extend comment.
755 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
756 general purpose variants not allowing for byte operands.
757 * i386-tbl.h: Re-generate.
758
efea62b4
NC		 7592019-10-29 Nick Clifton <nickc@redhat.com>
760
761 * tic30-dis.c (print_branch): Correct size of operand array.
762
9adb2591
NC		 7632019-10-29 Nick Clifton <nickc@redhat.com>
764
765 * d30v-dis.c (print_insn): Check that operand index is valid
766 before attempting to access the operands array.
767
993a00a9
NC		 7682019-10-29 Nick Clifton <nickc@redhat.com>
769
770 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
771 locating the bit to be tested.
772
66a66a17
NC		 7732019-10-29 Nick Clifton <nickc@redhat.com>
774
775 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
776 values.
777 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
778 (print_insn_s12z): Check for illegal size values.
779
1ee3542c
NC		 7802019-10-28 Nick Clifton <nickc@redhat.com>
781
782 * csky-dis.c (csky_chars_to_number): Check for a negative
783 count. Use an unsigned integer to construct the return value.
784
bbf9a0b5
NC		 7852019-10-28 Nick Clifton <nickc@redhat.com>
786
787 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
788 operand buffer. Set value to 15 not 13.
789 (get_register_operand): Use OPERAND_BUFFER_LEN.
790 (get_indirect_operand): Likewise.
791 (print_two_operand): Likewise.
792 (print_three_operand): Likewise.
793 (print_oar_insn): Likewise.
794
d1e304bc
NC		 7952019-10-28 Nick Clifton <nickc@redhat.com>
796
797 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
798 (bit_extract_simple): Likewise.
799 (bit_copy): Likewise.
800 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
801 index_offset array are not accessed.
802
dee33451
NC		 8032019-10-28 Nick Clifton <nickc@redhat.com>
804
805 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
806 operand.
807
27cee81d
NC		 8082019-10-25 Nick Clifton <nickc@redhat.com>
809
810 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
811 access to opcodes.op array element.
812
de6d8dc2
NC		 8132019-10-23 Nick Clifton <nickc@redhat.com>
814
815 * rx-dis.c (get_register_name): Fix spelling typo in error
816 message.
817 (get_condition_name, get_flag_name, get_double_register_name)
818 (get_double_register_high_name, get_double_register_low_name)
819 (get_double_control_register_name, get_double_condition_name)
820 (get_opsize_name, get_size_name): Likewise.
821
6207ed28
NC		 8222019-10-22 Nick Clifton <nickc@redhat.com>
823
824 * rx-dis.c (get_size_name): New function. Provides safe
825 access to name array.
826 (get_opsize_name): Likewise.
827 (print_insn_rx): Use the accessor functions.
828
12234dfd
NC		 8292019-10-16 Nick Clifton <nickc@redhat.com>
830
831 * rx-dis.c (get_register_name): New function. Provides safe
832 access to name array.
833 (get_condition_name, get_flag_name, get_double_register_name)
834 (get_double_register_high_name, get_double_register_low_name)
835 (get_double_control_register_name, get_double_condition_name):
836 Likewise.
837 (print_insn_rx): Use the accessor functions.
838
1d378749
NC		 8392019-10-09 Nick Clifton <nickc@redhat.com>
840
841 PR 25041
842 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
843 instructions.
844
d241b910
JB		 8452019-10-07 Jan Beulich <jbeulich@suse.com>
846
847 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
848 (cmpsd): Likewise. Move EsSeg to other operand.
849 * opcodes/i386-tbl.h: Re-generate.
850
f5c5b7c1
AM		 8512019-09-23 Alan Modra <amodra@gmail.com>
852
853 * m68k-dis.c: Include cpu-m68k.h
854
7beeaeb8
AM		 8552019-09-23 Alan Modra <amodra@gmail.com>
856
857 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
858 "elf/mips.h" earlier.
859
3f9aad11
JB		 8602018-09-20 Jan Beulich <jbeulich@suse.com>
861
862 PR gas/25012
863 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
864 with SReg operand.
865 * i386-tbl.h: Re-generate.
866
fd361982
AM		 8672019-09-18 Alan Modra <amodra@gmail.com>
868
869 * arc-ext.c: Update throughout for bfd section macro changes.
870
e0b2a78c
SM		 8712019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
872
873 * Makefile.in: Re-generate.
874 * configure: Re-generate.
875
7e9ad3a3
JW		 8762019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
877
878 * riscv-opc.c (riscv_opcodes): Change subset field
879 to insn_class field for all instructions.
880 (riscv_insn_types): Likewise.
881
bb695960
PB		 8822019-09-16 Phil Blundell <pb@pbcl.net>
883
884 * configure: Regenerated.
885
8063ab7e
MV		 8862019-09-10 Miod Vallat <miod@online.fr>
887
888 PR 24982
889 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
890
60391a25
PB		 8912019-09-09 Phil Blundell <pb@pbcl.net>
892
893 binutils 2.33 branch created.
894
f44b758d
NC		 8952019-09-03 Nick Clifton <nickc@redhat.com>
896
897 PR 24961
898 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
899 greater than zero before indexing via (bufcnt -1).
900
1e4b5e7d
NC		 9012019-09-03 Nick Clifton <nickc@redhat.com>
902
903 PR 24958
904 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
905 (MAX_SPEC_REG_NAME_LEN): Define.
906 (struct mmix_dis_info): Use defined constants for array lengths.
907 (get_reg_name): New function.
908 (get_sprec_reg_name): New function.
909 (print_insn_mmix): Use new functions.
910
c4a23bf8
SP		 9112019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
912
913 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
914 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
915 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
916
a051e2f3
KT		 9172019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
918
919 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
920 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
921 (aarch64_sys_reg_supported_p): Update checks for the above.
922
08132bdd
SP		 9232019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
924
925 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
926 cases MVE_SQRSHRL and MVE_UQRSHLL.
927 (print_insn_mve): Add case for specifier 'k' to check
928 specific bit of the instruction.
929
d88bdcb4
PA		 9302019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
931
932 PR 24854
933 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
934 encountering an unknown machine type.
935 (print_insn_arc): Handle arc_insn_length returning 0. In error
936 cases return -1 rather than calling abort.
937
bc750500
JB		 9382019-08-07 Jan Beulich <jbeulich@suse.com>
939
940 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
941 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
942 IgnoreSize.
943 * i386-tbl.h: Re-generate.
944
23d188c7
BW		 9452019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
946
947 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
948 instructions.
949
c0d6f62f
JW		 9502019-07-30 Mel Chen <mel.chen@sifive.com>
951
952 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
953 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
954
955 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
956 fscsr.
957
0f3f7167
CZ		 9582019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
959
960 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
961 and MPY class instructions.
962 (parse_option): Add nps400 option.
963 (print_arc_disassembler_options): Add nps400 info.
964
7e126ba3
CZ		 9652019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
966
967 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
968 (bspop): Likewise.
969 (modapp): Likewise.
970 * arc-opc.c (RAD_CHK): Add.
971 * arc-tbl.h: Regenerate.
972
a028026d
KT		 9732019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
974
975 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
976 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
977
ac79ff9e
NC		 9782019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
979
980 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
981 instructions as UNPREDICTABLE.
982
231097b0
JM		 9832019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
984
985 * bpf-desc.c: Regenerated.
986
1d942ae9
JB		 9872019-07-17 Jan Beulich <jbeulich@suse.com>
988
989 * i386-gen.c (static_assert): Define.
990 (main): Use it.
991 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
992 (Opcode_Modifier_Num): ... this.
993 (Mem): Delete.
994
dfd69174
JB		 9952019-07-16 Jan Beulich <jbeulich@suse.com>
996
997 * i386-gen.c (operand_types): Move RegMem ...
998 (opcode_modifiers): ... here.
999 * i386-opc.h (RegMem): Move to opcode modifer enum.
1000 (union i386_operand_type): Move regmem field ...
1001 (struct i386_opcode_modifier): ... here.
1002 * i386-opc.tbl (RegMem): Define.
1003 (mov, movq): Move RegMem on segment, control, debug, and test
1004 register flavors.
1005 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1006 to non-SSE2AVX flavor.
1007 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1008 Move RegMem on register only flavors. Drop IgnoreSize from
1009 legacy encoding flavors.
1010 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1011 flavors.
1012 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1013 register only flavors.
1014 (vmovd): Move RegMem and drop IgnoreSize on register only
1015 flavor. Change opcode and operand order to store form.
1016 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1017
21df382b
JB		 10182019-07-16 Jan Beulich <jbeulich@suse.com>
1019
1020 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1021 entries.
1022 * i386-opc.h (SReg2, SReg3): Replace by ...
1023 (SReg): ... this.
1024 (union i386_operand_type): Replace sreg fields.
1025 * i386-opc.tbl (mov, ): Use SReg.
1026 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1027 register flavors.
1028 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1029 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1030
3719fd55
JM		 10312019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1032
1033 * bpf-desc.c: Regenerate.
1034 * bpf-opc.c: Likewise.
1035 * bpf-opc.h: Likewise.
1036
92434a14
JM		 10372019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1038
1039 * bpf-desc.c: Regenerate.
1040 * bpf-opc.c: Likewise.
1041
43dd7626
HPN		 10422019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1043
1044 * arm-dis.c (print_insn_coprocessor): Rename index to
1045 index_operand.
1046
98602811
JW		 10472019-07-05 Kito Cheng <kito.cheng@sifive.com>
1048
1049 * riscv-opc.c (riscv_insn_types): Add r4 type.
1050
1051 * riscv-opc.c (riscv_insn_types): Add b and j type.
1052
1053 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1054 format for sb type and correct s type.
1055
01c1ee4a
RS		 10562019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1057
1058 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1059 SVE FMOV alias of FCPY.
1060
83adff69
RS		 10612019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1062
1063 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1064 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1065
89418844
RS		 10662019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1067
1068 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1069 registers in an instruction prefixed by MOVPRFX.
1070
41be57ca
MM		 10712019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1072
1073 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1074 sve_size_13 icode to account for variant behaviour of
1075 pmull{t,b}.
1076 * aarch64-dis-2.c: Regenerate.
1077 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1078 sve_size_13 icode to account for variant behaviour of
1079 pmull{t,b}.
1080 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1081 (OP_SVE_VVV_Q_D): Add new qualifier.
1082 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1083 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1084 AES and those not.
1085
9d3bf266
JB		 10862019-07-01 Jan Beulich <jbeulich@suse.com>
1087
1088 * opcodes/i386-gen.c (operand_type_init): Remove
1089 OPERAND_TYPE_VEC_IMM4 entry.
1090 (operand_types): Remove Vec_Imm4.
1091 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1092 (union i386_operand_type): Remove vec_imm4.
1093 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1094 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1095
c3949f43
JB		 10962019-07-01 Jan Beulich <jbeulich@suse.com>
1097
1098 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1099 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1100 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1101 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1102 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1103 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1104 * i386-tbl.h: Re-generate.
1105
5641ec01
JB		 11062019-07-01 Jan Beulich <jbeulich@suse.com>
1107
1108 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1109 register operands.
1110 * i386-tbl.h: Re-generate.
1111
79dec6b7
JB		 11122019-07-01 Jan Beulich <jbeulich@suse.com>
1113
1114 * i386-opc.tbl (C): New.
1115 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1116 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1117 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1118 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1119 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1120 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1121 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1122 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1123 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1124 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1125 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1126 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1127 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1128 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1129 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1130 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1131 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1132 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1133 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1134 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1135 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1136 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1137 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1138 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1139 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1140 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1141 flavors.
1142 * i386-tbl.h: Re-generate.
1143
a0a1771e
JB		 11442019-07-01 Jan Beulich <jbeulich@suse.com>
1145
1146 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1147 register operands.
1148 * i386-tbl.h: Re-generate.
1149
cd546e7b
JB		 11502019-07-01 Jan Beulich <jbeulich@suse.com>
1151
1152 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1153 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1154 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1155 * i386-tbl.h: Re-generate.
1156
e3bba3fc
JB		 11572019-07-01 Jan Beulich <jbeulich@suse.com>
1158
1159 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1160 Disp8MemShift from register only templates.
1161 * i386-tbl.h: Re-generate.
1162
36cc073e
JB		 11632019-07-01 Jan Beulich <jbeulich@suse.com>
1164
1165 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1166 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1167 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1168 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1169 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1170 EVEX_W_0F11_P_3_M_1): Delete.
1171 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1172 EVEX_W_0F11_P_3): New.
1173 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1174 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1175 MOD_EVEX_0F11_PREFIX_3 table entries.
1176 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1177 PREFIX_EVEX_0F11 table entries.
1178 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1179 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1180 EVEX_W_0F11_P_3_M_{0,1} table entries.
1181
219920a7
JB		 11822019-07-01 Jan Beulich <jbeulich@suse.com>
1183
1184 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1185 Delete.
1186
e395f487
L		 11872019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1188
1189 PR binutils/24719
1190 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1191 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1192 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1193 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1194 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1195 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1196 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1197 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1198 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1199 PREFIX_EVEX_0F38C6_REG_6 entries.
1200 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1201 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1202 EVEX_W_0F38C7_R_6_P_2 entries.
1203 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1204 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1205 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1206 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1207 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1208 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1209 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1210
2b7bcc87
JB		 12112019-06-27 Jan Beulich <jbeulich@suse.com>
1212
1213 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1214 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1215 VEX_LEN_0F2D_P_3): Delete.
1216 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1217 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1218 (prefix_table): ... here.
1219
c1dc7af5
JB		 12202019-06-27 Jan Beulich <jbeulich@suse.com>
1221
1222 * i386-dis.c (Iq): Delete.
1223 (Id): New.
1224 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1225 TBM insns.
1226 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1227 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1228 (OP_E_memory): Also honor needindex when deciding whether an
1229 address size prefix needs printing.
1230 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1231
d7560e2d
JW		 12322019-06-26 Jim Wilson <jimw@sifive.com>
1233
1234 PR binutils/24739
1235 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1236 Set info->display_endian to info->endian_code.
1237
2c703856
JB		 12382019-06-25 Jan Beulich <jbeulich@suse.com>
1239
1240 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1241 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1242 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1243 OPERAND_TYPE_ACC64 entries.
1244 * i386-init.h: Re-generate.
1245
54fbadc0
JB		 12462019-06-25 Jan Beulich <jbeulich@suse.com>
1247
1248 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1249 Delete.
1250 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1251 of dqa_mode.
1252 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1253 entries here.
1254 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1255 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1256
a280ab8e
JB		 12572019-06-25 Jan Beulich <jbeulich@suse.com>
1258
1259 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1260 variables.
1261
e1a1babd
JB		 12622019-06-25 Jan Beulich <jbeulich@suse.com>
1263
1264 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1265 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1266 movnti.
d7560e2d 1267 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1268 * i386-tbl.h: Re-generate.
1269
b8364fa7
JB		 12702019-06-25 Jan Beulich <jbeulich@suse.com>
1271
1272 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1273 * i386-tbl.h: Re-generate.
1274
ad692897
L		 12752019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1276
1277 * i386-dis-evex.h: Break into ...
1278 * i386-dis-evex-len.h: New file.
1279 * i386-dis-evex-mod.h: Likewise.
1280 * i386-dis-evex-prefix.h: Likewise.
1281 * i386-dis-evex-reg.h: Likewise.
1282 * i386-dis-evex-w.h: Likewise.
1283 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1284 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1285 i386-dis-evex-mod.h.
1286
f0a6222e
L		 12872019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1288
1289 PR binutils/24700
1290 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1291 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1292 EVEX_W_0F385B_P_2.
1293 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1294 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1295 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1296 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1297 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1298 EVEX_LEN_0F385B_P_2_W_1.
1299 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1300 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1301 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1302 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1303 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1304 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1305 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1306 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1307 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1308 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1309
6e1c90b7
L		 13102019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1311
1312 PR binutils/24691
1313 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1314 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1315 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1316 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1317 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1318 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1319 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1320 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1321 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1322 EVEX_LEN_0F3A43_P_2_W_1.
1323 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1324 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1325 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1326 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1327 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1328 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1329 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1330 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1331 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1332 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1333 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1334 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1335
bcc5a6eb
NC		 13362019-06-14 Nick Clifton <nickc@redhat.com>
1337
1338 * po/fr.po; Updated French translation.
1339
e4c4ac46
SH		 13402019-06-13 Stafford Horne <shorne@gmail.com>
1341
1342 * or1k-asm.c: Regenerated.
1343 * or1k-desc.c: Regenerated.
1344 * or1k-desc.h: Regenerated.
1345 * or1k-dis.c: Regenerated.
1346 * or1k-ibld.c: Regenerated.
1347 * or1k-opc.c: Regenerated.
1348 * or1k-opc.h: Regenerated.
1349 * or1k-opinst.c: Regenerated.
1350
a0e44ef5
PB		 13512019-06-12 Peter Bergner <bergner@linux.ibm.com>
1352
1353 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1354
12efd68d
L		 13552019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1356
1357 PR binutils/24633
1358 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1359 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1360 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1361 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1362 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1363 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1364 EVEX_LEN_0F3A1B_P_2_W_1.
1365 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1366 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1367 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1368 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1369 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1370 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1371 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1372 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1373
63c6fc6c
L		 13742019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1375
1376 PR binutils/24626
1377 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1378 EVEX.vvvv when disassembling VEX and EVEX instructions.
1379 (OP_VEX): Set vex.register_specifier to 0 after readding
1380 vex.register_specifier.
1381 (OP_Vex_2src_1): Likewise.
1382 (OP_Vex_2src_2): Likewise.
1383 (OP_LWP_E): Likewise.
1384 (OP_EX_Vex): Don't check vex.register_specifier.
1385 (OP_XMM_Vex): Likewise.
1386
9186c494
L		 13872019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1388 Lili Cui <lili.cui@intel.com>
1389
1390 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1391 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1392 instructions.
1393 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1394 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1395 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1396 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1397 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1398 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1399 * i386-init.h: Regenerated.
1400 * i386-tbl.h: Likewise.
1401
5d79adc4
L		 14022019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1403 Lili Cui <lili.cui@intel.com>
1404
1405 * doc/c-i386.texi: Document enqcmd.
1406 * testsuite/gas/i386/enqcmd-intel.d: New file.
1407 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1408 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1409 * testsuite/gas/i386/enqcmd.d: Likewise.
1410 * testsuite/gas/i386/enqcmd.s: Likewise.
1411 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1412 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1413 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1414 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1415 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1416 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1417 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1418 and x86-64-enqcmd.
1419
a9d96ab9
AH		 14202019-06-04 Alan Hayward <alan.hayward@arm.com>
1421
1422 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1423
4f6d070a
AM		 14242019-06-03 Alan Modra <amodra@gmail.com>
1425
1426 * ppc-dis.c (prefix_opcd_indices): Correct size.
1427
a2f4b66c
L		 14282019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1429
1430 PR gas/24625
1431 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1432 Disp8ShiftVL.
1433 * i386-tbl.h: Regenerated.
1434
405b5bd8
AM		 14352019-05-24 Alan Modra <amodra@gmail.com>
1436
1437 * po/POTFILES.in: Regenerate.
1438
8acf1435
PB		 14392019-05-24 Peter Bergner <bergner@linux.ibm.com>
1440 Alan Modra <amodra@gmail.com>
1441
1442 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1443 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1444 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1445 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1446 XTOP>): Define and add entries.
1447 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1448 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1449 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1450 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1451
dd7efa79
PB		 14522019-05-24 Peter Bergner <bergner@linux.ibm.com>
1453 Alan Modra <amodra@gmail.com>
1454
1455 * ppc-dis.c (ppc_opts): Add "future" entry.
1456 (PREFIX_OPCD_SEGS): Define.
1457 (prefix_opcd_indices): New array.
1458 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1459 (lookup_prefix): New function.
1460 (print_insn_powerpc): Handle 64-bit prefix instructions.
1461 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1462 (PMRR, POWERXX): Define.
1463 (prefix_opcodes): New instruction table.
1464 (prefix_num_opcodes): New constant.
1465
79472b45
JM		 14662019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1467
1468 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1469 * configure: Regenerated.
1470 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1471 and cpu/bpf.opc.
1472 (HFILES): Add bpf-desc.h and bpf-opc.h.
1473 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1474 bpf-ibld.c and bpf-opc.c.
1475 (BPF_DEPS): Define.
1476 * Makefile.in: Regenerated.
1477 * disassemble.c (ARCH_bpf): Define.
1478 (disassembler): Add case for bfd_arch_bpf.
1479 (disassemble_init_for_target): Likewise.
1480 (enum epbf_isa_attr): Define.
1481 * disassemble.h: extern print_insn_bpf.
1482 * bpf-asm.c: Generated.
1483 * bpf-opc.h: Likewise.
1484 * bpf-opc.c: Likewise.
1485 * bpf-ibld.c: Likewise.
1486 * bpf-dis.c: Likewise.
1487 * bpf-desc.h: Likewise.
1488 * bpf-desc.c: Likewise.
1489
ba6cd17f
SD		 14902019-05-21 Sudakshina Das <sudi.das@arm.com>
1491
1492 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1493 and VMSR with the new operands.
1494
e39c1607
SD		 14952019-05-21 Sudakshina Das <sudi.das@arm.com>
1496
1497 * arm-dis.c (enum mve_instructions): New enum
1498 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1499 and cneg.
1500 (mve_opcodes): New instructions as above.
1501 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1502 csneg and csel.
1503 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1504
23d00a41
SD		 15052019-05-21 Sudakshina Das <sudi.das@arm.com>
1506
1507 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1508 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1509 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1510 uqshl, urshrl and urshr.
1511 (is_mve_okay_in_it): Add new instructions to TRUE list.
1512 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1513 (print_insn_mve): Updated to accept new %j,
1514 %<bitfield>m and %<bitfield>n patterns.
1515
cd4797ee
FS		 15162019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1517
1518 * mips-opc.c (mips_builtin_opcodes): Change source register
1519 constraint for DAUI.
1520
999b073b
NC		 15212019-05-20 Nick Clifton <nickc@redhat.com>
1522
1523 * po/fr.po: Updated French translation.
1524
14b456f2
AV		 15252019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1526 Michael Collison <michael.collison@arm.com>
1527
1528 * arm-dis.c (thumb32_opcodes): Add new instructions.
1529 (enum mve_instructions): Likewise.
1530 (enum mve_undefined): Add new reasons.
1531 (is_mve_encoding_conflict): Handle new instructions.
1532 (is_mve_undefined): Likewise.
1533 (is_mve_unpredictable): Likewise.
1534 (print_mve_undefined): Likewise.
1535 (print_mve_size): Likewise.
1536
f49bb598
AV		 15372019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1538 Michael Collison <michael.collison@arm.com>
1539
1540 * arm-dis.c (thumb32_opcodes): Add new instructions.
1541 (enum mve_instructions): Likewise.
1542 (is_mve_encoding_conflict): Handle new instructions.
1543 (is_mve_undefined): Likewise.
1544 (is_mve_unpredictable): Likewise.
1545 (print_mve_size): Likewise.
1546
56858bea
AV		 15472019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1548 Michael Collison <michael.collison@arm.com>
1549
1550 * arm-dis.c (thumb32_opcodes): Add new instructions.
1551 (enum mve_instructions): Likewise.
1552 (is_mve_encoding_conflict): Likewise.
1553 (is_mve_unpredictable): Likewise.
1554 (print_mve_size): Likewise.
1555
e523f101
AV		 15562019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1557 Michael Collison <michael.collison@arm.com>
1558
1559 * arm-dis.c (thumb32_opcodes): Add new instructions.
1560 (enum mve_instructions): Likewise.
1561 (is_mve_encoding_conflict): Handle new instructions.
1562 (is_mve_undefined): Likewise.
1563 (is_mve_unpredictable): Likewise.
1564 (print_mve_size): Likewise.
1565
66dcaa5d
AV		 15662019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1567 Michael Collison <michael.collison@arm.com>
1568
1569 * arm-dis.c (thumb32_opcodes): Add new instructions.
1570 (enum mve_instructions): Likewise.
1571 (is_mve_encoding_conflict): Handle new instructions.
1572 (is_mve_undefined): Likewise.
1573 (is_mve_unpredictable): Likewise.
1574 (print_mve_size): Likewise.
1575 (print_insn_mve): Likewise.
1576
d052b9b7
AV		 15772019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1578 Michael Collison <michael.collison@arm.com>
1579
1580 * arm-dis.c (thumb32_opcodes): Add new instructions.
1581 (print_insn_thumb32): Handle new instructions.
1582
ed63aa17
AV		 15832019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1584 Michael Collison <michael.collison@arm.com>
1585
1586 * arm-dis.c (enum mve_instructions): Add new instructions.
1587 (enum mve_undefined): Add new reasons.
1588 (is_mve_encoding_conflict): Handle new instructions.
1589 (is_mve_undefined): Likewise.
1590 (is_mve_unpredictable): Likewise.
1591 (print_mve_undefined): Likewise.
1592 (print_mve_size): Likewise.
1593 (print_mve_shift_n): Likewise.
1594 (print_insn_mve): Likewise.
1595
897b9bbc
AV		 15962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1597 Michael Collison <michael.collison@arm.com>
1598
1599 * arm-dis.c (enum mve_instructions): Add new instructions.
1600 (is_mve_encoding_conflict): Handle new instructions.
1601 (is_mve_unpredictable): Likewise.
1602 (print_mve_rotate): Likewise.
1603 (print_mve_size): Likewise.
1604 (print_insn_mve): Likewise.
1605
1c8f2df8
AV		 16062019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1607 Michael Collison <michael.collison@arm.com>
1608
1609 * arm-dis.c (enum mve_instructions): Add new instructions.
1610 (is_mve_encoding_conflict): Handle new instructions.
1611 (is_mve_unpredictable): Likewise.
1612 (print_mve_size): Likewise.
1613 (print_insn_mve): Likewise.
1614
d3b63143
AV		 16152019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1616 Michael Collison <michael.collison@arm.com>
1617
1618 * arm-dis.c (enum mve_instructions): Add new instructions.
1619 (enum mve_undefined): Add new reasons.
1620 (is_mve_encoding_conflict): Handle new instructions.
1621 (is_mve_undefined): Likewise.
1622 (is_mve_unpredictable): Likewise.
1623 (print_mve_undefined): Likewise.
1624 (print_mve_size): Likewise.
1625 (print_insn_mve): Likewise.
1626
14925797
AV		 16272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1628 Michael Collison <michael.collison@arm.com>
1629
1630 * arm-dis.c (enum mve_instructions): Add new instructions.
1631 (is_mve_encoding_conflict): Handle new instructions.
1632 (is_mve_undefined): Likewise.
1633 (is_mve_unpredictable): Likewise.
1634 (print_mve_size): Likewise.
1635 (print_insn_mve): Likewise.
1636
c507f10b
AV		 16372019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1638 Michael Collison <michael.collison@arm.com>
1639
1640 * arm-dis.c (enum mve_instructions): Add new instructions.
1641 (enum mve_unpredictable): Add new reasons.
1642 (enum mve_undefined): Likewise.
1643 (is_mve_okay_in_it): Handle new isntructions.
1644 (is_mve_encoding_conflict): Likewise.
1645 (is_mve_undefined): Likewise.
1646 (is_mve_unpredictable): Likewise.
1647 (print_mve_vmov_index): Likewise.
1648 (print_simd_imm8): Likewise.
1649 (print_mve_undefined): Likewise.
1650 (print_mve_unpredictable): Likewise.
1651 (print_mve_size): Likewise.
1652 (print_insn_mve): Likewise.
1653
bf0b396d
AV		 16542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1655 Michael Collison <michael.collison@arm.com>
1656
1657 * arm-dis.c (enum mve_instructions): Add new instructions.
1658 (enum mve_unpredictable): Add new reasons.
1659 (enum mve_undefined): Likewise.
1660 (is_mve_encoding_conflict): Handle new instructions.
1661 (is_mve_undefined): Likewise.
1662 (is_mve_unpredictable): Likewise.
1663 (print_mve_undefined): Likewise.
1664 (print_mve_unpredictable): Likewise.
1665 (print_mve_rounding_mode): Likewise.
1666 (print_mve_vcvt_size): Likewise.
1667 (print_mve_size): Likewise.
1668 (print_insn_mve): Likewise.
1669
ef1576a1
AV		 16702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1671 Michael Collison <michael.collison@arm.com>
1672
1673 * arm-dis.c (enum mve_instructions): Add new instructions.
1674 (enum mve_unpredictable): Add new reasons.
1675 (enum mve_undefined): Likewise.
1676 (is_mve_undefined): Handle new instructions.
1677 (is_mve_unpredictable): Likewise.
1678 (print_mve_undefined): Likewise.
1679 (print_mve_unpredictable): Likewise.
1680 (print_mve_size): Likewise.
1681 (print_insn_mve): Likewise.
1682
aef6d006
AV		 16832019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1684 Michael Collison <michael.collison@arm.com>
1685
1686 * arm-dis.c (enum mve_instructions): Add new instructions.
1687 (enum mve_undefined): Add new reasons.
1688 (insns): Add new instructions.
1689 (is_mve_encoding_conflict):
1690 (print_mve_vld_str_addr): New print function.
1691 (is_mve_undefined): Handle new instructions.
1692 (is_mve_unpredictable): Likewise.
1693 (print_mve_undefined): Likewise.
1694 (print_mve_size): Likewise.
1695 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1696 (print_insn_mve): Handle new operands.
1697
04d54ace
AV		 16982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1699 Michael Collison <michael.collison@arm.com>
1700
1701 * arm-dis.c (enum mve_instructions): Add new instructions.
1702 (enum mve_unpredictable): Add new reasons.
1703 (is_mve_encoding_conflict): Handle new instructions.
1704 (is_mve_unpredictable): Likewise.
1705 (mve_opcodes): Add new instructions.
1706 (print_mve_unpredictable): Handle new reasons.
1707 (print_mve_register_blocks): New print function.
1708 (print_mve_size): Handle new instructions.
1709 (print_insn_mve): Likewise.
1710
9743db03
AV		 17112019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1712 Michael Collison <michael.collison@arm.com>
1713
1714 * arm-dis.c (enum mve_instructions): Add new instructions.
1715 (enum mve_unpredictable): Add new reasons.
1716 (enum mve_undefined): Likewise.
1717 (is_mve_encoding_conflict): Handle new instructions.
1718 (is_mve_undefined): Likewise.
1719 (is_mve_unpredictable): Likewise.
1720 (coprocessor_opcodes): Move NEON VDUP from here...
1721 (neon_opcodes): ... to here.
1722 (mve_opcodes): Add new instructions.
1723 (print_mve_undefined): Handle new reasons.
1724 (print_mve_unpredictable): Likewise.
1725 (print_mve_size): Handle new instructions.
1726 (print_insn_neon): Handle vdup.
1727 (print_insn_mve): Handle new operands.
1728
143275ea
AV		 17292019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1730 Michael Collison <michael.collison@arm.com>
1731
1732 * arm-dis.c (enum mve_instructions): Add new instructions.
1733 (enum mve_unpredictable): Add new values.
1734 (mve_opcodes): Add new instructions.
1735 (vec_condnames): New array with vector conditions.
1736 (mve_predicatenames): New array with predicate suffixes.
1737 (mve_vec_sizename): New array with vector sizes.
1738 (enum vpt_pred_state): New enum with vector predication states.
1739 (struct vpt_block): New struct type for vpt blocks.
1740 (vpt_block_state): Global struct to keep track of state.
1741 (mve_extract_pred_mask): New helper function.
1742 (num_instructions_vpt_block): Likewise.
1743 (mark_outside_vpt_block): Likewise.
1744 (mark_inside_vpt_block): Likewise.
1745 (invert_next_predicate_state): Likewise.
1746 (update_next_predicate_state): Likewise.
1747 (update_vpt_block_state): Likewise.
1748 (is_vpt_instruction): Likewise.
1749 (is_mve_encoding_conflict): Add entries for new instructions.
1750 (is_mve_unpredictable): Likewise.
1751 (print_mve_unpredictable): Handle new cases.
1752 (print_instruction_predicate): Likewise.
1753 (print_mve_size): New function.
1754 (print_vec_condition): New function.
1755 (print_insn_mve): Handle vpt blocks and new print operands.
1756
f08d8ce3
AV		 17572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1758
1759 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1760 8, 14 and 15 for Armv8.1-M Mainline.
1761
73cd51e5
AV		 17622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1763 Michael Collison <michael.collison@arm.com>
1764
1765 * arm-dis.c (enum mve_instructions): New enum.
1766 (enum mve_unpredictable): Likewise.
1767 (enum mve_undefined): Likewise.
1768 (struct mopcode32): New struct.
1769 (is_mve_okay_in_it): New function.
1770 (is_mve_architecture): Likewise.
1771 (arm_decode_field): Likewise.
1772 (arm_decode_field_multiple): Likewise.
1773 (is_mve_encoding_conflict): Likewise.
1774 (is_mve_undefined): Likewise.
1775 (is_mve_unpredictable): Likewise.
1776 (print_mve_undefined): Likewise.
1777 (print_mve_unpredictable): Likewise.
1778 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1779 (print_insn_mve): New function.
1780 (print_insn_thumb32): Handle MVE architecture.
1781 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1782
3076e594
NC		 17832019-05-10 Nick Clifton <nickc@redhat.com>
1784
1785 PR 24538
1786 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1787 end of the table prematurely.
1788
387e7624
FS		 17892019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1790
1791 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1792 macros for R6.
1793
0067be51
AM		 17942019-05-11 Alan Modra <amodra@gmail.com>
1795
1796 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1797 when -Mraw is in effect.
1798
42e6288f
MM		 17992019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1800
1801 * aarch64-dis-2.c: Regenerate.
1802 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1803 (OP_SVE_BBB): New variant set.
1804 (OP_SVE_DDDD): New variant set.
1805 (OP_SVE_HHH): New variant set.
1806 (OP_SVE_HHHU): New variant set.
1807 (OP_SVE_SSS): New variant set.
1808 (OP_SVE_SSSU): New variant set.
1809 (OP_SVE_SHH): New variant set.
1810 (OP_SVE_SBBU): New variant set.
1811 (OP_SVE_DSS): New variant set.
1812 (OP_SVE_DHHU): New variant set.
1813 (OP_SVE_VMV_HSD_BHS): New variant set.
1814 (OP_SVE_VVU_HSD_BHS): New variant set.
1815 (OP_SVE_VVVU_SD_BH): New variant set.
1816 (OP_SVE_VVVU_BHSD): New variant set.
1817 (OP_SVE_VVV_QHD_DBS): New variant set.
1818 (OP_SVE_VVV_HSD_BHS): New variant set.
1819 (OP_SVE_VVV_HSD_BHS2): New variant set.
1820 (OP_SVE_VVV_BHS_HSD): New variant set.
1821 (OP_SVE_VV_BHS_HSD): New variant set.
1822 (OP_SVE_VVV_SD): New variant set.
1823 (OP_SVE_VVU_BHS_HSD): New variant set.
1824 (OP_SVE_VZVV_SD): New variant set.
1825 (OP_SVE_VZVV_BH): New variant set.
1826 (OP_SVE_VZV_SD): New variant set.
1827 (aarch64_opcode_table): Add sve2 instructions.
1828
28ed815a
MM		 18292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1830
1831 * aarch64-asm-2.c: Regenerated.
1832 * aarch64-dis-2.c: Regenerated.
1833 * aarch64-opc-2.c: Regenerated.
1834 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1835 for SVE_SHLIMM_UNPRED_22.
1836 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1837 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1838 operand.
1839
fd1dc4a0
MM		 18402019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1841
1842 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1843 sve_size_tsz_bhs iclass encode.
1844 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1845 sve_size_tsz_bhs iclass decode.
1846
31e36ab3
MM		 18472019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1848
1849 * aarch64-asm-2.c: Regenerated.
1850 * aarch64-dis-2.c: Regenerated.
1851 * aarch64-opc-2.c: Regenerated.
1852 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1853 for SVE_Zm4_11_INDEX.
1854 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1855 (fields): Handle SVE_i2h field.
1856 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1857 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1858
1be5f94f
MM		 18592019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1860
1861 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1862 sve_shift_tsz_bhsd iclass encode.
1863 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1864 sve_shift_tsz_bhsd iclass decode.
1865
3c17238b
MM		 18662019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1867
1868 * aarch64-asm-2.c: Regenerated.
1869 * aarch64-dis-2.c: Regenerated.
1870 * aarch64-opc-2.c: Regenerated.
1871 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1872 (aarch64_encode_variant_using_iclass): Handle
1873 sve_shift_tsz_hsd iclass encode.
1874 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1875 sve_shift_tsz_hsd iclass decode.
1876 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1877 for SVE_SHRIMM_UNPRED_22.
1878 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1879 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1880 operand.
1881
cd50a87a
MM		 18822019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1883
1884 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1885 sve_size_013 iclass encode.
1886 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1887 sve_size_013 iclass decode.
1888
3c705960
MM		 18892019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1890
1891 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1892 sve_size_bh iclass encode.
1893 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1894 sve_size_bh iclass decode.
1895
0a57e14f
MM		 18962019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1897
1898 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1899 sve_size_sd2 iclass encode.
1900 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1901 sve_size_sd2 iclass decode.
1902 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1903 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1904
c469c864
MM		 19052019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1906
1907 * aarch64-asm-2.c: Regenerated.
1908 * aarch64-dis-2.c: Regenerated.
1909 * aarch64-opc-2.c: Regenerated.
1910 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1911 for SVE_ADDR_ZX.
1912 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1913 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1914
116adc27
MM		 19152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1916
1917 * aarch64-asm-2.c: Regenerated.
1918 * aarch64-dis-2.c: Regenerated.
1919 * aarch64-opc-2.c: Regenerated.
1920 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1921 for SVE_Zm3_11_INDEX.
1922 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1923 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1924 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1925 fields.
1926 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1927
3bd82c86
MM		 19282019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1929
1930 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1931 sve_size_hsd2 iclass encode.
1932 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1933 sve_size_hsd2 iclass decode.
1934 * aarch64-opc.c (fields): Handle SVE_size field.
1935 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1936
adccc507
MM		 19372019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1938
1939 * aarch64-asm-2.c: Regenerated.
1940 * aarch64-dis-2.c: Regenerated.
1941 * aarch64-opc-2.c: Regenerated.
1942 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1943 for SVE_IMM_ROT3.
1944 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1945 (fields): Handle SVE_rot3 field.
1946 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1947 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1948
5cd99750
MM		 19492019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1950
1951 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1952 instructions.
1953
7ce2460a
MM		 19542019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1955
1956 * aarch64-tbl.h
1957 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1958 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1959 aarch64_feature_sve2bitperm): New feature sets.
1960 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1961 for feature set addresses.
1962 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1963 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1964
41cee089
FS		 19652019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1966 Faraz Shahbazker <fshahbazker@wavecomp.com>
1967
1968 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1969 argument and set ASE_EVA_R6 appropriately.
1970 (set_default_mips_dis_options): Pass ISA to above.
1971 (parse_mips_dis_option): Likewise.
1972 * mips-opc.c (EVAR6): New macro.
1973 (mips_builtin_opcodes): Add llwpe, scwpe.
1974
b83b4b13
SD		 19752019-05-01 Sudakshina Das <sudi.das@arm.com>
1976
1977 * aarch64-asm-2.c: Regenerated.
1978 * aarch64-dis-2.c: Regenerated.
1979 * aarch64-opc-2.c: Regenerated.
1980 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1981 AARCH64_OPND_TME_UIMM16.
1982 (aarch64_print_operand): Likewise.
1983 * aarch64-tbl.h (QL_IMM_NIL): New.
1984 (TME): New.
1985 (_TME_INSN): New.
1986 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1987
4a90ce95
JD		 19882019-04-29 John Darrington <john@darrington.wattle.id.au>
1989
1990 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1991
a45328b9
AB		 19922019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1993 Faraz Shahbazker <fshahbazker@wavecomp.com>
1994
1995 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1996
d10be0cb
JD		 19972019-04-24 John Darrington <john@darrington.wattle.id.au>
1998
1999 * s12z-opc.h: Add extern "C" bracketing to help
2000 users who wish to use this interface in c++ code.
2001
a679f24e
JD		 20022019-04-24 John Darrington <john@darrington.wattle.id.au>
2003
2004 * s12z-opc.c (bm_decode): Handle bit map operations with the
2005 "reserved0" mode.
2006
32c36c3c
AV		 20072019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2008
2009 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2010 specifier. Add entries for VLDR and VSTR of system registers.
2011 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2012 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2013 of %J and %K format specifier.
2014
efd6b359
AV		 20152019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2016
2017 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2018 Add new entries for VSCCLRM instruction.
2019 (print_insn_coprocessor): Handle new %C format control code.
2020
6b0dd094
AV		 20212019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2022
2023 * arm-dis.c (enum isa): New enum.
2024 (struct sopcode32): New structure.
2025 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2026 set isa field of all current entries to ANY.
2027 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2028 Only match an entry if its isa field allows the current mode.
2029
4b5a202f
AV		 20302019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2031
2032 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2033 CLRM.
2034 (print_insn_thumb32): Add logic to print %n CLRM register list.
2035
60f993ce
AV		 20362019-04-15 Sudakshina Das <sudi.das@arm.com>
2037
2038 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2039 and %Q patterns.
2040
f6b2b12d
AV		 20412019-04-15 Sudakshina Das <sudi.das@arm.com>
2042
2043 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2044 (print_insn_thumb32): Edit the switch case for %Z.
2045
1889da70
AV		 20462019-04-15 Sudakshina Das <sudi.das@arm.com>
2047
2048 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2049
65d1bc05
AV		 20502019-04-15 Sudakshina Das <sudi.das@arm.com>
2051
2052 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2053
1caf72a5
AV		 20542019-04-15 Sudakshina Das <sudi.das@arm.com>
2055
2056 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2057
f1c7f421
AV		 20582019-04-15 Sudakshina Das <sudi.das@arm.com>
2059
2060 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2061 Arm register with r13 and r15 unpredictable.
2062 (thumb32_opcodes): New instructions for bfx and bflx.
2063
4389b29a
AV		 20642019-04-15 Sudakshina Das <sudi.das@arm.com>
2065
2066 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2067
e5d6e09e
AV		 20682019-04-15 Sudakshina Das <sudi.das@arm.com>
2069
2070 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2071
e12437dc
AV		 20722019-04-15 Sudakshina Das <sudi.das@arm.com>
2073
2074 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2075
031254f2
AV		 20762019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2077
2078 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2079
e5a557ac
JD		 20802019-04-12 John Darrington <john@darrington.wattle.id.au>
2081
2082 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2083 "optr". ("operator" is a reserved word in c++).
2084
bd7ceb8d
SD		 20852019-04-11 Sudakshina Das <sudi.das@arm.com>
2086
2087 * aarch64-opc.c (aarch64_print_operand): Add case for
2088 AARCH64_OPND_Rt_SP.
2089 (verify_constraints): Likewise.
2090 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2091 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2092 to accept Rt|SP as first operand.
2093 (AARCH64_OPERANDS): Add new Rt_SP.
2094 * aarch64-asm-2.c: Regenerated.
2095 * aarch64-dis-2.c: Regenerated.
2096 * aarch64-opc-2.c: Regenerated.
2097
e54010f1
SD		 20982019-04-11 Sudakshina Das <sudi.das@arm.com>
2099
2100 * aarch64-asm-2.c: Regenerated.
2101 * aarch64-dis-2.c: Likewise.
2102 * aarch64-opc-2.c: Likewise.
2103 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2104
7e96e219
RS		 21052019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2106
2107 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2108
6f2791d5
L		 21092019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2110
2111 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2112 * i386-init.h: Regenerated.
2113
e392bad3
AM		 21142019-04-07 Alan Modra <amodra@gmail.com>
2115
2116 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2117 op_separator to control printing of spaces, comma and parens
2118 rather than need_comma, need_paren and spaces vars.
2119
dffaa15c
AM		 21202019-04-07 Alan Modra <amodra@gmail.com>
2121
2122 PR 24421
2123 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2124 (print_insn_neon, print_insn_arm): Likewise.
2125
d6aab7a1
XG		 21262019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2127
2128 * i386-dis-evex.h (evex_table): Updated to support BF16
2129 instructions.
2130 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2131 and EVEX_W_0F3872_P_3.
2132 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2133 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2134 * i386-opc.h (enum): Add CpuAVX512_BF16.
2135 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2136 * i386-opc.tbl: Add AVX512 BF16 instructions.
2137 * i386-init.h: Regenerated.
2138 * i386-tbl.h: Likewise.
2139
66e85460
AM		 21402019-04-05 Alan Modra <amodra@gmail.com>
2141
2142 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2143 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2144 to favour printing of "-" branch hint when using the "y" bit.
2145 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2146
c2b1c275
AM		 21472019-04-05 Alan Modra <amodra@gmail.com>
2148
2149 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2150 opcode until first operand is output.
2151
aae9718e
PB		 21522019-04-04 Peter Bergner <bergner@linux.ibm.com>
2153
2154 PR gas/24349
2155 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2156 (valid_bo_post_v2): Add support for 'at' branch hints.
2157 (insert_bo): Only error on branch on ctr.
2158 (get_bo_hint_mask): New function.
2159 (insert_boe): Add new 'branch_taken' formal argument. Add support
2160 for inserting 'at' branch hints.
2161 (extract_boe): Add new 'branch_taken' formal argument. Add support
2162 for extracting 'at' branch hints.
2163 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2164 (BOE): Delete operand.
2165 (BOM, BOP): New operands.
2166 (RM): Update value.
2167 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2168 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2169 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2170 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2171 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2172 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2173 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2174 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2175 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2176 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2177 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2178 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2179 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2180 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2181 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2182 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2183 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2184 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2185 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2186 bttarl+>: New extended mnemonics.
2187
96a86c01
AM		 21882019-03-28 Alan Modra <amodra@gmail.com>
2189
2190 PR 24390
2191 * ppc-opc.c (BTF): Define.
2192 (powerpc_opcodes): Use for mtfsb*.
2193 * ppc-dis.c (print_insn_powerpc): Print fields with both
2194 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2195
796d6298
TC		 21962019-03-25 Tamar Christina <tamar.christina@arm.com>
2197
2198 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2199 (mapping_symbol_for_insn): Implement new algorithm.
2200 (print_insn): Remove duplicate code.
2201
60df3720
TC		 22022019-03-25 Tamar Christina <tamar.christina@arm.com>
2203
2204 * aarch64-dis.c (print_insn_aarch64):
2205 Implement override.
2206
51457761
TC		 22072019-03-25 Tamar Christina <tamar.christina@arm.com>
2208
2209 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2210 order.
2211
53b2f36b
TC		 22122019-03-25 Tamar Christina <tamar.christina@arm.com>
2213
2214 * aarch64-dis.c (last_stop_offset): New.
2215 (print_insn_aarch64): Use stop_offset.
2216
89199bb5
L		 22172019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2218
2219 PR gas/24359
2220 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2221 CPU_ANY_AVX2_FLAGS.
2222 * i386-init.h: Regenerated.
2223
97ed31ae
L		 22242019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2225
2226 PR gas/24348
2227 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2228 vmovdqu16, vmovdqu32 and vmovdqu64.
2229 * i386-tbl.h: Regenerated.
2230
0919bfe9
AK		 22312019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2232
2233 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2234 from vstrszb, vstrszh, and vstrszf.
2235
22362019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2237
2238 * s390-opc.txt: Add instruction descriptions.
2239
21820ebe
JW		 22402019-02-08 Jim Wilson <jimw@sifive.com>
2241
2242 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2243 <bne>: Likewise.
2244
f7dd2fb2
TC		 22452019-02-07 Tamar Christina <tamar.christina@arm.com>
2246
2247 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2248
6456d318
TC		 22492019-02-07 Tamar Christina <tamar.christina@arm.com>
2250
2251 PR binutils/23212
2252 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2253 * aarch64-opc.c (verify_elem_sd): New.
2254 (fields): Add FLD_sz entr.
2255 * aarch64-tbl.h (_SIMD_INSN): New.
2256 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2257 fmulx scalar and vector by element isns.
2258
4a83b610
NC		 22592019-02-07 Nick Clifton <nickc@redhat.com>
2260
2261 * po/sv.po: Updated Swedish translation.
2262
fc60b8c8
AK		 22632019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2264
2265 * s390-mkopc.c (main): Accept arch13 as cpu string.
2266 * s390-opc.c: Add new instruction formats and instruction opcode
2267 masks.
2268 * s390-opc.txt: Add new arch13 instructions.
2269
e10620d3
TC		 22702019-01-25 Sudakshina Das <sudi.das@arm.com>
2271
2272 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2273 (aarch64_opcode): Change encoding for stg, stzg
2274 st2g and st2zg.
2275 * aarch64-asm-2.c: Regenerated.
2276 * aarch64-dis-2.c: Regenerated.
2277 * aarch64-opc-2.c: Regenerated.
2278
20a4ca55
SD		 22792019-01-25 Sudakshina Das <sudi.das@arm.com>
2280
2281 * aarch64-asm-2.c: Regenerated.
2282 * aarch64-dis-2.c: Likewise.
2283 * aarch64-opc-2.c: Likewise.
2284 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2285
550fd7bf
SD		 22862019-01-25 Sudakshina Das <sudi.das@arm.com>
2287 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2288
2289 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2290 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2291 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2292 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2293 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2294 case for ldstgv_indexed.
2295 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2296 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2297 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2298 * aarch64-asm-2.c: Regenerated.
2299 * aarch64-dis-2.c: Regenerated.
2300 * aarch64-opc-2.c: Regenerated.
2301
d9938630
NC		 23022019-01-23 Nick Clifton <nickc@redhat.com>
2303
2304 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2305
375cd423
NC		 23062019-01-21 Nick Clifton <nickc@redhat.com>
2307
2308 * po/de.po: Updated German translation.
2309 * po/uk.po: Updated Ukranian translation.
2310
57299f48
CX		 23112019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2312 * mips-dis.c (mips_arch_choices): Fix typo in
2313 gs464, gs464e and gs264e descriptors.
2314
f48dfe41
NC		 23152019-01-19 Nick Clifton <nickc@redhat.com>
2316
2317 * configure: Regenerate.
2318 * po/opcodes.pot: Regenerate.
2319
f974f26c
NC		 23202018-06-24 Nick Clifton <nickc@redhat.com>
2321
2322 2.32 branch created.
2323
39f286cd
JD		 23242019-01-09 John Darrington <john@darrington.wattle.id.au>
2325
448b8ca8
JD		 2326 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2327 if it is null.
2328 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2329 zero.
2330
3107326d
AP		 23312019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2332
2333 * configure: Regenerate.
2334
7e9ca91e
AM		 23352019-01-07 Alan Modra <amodra@gmail.com>
2336
2337 * configure: Regenerate.
2338 * po/POTFILES.in: Regenerate.
2339
ef1ad42b
JD		 23402019-01-03 John Darrington <john@darrington.wattle.id.au>
2341
2342 * s12z-opc.c: New file.
2343 * s12z-opc.h: New file.
2344 * s12z-dis.c: Removed all code not directly related to display
2345 of instructions. Used the interface provided by the new files
2346 instead.
2347 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2348 * Makefile.in: Regenerate.
ef1ad42b 2349 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2350 * configure: Regenerate.
ef1ad42b 2351
82704155
AM		 23522019-01-01 Alan Modra <amodra@gmail.com>
2353
2354 Update year range in copyright notice of all files.
2355
d5c04e1b 2356For older changes see ChangeLog-2018
3499769a 2357\f
d5c04e1b 2358Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2359
2360Copying and distribution of this file, with or without modification,
2361are permitted in any medium without royalty provided the copyright
2362notice and this notice are preserved.
2363
2364Local Variables:
2365mode: change-log
2366left-margin: 8
2367fill-column: 74
2368version-control: never
2369End:
GDB Binutils - Deliverables
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