projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* gdb.base/hashline2.exp: Fix typo.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4267b19f
NC		 12008-10-22 Nick Clifton <nickc@redhat.com>
2
3 PR 6937
4 * configure.in (SHARED_LIBADD): Revert previous change.
5 Add a comment explaining why.
6 (SHARED_DEPENDENCIES): Revert previous change.
7 * configure: Regenerate.
8
8a9629d0
NC		 92008-10-10 Nick Clifton <nickc@redhat.com>
10
11 PR 6937
12 * configure.in (SHARED_LIBADD): Add libiberty.a.
13 (SHARED_DEPENDENCIES): Add libiberty.a.
14
c587b3f9
L		 152008-09-30 H.J. Lu <hongjiu.lu@intel.com>
16
17 * i386-gen.c: Include "hashtab.h".
18 (next_field): Take a new argument, last. Check last.
19 (process_i386_cpu_flag): Updated.
20 (process_i386_opcode_modifier): Likewise.
21 (process_i386_operand_type): Likewise.
22 (process_i386_registers): Likewise.
23 (output_i386_opcode): New.
24 (opcode_hash_entry): Likewise.
25 (opcode_hash_table): Likewise.
26 (opcode_hash_hash): Likewise.
27 (opcode_hash_eq): Likewise.
28 (process_i386_opcodes): Use opcode hash table and opcode array.
29
34b23dab
AK		 302008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
31
32 * s390-opc.txt (stdy, stey): Fix description
33
782e11fd
AM		 342008-09-30 Alan Modra <amodra@bigpond.net.au>
35
36 * Makefile.am: Run "make dep-am".
37 * Makefile.in: Regenerate.
38
1927a18f
L		 392008-09-29 H.J. Lu <hongjiu.lu@intel.com>
40
41 * aclocal.m4: Regenerated.
42 * configure: Likewise.
43 * Makefile.in: Likewise.
44
afac680a
NC		 452008-09-29 Nick Clifton <nickc@redhat.com>
46
47 * po/vi.po: Updated Vietnamese translation.
48 * po/fr.po: Updated French translation.
49
b40d5eb9
AK		 502008-09-26 Florian Krohm <fkrohm@us.ibm.com>
51
52 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
53 (cfxr, cfdr, cfer, clclu): Add esa flag.
54 (sqd): Instruction added.
55 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
56 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
57
d0411736
AM		 582008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
59
60 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
61 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
62
3e126784
L		 632008-09-11 H.J. Lu <hongjiu.lu@intel.com>
64
65 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
66 * i386-tbl.h: Regenerated.
67
ddab3d59
JB		 682008-08-28 Jan Beulich <jbeulich@novell.com>
69
70 * i386-dis.c (dis386): Adjust far return mnemonics.
71 * i386-opc.tbl: Add retf.
72 * i386-tbl.h: Re-generate.
73
b19d5385
JB		 742008-08-28 Jan Beulich <jbeulich@novell.com>
75
76 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
77
1ca35711
L		 782008-08-28 H.J. Lu <hongjiu.lu@intel.com>
79
80 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
81 * ia64-gen.c (lookup_specifier): Likewise.
82
83 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
84 * ia64-raw.tbl: Likewise.
85 * ia64-waw.tbl: Likewise.
86 * ia64-asmtab.c: Regenerated.
87
515c56e7
L		 882008-08-27 H.J. Lu <hongjiu.lu@intel.com>
89
90 * i386-opc.tbl: Correct fidivr operand size.
91
92 * i386-tbl.h: Regenerated.
93
da594c4a
AM		 942008-08-24 Alan Modra <amodra@bigpond.net.au>
95
96 * configure.in: Update a number of obsolete autoconf macros.
97 * aclocal.m4: Regenerate.
98
a5ff0eb2
L		 992008-08-20 H.J. Lu <hongjiu.lu@intel.com>
100
101 AVX Programming Reference (August, 2008)
102 * i386-dis.c (PREFIX_VEX_38DB): New.
103 (PREFIX_VEX_38DC): Likewise.
104 (PREFIX_VEX_38DD): Likewise.
105 (PREFIX_VEX_38DE): Likewise.
106 (PREFIX_VEX_38DF): Likewise.
107 (PREFIX_VEX_3ADF): Likewise.
108 (VEX_LEN_38DB_P_2): Likewise.
109 (VEX_LEN_38DC_P_2): Likewise.
110 (VEX_LEN_38DD_P_2): Likewise.
111 (VEX_LEN_38DE_P_2): Likewise.
112 (VEX_LEN_38DF_P_2): Likewise.
113 (VEX_LEN_3ADF_P_2): Likewise.
114 (PREFIX_VEX_3A04): Updated.
115 (VEX_LEN_3A06_P_2): Likewise.
116 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
117 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
118 (x86_64_table): Likewise.
119 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
120 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
121 VEX_LEN_3ADF_P_2.
122
123 * i386-opc.tbl: Add AES + AVX instructions.
124 * i386-init.h: Regenerated.
125 * i386-tbl.h: Likewise.
126
7dc6076f
AK		 1272008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
128
129 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
130 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
131
7357c5b6
AM		 1322008-08-15 Alan Modra <amodra@bigpond.net.au>
133
134 PR 6526
135 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
136 * Makefile.in: Regenerate.
137 * aclocal.m4: Regenerate.
138 * config.in: Regenerate.
139 * configure: Regenerate.
140
899d85be
AM		 1412008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
142
143 PR 6825
144 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
145
dfb07592
L		 1462008-08-12 H.J. Lu <hongjiu.lu@intel.com>
147
148 * i386-opc.tbl: Add syscall and sysret for Cpu64.
149
150 * i386-tbl.h: Regenerated.
151
323ee3f4
AM		 1522008-08-04 Alan Modra <amodra@bigpond.net.au>
153
154 * Makefile.am (POTFILES.in): Set LC_ALL=C.
155 * Makefile.in: Regenerate.
156 * po/POTFILES.in: Regenerate.
157
9b4e5766
PB		 1582008-08-01 Peter Bergner <bergner@vnet.ibm.com>
159
160 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
161 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
162 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
163 * ppc-opc.c (insert_xt6): New static function.
164 (extract_xt6): Likewise.
165 (insert_xa6): Likewise.
166 (extract_xa6: Likewise.
167 (insert_xb6): Likewise.
168 (extract_xb6): Likewise.
169 (insert_xb6s): Likewise.
170 (extract_xb6s): Likewise.
171 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
172 XX3DM_MASK, PPCVSX): New.
173 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
174 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
175
20fd6e2e
PA		 1762008-08-01 Pedro Alves <pedro@codesourcery.com>
177
178 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
179 * Makefile.in: Regenerate.
180
a656ed5b
L		 1812008-08-01 H.J. Lu <hongjiu.lu@intel.com>
182
183 * i386-reg.tbl: Use Dw2Inval on AVX registers.
184 * i386-tbl.h: Regenerated.
185
081ba1b3
AM		 1862008-07-30 Michael J. Eager <eager@eagercon.com>
187
188 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
189 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
190 (insert_sprg, PPC405): Use PPC_OPCODE_405.
191 (powerpc_opcodes): Add Xilinx APU related opcodes.
192
0af1713e
AM		 1932008-07-30 Alan Modra <amodra@bigpond.net.au>
194
195 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
196
30c09090
RS		 1972008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
198
199 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
200
c27e721e
AN		 2012008-07-07 Adam Nemet <anemet@caviumnetworks.com>
202
203 * mips-opc.c (CP): New macro.
204 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
205 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
206 dmtc2 Octeon instructions.
207
bd2e2557
SS		 2082008-07-07 Stan Shebs <stan@codesourcery.com>
209
210 * dis-init.c (init_disassemble_info): Init endian_code field.
211 * arm-dis.c (print_insn): Disassemble code according to
212 setting of endian_code.
213 (print_insn_big_arm): Detect when BE8 extension flag has been set.
214
6ba2a415
RS		 2152008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
216
217 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
218 for ELF symbols.
219
c8187e15
PB		 2202008-06-25 Peter Bergner <bergner@vnet.ibm.com>
221
222 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
223 (print_ppc_disassembler_options): Likewise.
224 * ppc-opc.c (PPC464): Define.
225 (powerpc_opcodes): Add mfdcrux and mtdcrux.
226
7a283e07
RW		 2272008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
228
229 * configure: Regenerate.
230
fa452fa6
PB		 2312008-06-13 Peter Bergner <bergner@vnet.ibm.com>
232
233 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
234 ppc_cpu_t typedef.
235 (struct dis_private): New.
236 (POWERPC_DIALECT): New define.
237 (powerpc_dialect): Renamed to...
238 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
239 struct dis_private.
240 (print_insn_big_powerpc): Update for using structure in
241 info->private_data.
242 (print_insn_little_powerpc): Likewise.
243 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
244 (skip_optional_operands): Likewise.
245 (print_insn_powerpc): Likewise. Remove initialization of dialect.
246 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
247 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
248 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
249 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
250 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
251 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
252 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
253 param to be of type ppc_cpu_t. Update prototype.
254
bb35fb24
NC		 2552008-06-12 Adam Nemet <anemet@caviumnetworks.com>
256
257 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
258 +s, +S.
259 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
260 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
261 syncw, syncws, vm3mulu, vm0 and vmulu.
262
dd3cbb7e
NC		 263 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
264 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
265 seqi, sne and snei.
266
a5dabbb0
L		 2672008-05-30 H.J. Lu <hongjiu.lu@intel.com>
268
269 * i386-opc.tbl: Add vmovd with 64bit operand.
270 * i386-tbl.h: Regenerated.
271
725a9891
MS		 2722008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
273
274 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
275
cbc80391
L		 2762008-05-22 H.J. Lu <hongjiu.lu@intel.com>
277
278 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
279 * i386-tbl.h: Regenerated.
280
116615c5
L		 2812008-05-22 H.J. Lu <hongjiu.lu@intel.com>
282
283 PR gas/6517
284 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
285 into 32bit and 64bit. Remove Reg64|Qword and add
286 IgnoreSize|No_qSuf on 32bit version.
287 * i386-tbl.h: Regenerated.
288
d9479f2d
L		 2892008-05-21 H.J. Lu <hongjiu.lu@intel.com>
290
291 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
292 * i386-tbl.h: Regenerated.
293
3ce6fddb
NC		 2942008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
295
296 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
297
8944f3c2
AM		 2982008-05-14 Alan Modra <amodra@bigpond.net.au>
299
300 * Makefile.am: Run "make dep-am".
301 * Makefile.in: Regenerate.
302
f1f8f695
L		 3032008-05-02 H.J. Lu <hongjiu.lu@intel.com>
304
305 * i386-dis.c (MOVBE_Fixup): New.
306 (Mo): Likewise.
307 (PREFIX_0F3880): Likewise.
308 (PREFIX_0F3881): Likewise.
309 (PREFIX_0F38F0): Updated.
310 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
311 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
312 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
313
314 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
315 CPU_EPT_FLAGS.
316 (cpu_flags): Add CpuMovbe and CpuEPT.
317
318 * i386-opc.h (CpuMovbe): New.
319 (CpuEPT): Likewise.
320 (CpuLM): Updated.
321 (i386_cpu_flags): Add cpumovbe and cpuept.
322
323 * i386-opc.tbl: Add entries for movbe and EPT instructions.
324 * i386-init.h: Regenerated.
325 * i386-tbl.h: Likewise.
326
89aa3097
AN		 3272008-04-29 Adam Nemet <anemet@caviumnetworks.com>
328
329 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
330 the two drem and the two dremu macros.
331
39c5c168
AN		 3322008-04-28 Adam Nemet <anemet@caviumnetworks.com>
333
334 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
335 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
336 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
337 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
338
f04d18b7
DM		 3392008-04-25 David S. Miller <davem@davemloft.net>
340
341 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
342 instead of %sys_tick_cmpr, as suggested in architecture manuals.
343
6194aaab
L		 3442008-04-23 Paolo Bonzini <bonzini@gnu.org>
345
346 * aclocal.m4: Regenerate.
347 * configure: Regenerate.
348
1a6b486f
DM		 3492008-04-23 David S. Miller <davem@davemloft.net>
350
351 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
352 extended values.
353 (prefetch_table): Add missing values.
354
81f8a913
L		 3552008-04-22 H.J. Lu <hongjiu.lu@intel.com>
356
357 * i386-gen.c (opcode_modifiers): Add NoAVX.
358
359 * i386-opc.h (NoAVX): New.
360 (OldGcc): Updated.
361 (i386_opcode_modifier): Add noavx.
362
363 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
364 instructions which don't have AVX equivalent.
365 * i386-tbl.h: Regenerated.
366
dae39acc
L		 3672008-04-18 H.J. Lu <hongjiu.lu@intel.com>
368
369 * i386-dis.c (OP_VEX_FMA): New.
370 (OP_EX_VexImmW): Likewise.
371 (VexFMA): Likewise.
372 (Vex128FMA): Likewise.
373 (EXVexImmW): Likewise.
374 (get_vex_imm8): Likewise.
375 (OP_EX_VexReg): Likewise.
376 (vex_i4_done): Renamed to ...
377 (vex_w_done): This.
378 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
379 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
380 FMA instructions.
381 (print_insn): Updated.
382 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
383 (OP_REG_VexI4): Check invalid high registers.
384
ce886ab1
DR		 3852008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
386 Michael Meissner <michael.meissner@amd.com>
387
388 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
389 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 390
19a6653c
AM		 3912008-04-14 Edmar Wienskoski <edmar@freescale.com>
392
393 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
394 accept Power E500MC instructions.
395 (print_ppc_disassembler_options): Document -Me500mc.
396 * ppc-opc.c (DUIS, DUI, T): New.
397 (XRT, XRTRA): Likewise.
398 (E500MC): Likewise.
399 (powerpc_opcodes): Add new Power E500MC instructions.
400
112b7c50
AK		 4012008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
402
403 * s390-dis.c (init_disasm): Evaluate disassembler_options.
404 (print_s390_disassembler_options): New function.
405 * disassemble.c (disassembler_usage): Invoke
406 print_s390_disassembler_options.
407
7ff42648
AK		 4082008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
409
410 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
411 of local variables used for mnemonic parsing: prefix, suffix and
412 number.
413
45a5551e
AK		 4142008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
415
416 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
417 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
418 (s390_crb_extensions): New extensions table.
419 (insertExpandedMnemonic): Handle '$' tag.
420 * s390-opc.txt: Remove conditional jump variants which can now
421 be expanded automatically.
422 Replace '*' tag with '$' in the compare and branch instructions.
423
06c8514a
L		 4242008-04-07 H.J. Lu <hongjiu.lu@intel.com>
425
426 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
427 (PREFIX_VEX_3AXX): Likewis.
428
b122c285
L		 4292008-04-07 H.J. Lu <hongjiu.lu@intel.com>
430
431 * i386-opc.tbl: Remove 4 extra blank lines.
432
594ab6a3
L		 4332008-04-04 H.J. Lu <hongjiu.lu@intel.com>
434
435 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
436 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
437 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
438 * i386-opc.tbl: Likewise.
439
440 * i386-opc.h (CpuCLMUL): Renamed to ...
441 (CpuPCLMUL): This.
442 (CpuFMA): Updated.
443 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
444
445 * i386-init.h: Regenerated.
446
c0f3af97
L		 4472008-04-03 H.J. Lu <hongjiu.lu@intel.com>
448
449 * i386-dis.c (OP_E_register): New.
450 (OP_E_memory): Likewise.
451 (OP_VEX): Likewise.
452 (OP_EX_Vex): Likewise.
453 (OP_EX_VexW): Likewise.
454 (OP_XMM_Vex): Likewise.
455 (OP_XMM_VexW): Likewise.
456 (OP_REG_VexI4): Likewise.
457 (PCLMUL_Fixup): Likewise.
458 (VEXI4_Fixup): Likewise.
459 (VZERO_Fixup): Likewise.
460 (VCMP_Fixup): Likewise.
461 (VPERMIL2_Fixup): Likewise.
462 (rex_original): Likewise.
463 (rex_ignored): Likewise.
464 (Mxmm): Likewise.
465 (XMM): Likewise.
466 (EXxmm): Likewise.
467 (EXxmmq): Likewise.
468 (EXymmq): Likewise.
469 (Vex): Likewise.
470 (Vex128): Likewise.
471 (Vex256): Likewise.
472 (VexI4): Likewise.
473 (EXdVex): Likewise.
474 (EXqVex): Likewise.
475 (EXVexW): Likewise.
476 (EXdVexW): Likewise.
477 (EXqVexW): Likewise.
478 (XMVex): Likewise.
479 (XMVexW): Likewise.
480 (XMVexI4): Likewise.
481 (PCLMUL): Likewise.
482 (VZERO): Likewise.
483 (VCMP): Likewise.
484 (VPERMIL2): Likewise.
485 (xmm_mode): Likewise.
486 (xmmq_mode): Likewise.
487 (ymmq_mode): Likewise.
488 (vex_mode): Likewise.
489 (vex128_mode): Likewise.
490 (vex256_mode): Likewise.
491 (USE_VEX_C4_TABLE): Likewise.
492 (USE_VEX_C5_TABLE): Likewise.
493 (USE_VEX_LEN_TABLE): Likewise.
494 (VEX_C4_TABLE): Likewise.
495 (VEX_C5_TABLE): Likewise.
496 (VEX_LEN_TABLE): Likewise.
497 (REG_VEX_XX): Likewise.
498 (MOD_VEX_XXX): Likewise.
499 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
500 (PREFIX_0F3A44): Likewise.
501 (PREFIX_0F3ADF): Likewise.
502 (PREFIX_VEX_XXX): Likewise.
503 (VEX_OF): Likewise.
504 (VEX_OF38): Likewise.
505 (VEX_OF3A): Likewise.
506 (VEX_LEN_XXX): Likewise.
507 (vex): Likewise.
508 (need_vex): Likewise.
509 (need_vex_reg): Likewise.
510 (vex_i4_done): Likewise.
511 (vex_table): Likewise.
512 (vex_len_table): Likewise.
513 (OP_REG_VexI4): Likewise.
514 (vex_cmp_op): Likewise.
515 (pclmul_op): Likewise.
516 (vpermil2_op): Likewise.
517 (m_mode): Updated.
518 (es_reg): Likewise.
519 (PREFIX_0F38F0): Likewise.
520 (PREFIX_0F3A60): Likewise.
521 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
522 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
523 and PREFIX_VEX_XXX entries.
524 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
525 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
526 PREFIX_0F3ADF.
527 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
528 Add MOD_VEX_XXX entries.
529 (ckprefix): Initialize rex_original and rex_ignored. Store the
530 REX byte in rex_original.
531 (get_valid_dis386): Handle the implicit prefix in VEX prefix
532 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
533 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
534 calling get_valid_dis386. Use rex_original and rex_ignored when
535 printing out REX.
536 (putop): Handle "XY".
537 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
538 ymmq_mode.
539 (OP_E_extended): Updated to use OP_E_register and
540 OP_E_memory.
541 (OP_XMM): Handle VEX.
542 (OP_EX): Likewise.
543 (XMM_Fixup): Likewise.
544 (CMP_Fixup): Use ARRAY_SIZE.
545
546 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
547 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
548 (operand_type_init): Add OPERAND_TYPE_REGYMM and
549 OPERAND_TYPE_VEX_IMM4.
550 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
551 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
552 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
553 VexImmExt and SSE2AVX.
554 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
555
556 * i386-opc.h (CpuAVX): New.
557 (CpuAES): Likewise.
558 (CpuCLMUL): Likewise.
559 (CpuFMA): Likewise.
560 (Vex): Likewise.
561 (Vex256): Likewise.
562 (VexNDS): Likewise.
563 (VexNDD): Likewise.
564 (VexW0): Likewise.
565 (VexW1): Likewise.
566 (Vex0F): Likewise.
567 (Vex0F38): Likewise.
568 (Vex0F3A): Likewise.
569 (Vex3Sources): Likewise.
570 (VexImmExt): Likewise.
571 (SSE2AVX): Likewise.
572 (RegYMM): Likewise.
573 (Ymmword): Likewise.
574 (Vex_Imm4): Likewise.
575 (Implicit1stXmm0): Likewise.
576 (CpuXsave): Updated.
577 (CpuLM): Likewise.
578 (ByteOkIntel): Likewise.
579 (OldGcc): Likewise.
580 (Control): Likewise.
581 (Unspecified): Likewise.
582 (OTMax): Likewise.
583 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
584 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
585 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
586 vex3sources, veximmext and sse2avx.
587 (i386_operand_type): Add regymm, ymmword and vex_imm4.
588
589 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
590
591 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
592
593 * i386-init.h: Regenerated.
594 * i386-tbl.h: Likewise.
595
b21c9cb4
BS		 5962008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
597
598 From Robin Getz <robin.getz@analog.com>
599 * bfin-dis.c (bu32): Typedef.
600 (enum const_forms_t): Add c_uimm32 and c_huimm32.
601 (constant_formats[]): Add uimm32 and huimm16.
602 (fmtconst_val): New.
603 (uimm32): Define.
604 (huimm32): Define.
605 (imm16_val): Define.
606 (luimm16_val): Define.
607 (struct saved_state): Define.
608 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
609 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
610 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
611 (get_allreg): New.
612 (decode_LDIMMhalf_0): Print out the whole register value.
613
ee171c8f
BS		 614 From Jie Zhang <jie.zhang@analog.com>
615 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
616 multiply and multiply-accumulate to data register instruction.
617
086134ec
BS		 618 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
619 c_imm32, c_huimm32e): Define.
620 (constant_formats): Add flags for printing decimal, leading spaces, and
621 exact symbols.
622 (comment, parallel): Add global flags in all disassembly.
623 (fmtconst): Take advantage of new flags, and print default in hex.
624 (fmtconst_val): Likewise.
625 (decode_macfunc): Be consistant with spaces, tabs, comments,
626 capitalization in disassembly, fix minor coding style issues.
627 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
628 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
629 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
630 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
631 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
632 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
633 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
634 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
635 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
636 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
637 _print_insn_bfin, print_insn_bfin): Likewise.
638
58c85be7
RW		 6392008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
640
641 * aclocal.m4: Regenerate.
642 * configure: Likewise.
643 * Makefile.in: Likewise.
644
50e7d84b
AM		 6452008-03-13 Alan Modra <amodra@bigpond.net.au>
646
647 * Makefile.am: Run "make dep-am".
648 * Makefile.in: Regenerate.
649 * configure: Regenerate.
650
de866fcc
AM		 6512008-03-07 Alan Modra <amodra@bigpond.net.au>
652
653 * ppc-opc.c (powerpc_opcodes): Order and format.
654
28dbc079
L		 6552008-03-01 H.J. Lu <hongjiu.lu@intel.com>
656
657 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
658 * i386-tbl.h: Regenerated.
659
849830bd
L		 6602008-02-23 H.J. Lu <hongjiu.lu@intel.com>
661
662 * i386-opc.tbl: Disallow 16-bit near indirect branches for
663 x86-64.
664 * i386-tbl.h: Regenerated.
665
743ddb6b
JB		 6662008-02-21 Jan Beulich <jbeulich@novell.com>
667
668 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
669 and Fword for far indirect jmp. Allow Reg16 and Word for near
670 indirect jmp on x86-64. Disallow Fword for lcall.
671 * i386-tbl.h: Re-generate.
672
796d5313
NC		 6732008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
674
675 * cr16-opc.c (cr16_num_optab): Defined
676
65da13b5
L		 6772008-02-16 H.J. Lu <hongjiu.lu@intel.com>
678
679 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
680 * i386-init.h: Regenerated.
681
0e336180
NC		 6822008-02-14 Nick Clifton <nickc@redhat.com>
683
684 PR binutils/5524
685 * configure.in (SHARED_LIBADD): Select the correct host specific
686 file extension for shared libraries.
687 * configure: Regenerate.
688
b7240065
JB		 6892008-02-13 Jan Beulich <jbeulich@novell.com>
690
691 * i386-opc.h (RegFlat): New.
692 * i386-reg.tbl (flat): Add.
693 * i386-tbl.h: Re-generate.
694
34b772a6
JB		 6952008-02-13 Jan Beulich <jbeulich@novell.com>
696
697 * i386-dis.c (a_mode): New.
698 (cond_jump_mode): Adjust.
699 (Ma): Change to a_mode.
700 (intel_operand_size): Handle a_mode.
701 * i386-opc.tbl: Allow Dword and Qword for bound.
702 * i386-tbl.h: Re-generate.
703
a60de03c
JB		 7042008-02-13 Jan Beulich <jbeulich@novell.com>
705
706 * i386-gen.c (process_i386_registers): Process new fields.
707 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
708 unsigned char. Add dw2_regnum and Dw2Inval.
709 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
710 register names.
711 * i386-tbl.h: Re-generate.
712
f03fe4c1
L		 7132008-02-11 H.J. Lu <hongjiu.lu@intel.com>
714
4b6bc8eb 715 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 716 * i386-init.h: Updated.
717
475a2301
L		 7182008-02-11 H.J. Lu <hongjiu.lu@intel.com>
719
720 * i386-gen.c (cpu_flags): Add CpuXsave.
721
722 * i386-opc.h (CpuXsave): New.
4b6bc8eb 723 (CpuLM): Updated.
475a2301
L		 724 (i386_cpu_flags): Add cpuxsave.
725
726 * i386-dis.c (MOD_0FAE_REG_4): New.
727 (RM_0F01_REG_2): Likewise.
728 (MOD_0FAE_REG_5): Updated.
729 (RM_0F01_REG_3): Likewise.
730 (reg_table): Use MOD_0FAE_REG_4.
731 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
732 for xrstor.
733 (rm_table): Add RM_0F01_REG_2.
734
735 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
736 * i386-init.h: Regenerated.
737 * i386-tbl.h: Likewise.
738
595785c6 7392008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 740
595785c6
JB		 741 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
742 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
743 * i386-tbl.h: Re-generate.
744
bb8541b9
L		 7452008-02-04 H.J. Lu <hongjiu.lu@intel.com>
746
747 PR 5715
748 * configure: Regenerated.
749
57b592a3
AN		 7502008-02-04 Adam Nemet <anemet@caviumnetworks.com>
751
752 * mips-dis.c: Update copyright.
753 (mips_arch_choices): Add Octeon.
754 * mips-opc.c: Update copyright.
755 (IOCT): New macro.
756 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
757
930bb4cf
AM		 7582008-01-29 Alan Modra <amodra@bigpond.net.au>
759
760 * ppc-opc.c: Support optional L form mtmsr.
761
82c18208
L		 7622008-01-24 H.J. Lu <hongjiu.lu@intel.com>
763
764 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
765
599121aa
L		 7662008-01-23 H.J. Lu <hongjiu.lu@intel.com>
767
768 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
769 * i386-init.h: Regenerated.
770
80098f51
TG		 7712008-01-23 Tristan Gingold <gingold@adacore.com>
772
773 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
774 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
775
115c7c25
L		 7762008-01-22 H.J. Lu <hongjiu.lu@intel.com>
777
778 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
779 (cpu_flags): Likewise.
780
781 * i386-opc.h (CpuMMX2): Removed.
782 (CpuSSE): Updated.
783
784 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
785 * i386-init.h: Regenerated.
786 * i386-tbl.h: Likewise.
787
6305a203
L		 7882008-01-22 H.J. Lu <hongjiu.lu@intel.com>
789
790 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
791 CPU_SMX_FLAGS.
792 * i386-init.h: Regenerated.
793
fd07a1c8
L		 7942008-01-15 H.J. Lu <hongjiu.lu@intel.com>
795
796 * i386-opc.tbl: Use Qword on movddup.
797 * i386-tbl.h: Regenerated.
798
321fd21e
L		 7992008-01-15 H.J. Lu <hongjiu.lu@intel.com>
800
801 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
802 * i386-tbl.h: Regenerated.
803
4ee52178
L		 8042008-01-15 H.J. Lu <hongjiu.lu@intel.com>
805
806 * i386-dis.c (Mx): New.
807 (PREFIX_0FC3): Likewise.
808 (PREFIX_0FC7_REG_6): Updated.
809 (dis386_twobyte): Use PREFIX_0FC3.
810 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
811 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
812 movntss.
813
5c07affc
L		 8142008-01-14 H.J. Lu <hongjiu.lu@intel.com>
815
816 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
817 (operand_types): Add Mem.
818
819 * i386-opc.h (IntelSyntax): New.
820 * i386-opc.h (Mem): New.
821 (Byte): Updated.
822 (Opcode_Modifier_Max): Updated.
823 (i386_opcode_modifier): Add intelsyntax.
824 (i386_operand_type): Add mem.
825
826 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
827 instructions.
828
829 * i386-reg.tbl: Add size for accumulator.
830
831 * i386-init.h: Regenerated.
832 * i386-tbl.h: Likewise.
833
0d6a2f58
L		 8342008-01-13 H.J. Lu <hongjiu.lu@intel.com>
835
836 * i386-opc.h (Byte): Fix a typo.
837
7d5e4556
L		 8382008-01-12 H.J. Lu <hongjiu.lu@intel.com>
839
840 PR gas/5534
841 * i386-gen.c (operand_type_init): Add Dword to
842 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
843 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
844 Qword and Xmmword.
845 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
846 Xmmword, Unspecified and Anysize.
847 (set_bitfield): Make Mmword an alias of Qword. Make Oword
848 an alias of Xmmword.
849
850 * i386-opc.h (CheckSize): Removed.
851 (Byte): Updated.
852 (Word): Likewise.
853 (Dword): Likewise.
854 (Qword): Likewise.
855 (Xmmword): Likewise.
856 (FWait): Updated.
857 (OTMax): Likewise.
858 (i386_opcode_modifier): Remove checksize, byte, word, dword,
859 qword and xmmword.
860 (Fword): New.
861 (TBYTE): Likewise.
862 (Unspecified): Likewise.
863 (Anysize): Likewise.
864 (i386_operand_type): Add byte, word, dword, fword, qword,
865 tbyte xmmword, unspecified and anysize.
866
867 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
868 Tbyte, Xmmword, Unspecified and Anysize.
869
870 * i386-reg.tbl: Add size for accumulator.
871
872 * i386-init.h: Regenerated.
873 * i386-tbl.h: Likewise.
874
b5b1fc4f
L		 8752008-01-10 H.J. Lu <hongjiu.lu@intel.com>
876
877 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
878 (REG_0F18): Updated.
879 (reg_table): Updated.
880 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
881 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
882
50e8458f
L		 8832008-01-08 H.J. Lu <hongjiu.lu@intel.com>
884
885 * i386-gen.c (set_bitfield): Use fail () on error.
886
3d4d5afa
L		 8872008-01-08 H.J. Lu <hongjiu.lu@intel.com>
888
889 * i386-gen.c (lineno): New.
890 (filename): Likewise.
891 (set_bitfield): Report filename and line numer on error.
892 (process_i386_opcodes): Set filename and update lineno.
893 (process_i386_registers): Likewise.
894
e1d4d893
L		 8952008-01-05 H.J. Lu <hongjiu.lu@intel.com>
896
897 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
898 ATTSyntax.
899
900 * i386-opc.h (IntelMnemonic): Renamed to ..
901 (ATTSyntax): This
902 (Opcode_Modifier_Max): Updated.
903 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
904 and intelsyntax.
905
8944f3c2 906 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 907 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
908 * i386-tbl.h: Regenerated.
909
6f143e4d
L		 9102008-01-04 H.J. Lu <hongjiu.lu@intel.com>
911
912 * i386-gen.c: Update copyright to 2008.
913 * i386-opc.h: Likewise.
914 * i386-opc.tbl: Likewise.
915
916 * i386-init.h: Regenerated.
917 * i386-tbl.h: Likewise.
918
c6add537
L		 9192008-01-04 H.J. Lu <hongjiu.lu@intel.com>
920
921 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
922 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
923 * i386-tbl.h: Regenerated.
924
3629bb00
L		 9252008-01-03 H.J. Lu <hongjiu.lu@intel.com>
926
927 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
928 CpuSSE4_2_Or_ABM.
929 (cpu_flags): Likewise.
930
931 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
932 (CpuSSE4_2_Or_ABM): Likewise.
933 (CpuLM): Updated.
934 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
935
936 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
937 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
938 and CpuPadLock, respectively.
939 * i386-init.h: Regenerated.
940 * i386-tbl.h: Likewise.
941
24995bd6
L		 9422008-01-03 H.J. Lu <hongjiu.lu@intel.com>
943
944 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
945
946 * i386-opc.h (No_xSuf): Removed.
947 (CheckSize): Updated.
948
949 * i386-tbl.h: Regenerated.
950
e0329a22
L		 9512008-01-02 H.J. Lu <hongjiu.lu@intel.com>
952
953 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
954 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
955 CPU_SSE5_FLAGS.
956 (cpu_flags): Add CpuSSE4_2_Or_ABM.
957
958 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
959 (CpuLM): Updated.
960 (i386_cpu_flags): Add cpusse4_2_or_abm.
961
962 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
963 CpuABM|CpuSSE4_2 on popcnt.
964 * i386-init.h: Regenerated.
965 * i386-tbl.h: Likewise.
966
f2a9c676
L		 9672008-01-02 H.J. Lu <hongjiu.lu@intel.com>
968
969 * i386-opc.h: Update comments.
970
d978b5be
L		 9712008-01-02 H.J. Lu <hongjiu.lu@intel.com>
972
973 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
974 * i386-opc.h: Likewise.
975 * i386-opc.tbl: Likewise.
976
582d5edd
L		 9772008-01-02 H.J. Lu <hongjiu.lu@intel.com>
978
979 PR gas/5534
980 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
981 Byte, Word, Dword, QWord and Xmmword.
982
983 * i386-opc.h (No_xSuf): New.
984 (CheckSize): Likewise.
985 (Byte): Likewise.
986 (Word): Likewise.
987 (Dword): Likewise.
988 (QWord): Likewise.
989 (Xmmword): Likewise.
990 (FWait): Updated.
991 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
992 Dword, QWord and Xmmword.
993
994 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
995 used.
996 * i386-tbl.h: Regenerated.
997
3fe15143
MK		 9982008-01-02 Mark Kettenis <kettenis@gnu.org>
999
1000 * m88k-dis.c (instructions): Fix fcvt.* instructions.
1001 From Miod Vallat.
1002
6c7ac64e 1003For older changes see ChangeLog-2007
252b5132
RH		 1004\f
1005Local Variables:
2f6d2f85
NC		 1006mode: change-log
1007left-margin: 8
1008fill-column: 74
252b5132
RH		 1009version-control: never
1010End:
GDB Binutils - Deliverables
This page took 0.520274 seconds and 4 git commands to generate.