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PR24960, Memory leak from disassembler
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
20135676
AM		 12019-12-10 Alan Modra <amodra@gmail.com>
2
3 PR 24960
4 * disassemble.c (disassemble_free_target): New function.
5
103ebbc3
AM		 62019-12-10 Alan Modra <amodra@gmail.com>
7
8 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
9 * disassemble.c (disassemble_init_for_target): Likewise.
10 * bpf-dis.c: Regenerate.
11 * epiphany-dis.c: Regenerate.
12 * fr30-dis.c: Regenerate.
13 * frv-dis.c: Regenerate.
14 * ip2k-dis.c: Regenerate.
15 * iq2000-dis.c: Regenerate.
16 * lm32-dis.c: Regenerate.
17 * m32c-dis.c: Regenerate.
18 * m32r-dis.c: Regenerate.
19 * mep-dis.c: Regenerate.
20 * mt-dis.c: Regenerate.
21 * or1k-dis.c: Regenerate.
22 * xc16x-dis.c: Regenerate.
23 * xstormy16-dis.c: Regenerate.
24
6f0e0752
AM		 252019-12-10 Alan Modra <amodra@gmail.com>
26
27 * ppc-dis.c (private): Delete variable.
28 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
29 (powerpc_init_dialect): Don't use global private.
30
e7c22a69
AM		 312019-12-10 Alan Modra <amodra@gmail.com>
32
33 * s12z-opc.c: Formatting.
34
0a6aef6b
AM		 352019-12-08 Alan Modra <amodra@gmail.com>
36
37 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
38 registers.
39
2dc4b12f
JB		 402019-12-05 Jan Beulich <jbeulich@suse.com>
41
42 * aarch64-tbl.h (aarch64_feature_crypto,
43 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
44 CRYPTO_V8_2_INSN): Delete.
45
378fd436
AM		 462019-12-05 Alan Modra <amodra@gmail.com>
47
48 PR 25249
49 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
50 (struct string_buf): New.
51 (strbuf): New function.
52 (get_field): Use strbuf rather than strdup of local temp.
53 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
54 (get_field_rfsl, get_field_imm15): Likewise.
55 (get_field_rd, get_field_r1, get_field_r2): Update macros.
56 (get_field_special): Likewise. Don't strcpy spr. Formatting.
57 (print_insn_microblaze): Formatting. Init and pass string_buf to
58 get_field functions.
59
0ba59a29
JB		 602019-12-04 Jan Beulich <jbeulich@suse.com>
61
62 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
63 * i386-tbl.h: Re-generate.
64
77ad8092
JB		 652019-12-04 Jan Beulich <jbeulich@suse.com>
66
67 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
68
3036c899
JB		 692019-12-04 Jan Beulich <jbeulich@suse.com>
70
71 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
72 forms.
73 (xbegin): Drop DefaultSize.
74 * i386-tbl.h: Re-generate.
75
8b301fbb
MI		 762019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
77
78 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
79 Change the coproc CRC conditions to use the extension
80 feature set, second word, base on ARM_EXT2_CRC.
81
6aa385b9
JB		 822019-11-14 Jan Beulich <jbeulich@suse.com>
83
84 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
85 * i386-tbl.h: Re-generate.
86
0cfa3eb3
JB		 872019-11-14 Jan Beulich <jbeulich@suse.com>
88
89 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
90 JumpInterSegment, and JumpAbsolute entries.
91 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
92 JUMP_ABSOLUTE): Define.
93 (struct i386_opcode_modifier): Extend jump field to 3 bits.
94 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
95 fields.
96 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
97 JumpInterSegment): Define.
98 * i386-tbl.h: Re-generate.
99
6f2f06be
JB		 1002019-11-14 Jan Beulich <jbeulich@suse.com>
101
102 * i386-gen.c (operand_type_init): Remove
103 OPERAND_TYPE_JUMPABSOLUTE entry.
104 (opcode_modifiers): Add JumpAbsolute entry.
105 (operand_types): Remove JumpAbsolute entry.
106 * i386-opc.h (JumpAbsolute): Move between enums.
107 (struct i386_opcode_modifier): Add jumpabsolute field.
108 (union i386_operand_type): Remove jumpabsolute field.
109 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
110 * i386-init.h, i386-tbl.h: Re-generate.
111
601e8564
JB		 1122019-11-14 Jan Beulich <jbeulich@suse.com>
113
114 * i386-gen.c (opcode_modifiers): Add AnySize entry.
115 (operand_types): Remove AnySize entry.
116 * i386-opc.h (AnySize): Move between enums.
117 (struct i386_opcode_modifier): Add anysize field.
118 (OTUnused): Un-comment.
119 (union i386_operand_type): Remove anysize field.
120 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
121 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
122 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
123 AnySize.
124 * i386-tbl.h: Re-generate.
125
7722d40a
JW		 1262019-11-12 Nelson Chu <nelson.chu@sifive.com>
127
128 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
129 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
130 use the floating point register (FPR).
131
ce760a76
MI		 1322019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
133
134 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
135 cmode 1101.
136 (is_mve_encoding_conflict): Update cmode conflict checks for
137 MVE_VMVN_IMM.
138
51c8edf6
JB		 1392019-11-12 Jan Beulich <jbeulich@suse.com>
140
141 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
142 entry.
143 (operand_types): Remove EsSeg entry.
144 (main): Replace stale use of OTMax.
145 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
146 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
147 (EsSeg): Delete.
148 (OTUnused): Comment out.
149 (union i386_operand_type): Remove esseg field.
150 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
151 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
152 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
153 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
154 * i386-init.h, i386-tbl.h: Re-generate.
155
474da251
JB		 1562019-11-12 Jan Beulich <jbeulich@suse.com>
157
158 * i386-gen.c (operand_instances): Add RegB entry.
159 * i386-opc.h (enum operand_instance): Add RegB.
160 * i386-opc.tbl (RegC, RegD, RegB): Define.
161 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
162 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
163 monitorx, mwaitx): Drop ImmExt and convert encodings
164 accordingly.
165 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
166 (edx, rdx): Add Instance=RegD.
167 (ebx, rbx): Add Instance=RegB.
168 * i386-tbl.h: Re-generate.
169
75e5731b
JB		 1702019-11-12 Jan Beulich <jbeulich@suse.com>
171
172 * i386-gen.c (operand_type_init): Adjust
173 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
174 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
175 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
176 (operand_instances): New.
177 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
178 (output_operand_type): New parameter "instance". Process it.
179 (process_i386_operand_type): New local variable "instance".
180 (main): Adjust static assertions.
181 * i386-opc.h (INSTANCE_WIDTH): Define.
182 (enum operand_instance): New.
183 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
184 (union i386_operand_type): Replace acc, inoutportreg, and
185 shiftcount by instance.
186 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
187 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
188 Add Instance=.
189 * i386-init.h, i386-tbl.h: Re-generate.
190
91802f3c
JB		 1912019-11-11 Jan Beulich <jbeulich@suse.com>
192
193 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
194 smaxp/sminp entries' "tied_operand" field to 2.
195
4f5fc85d
JB		 1962019-11-11 Jan Beulich <jbeulich@suse.com>
197
198 * aarch64-opc.c (operand_general_constraint_met_p): Replace
199 "index" local variable by that of the already existing "num".
200
dc2be329
L		 2012019-11-08 H.J. Lu <hongjiu.lu@intel.com>
202
203 PR gas/25167
204 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
205 * i386-tbl.h: Regenerated.
206
f74a6307
JB		 2072019-11-08 Jan Beulich <jbeulich@suse.com>
208
209 * i386-gen.c (operand_type_init): Add Class= to
210 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
211 OPERAND_TYPE_REGBND entry.
212 (operand_classes): Add RegMask and RegBND entries.
213 (operand_types): Drop RegMask and RegBND entry.
214 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
215 (RegMask, RegBND): Delete.
216 (union i386_operand_type): Remove regmask and regbnd fields.
217 * i386-opc.tbl (RegMask, RegBND): Define.
218 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
219 Class=RegBND.
220 * i386-init.h, i386-tbl.h: Re-generate.
221
3528c362
JB		 2222019-11-08 Jan Beulich <jbeulich@suse.com>
223
224 * i386-gen.c (operand_type_init): Add Class= to
225 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
226 OPERAND_TYPE_REGZMM entries.
227 (operand_classes): Add RegMMX and RegSIMD entries.
228 (operand_types): Drop RegMMX and RegSIMD entries.
229 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
230 (RegMMX, RegSIMD): Delete.
231 (union i386_operand_type): Remove regmmx and regsimd fields.
232 * i386-opc.tbl (RegMMX): Define.
233 (RegXMM, RegYMM, RegZMM): Add Class=.
234 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
235 Class=RegSIMD.
236 * i386-init.h, i386-tbl.h: Re-generate.
237
4a5c67ed
JB		 2382019-11-08 Jan Beulich <jbeulich@suse.com>
239
240 * i386-gen.c (operand_type_init): Add Class= to
241 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
242 entries.
243 (operand_classes): Add RegCR, RegDR, and RegTR entries.
244 (operand_types): Drop Control, Debug, and Test entries.
245 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
246 (Control, Debug, Test): Delete.
247 (union i386_operand_type): Remove control, debug, and test
248 fields.
249 * i386-opc.tbl (Control, Debug, Test): Define.
250 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
251 Class=RegDR, and Test by Class=RegTR.
252 * i386-init.h, i386-tbl.h: Re-generate.
253
00cee14f
JB		 2542019-11-08 Jan Beulich <jbeulich@suse.com>
255
256 * i386-gen.c (operand_type_init): Add Class= to
257 OPERAND_TYPE_SREG entry.
258 (operand_classes): Add SReg entry.
259 (operand_types): Drop SReg entry.
260 * i386-opc.h (enum operand_class): Add SReg.
261 (SReg): Delete.
262 (union i386_operand_type): Remove sreg field.
263 * i386-opc.tbl (SReg): Define.
264 * i386-reg.tbl: Replace SReg by Class=SReg.
265 * i386-init.h, i386-tbl.h: Re-generate.
266
bab6aec1
JB		 2672019-11-08 Jan Beulich <jbeulich@suse.com>
268
269 * i386-gen.c (operand_type_init): Add Class=. New
270 OPERAND_TYPE_ANYIMM entry.
271 (operand_classes): New.
272 (operand_types): Drop Reg entry.
273 (output_operand_type): New parameter "class". Process it.
274 (process_i386_operand_type): New local variable "class".
275 (main): Adjust static assertions.
276 * i386-opc.h (CLASS_WIDTH): Define.
277 (enum operand_class): New.
278 (Reg): Replace by Class. Adjust comment.
279 (union i386_operand_type): Replace reg by class.
280 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
281 Class=.
282 * i386-reg.tbl: Replace Reg by Class=Reg.
283 * i386-init.h: Re-generate.
284
1f4cd317
MM		 2852019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
286
287 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
288 (aarch64_opcode_table): Add data gathering hint mnemonic.
289 * opcodes/aarch64-dis-2.c: Account for new instruction.
290
616ce08e
MM		 2912019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
292
293 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
294
295
8382113f
MM		 2962019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
297
298 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
299 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
300 aarch64_feature_f64mm): New feature sets.
301 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
302 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
303 instructions.
304 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
305 macros.
306 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
307 (OP_SVE_QQQ): New qualifier.
308 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
309 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
310 the movprfx constraint.
311 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
312 (aarch64_opcode_table): Define new instructions smmla,
313 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
314 uzip{1/2}, trn{1/2}.
315 * aarch64-opc.c (operand_general_constraint_met_p): Handle
316 AARCH64_OPND_SVE_ADDR_RI_S4x32.
317 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
318 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
319 Account for new instructions.
320 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
321 S4x32 operand.
322 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
323
aab2c27d
MM		 3242019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3252019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
326
327 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
328 Armv8.6-A.
329 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
330 (neon_opcodes): Add bfloat SIMD instructions.
331 (print_insn_coprocessor): Add new control character %b to print
332 condition code without checking cp_num.
333 (print_insn_neon): Account for BFloat16 instructions that have no
334 special top-byte handling.
335
33593eaf
MM		 3362019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3372019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
338
339 * arm-dis.c (print_insn_coprocessor,
340 print_insn_generic_coprocessor): Create wrapper functions around
341 the implementation of the print_insn_coprocessor control codes.
342 (print_insn_coprocessor_1): Original print_insn_coprocessor
343 function that now takes which array to look at as an argument.
344 (print_insn_arm): Use both print_insn_coprocessor and
345 print_insn_generic_coprocessor.
346 (print_insn_thumb32): As above.
347
df678013
MM		 3482019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3492019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
350
351 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
352 in reglane special case.
353 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
354 aarch64_find_next_opcode): Account for new instructions.
355 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
356 in reglane special case.
357 * aarch64-opc.c (struct operand_qualifier_data): Add data for
358 new AARCH64_OPND_QLF_S_2H qualifier.
359 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
360 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
361 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
362 sets.
363 (BFLOAT_SVE, BFLOAT): New feature set macros.
364 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
365 instructions.
366 (aarch64_opcode_table): Define new instructions bfdot,
367 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
368 bfcvtn2, bfcvt.
369
8ae2d3d9
MM		 3702019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3712019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
372
373 * aarch64-tbl.h (ARMV8_6): New macro.
374
142861df
JB		 3752019-11-07 Jan Beulich <jbeulich@suse.com>
376
377 * i386-dis.c (prefix_table): Add mcommit.
378 (rm_table): Add rdpru.
379 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
380 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
381 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
382 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
383 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
384 * i386-opc.tbl (mcommit, rdpru): New.
385 * i386-init.h, i386-tbl.h: Re-generate.
386
081e283f
JB		 3872019-11-07 Jan Beulich <jbeulich@suse.com>
388
389 * i386-dis.c (OP_Mwait): Drop local variable "names", use
390 "names32" instead.
391 (OP_Monitor): Drop local variable "op1_names", re-purpose
392 "names" for it instead, and replace former "names" uses by
393 "names32" ones.
394
c050c89a
JB		 3952019-11-07 Jan Beulich <jbeulich@suse.com>
396
397 PR/gas 25167
398 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
399 operand-less forms.
400 * opcodes/i386-tbl.h: Re-generate.
401
7abb8d81
JB		 4022019-11-05 Jan Beulich <jbeulich@suse.com>
403
404 * i386-dis.c (OP_Mwaitx): Delete.
405 (prefix_table): Use OP_Mwait for mwaitx entry.
406 (OP_Mwait): Also handle mwaitx.
407
267b8516
JB		 4082019-11-05 Jan Beulich <jbeulich@suse.com>
409
410 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
411 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
412 (prefix_table): Add respective entries.
413 (rm_table): Link to those entries.
414
f8687e93
JB		 4152019-11-05 Jan Beulich <jbeulich@suse.com>
416
417 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
418 (REG_0F1C_P_0_MOD_0): ... this.
419 (REG_0F1E_MOD_3): Rename to ...
420 (REG_0F1E_P_1_MOD_3): ... this.
421 (RM_0F01_REG_5): Rename to ...
422 (RM_0F01_REG_5_MOD_3): ... this.
423 (RM_0F01_REG_7): Rename to ...
424 (RM_0F01_REG_7_MOD_3): ... this.
425 (RM_0F1E_MOD_3_REG_7): Rename to ...
426 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
427 (RM_0FAE_REG_6): Rename to ...
428 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
429 (RM_0FAE_REG_7): Rename to ...
430 (RM_0FAE_REG_7_MOD_3): ... this.
431 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
432 (PREFIX_0F01_REG_5_MOD_0): ... this.
433 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
434 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
435 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
436 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
437 (PREFIX_0FAE_REG_0): Rename to ...
438 (PREFIX_0FAE_REG_0_MOD_3): ... this.
439 (PREFIX_0FAE_REG_1): Rename to ...
440 (PREFIX_0FAE_REG_1_MOD_3): ... this.
441 (PREFIX_0FAE_REG_2): Rename to ...
442 (PREFIX_0FAE_REG_2_MOD_3): ... this.
443 (PREFIX_0FAE_REG_3): Rename to ...
444 (PREFIX_0FAE_REG_3_MOD_3): ... this.
445 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
446 (PREFIX_0FAE_REG_4_MOD_0): ... this.
447 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
448 (PREFIX_0FAE_REG_4_MOD_3): ... this.
449 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
450 (PREFIX_0FAE_REG_5_MOD_0): ... this.
451 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
452 (PREFIX_0FAE_REG_5_MOD_3): ... this.
453 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
454 (PREFIX_0FAE_REG_6_MOD_0): ... this.
455 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
456 (PREFIX_0FAE_REG_6_MOD_3): ... this.
457 (PREFIX_0FAE_REG_7): Rename to ...
458 (PREFIX_0FAE_REG_7_MOD_0): ... this.
459 (PREFIX_MOD_0_0FC3): Rename to ...
460 (PREFIX_0FC3_MOD_0): ... this.
461 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
462 (PREFIX_0FC7_REG_6_MOD_0): ... this.
463 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
464 (PREFIX_0FC7_REG_6_MOD_3): ... this.
465 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
466 (PREFIX_0FC7_REG_7_MOD_3): ... this.
467 (reg_table, prefix_table, mod_table, rm_table): Adjust
468 accordingly.
469
5103274f
NC		 4702019-11-04 Nick Clifton <nickc@redhat.com>
471
472 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
473 of a v850 system register. Move the v850_sreg_names array into
474 this function.
475 (get_v850_reg_name): Likewise for ordinary register names.
476 (get_v850_vreg_name): Likewise for vector register names.
477 (get_v850_cc_name): Likewise for condition codes.
478 * get_v850_float_cc_name): Likewise for floating point condition
479 codes.
480 (get_v850_cacheop_name): Likewise for cache-ops.
481 (get_v850_prefop_name): Likewise for pref-ops.
482 (disassemble): Use the new accessor functions.
483
1820262b
DB		 4842019-10-30 Delia Burduv <delia.burduv@arm.com>
485
486 * aarch64-opc.c (print_immediate_offset_address): Don't print the
487 immediate for the writeback form of ldraa/ldrab if it is 0.
488 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
489 * aarch64-opc-2.c: Regenerated.
490
3cc17af5
JB		 4912019-10-30 Jan Beulich <jbeulich@suse.com>
492
493 * i386-gen.c (operand_type_shorthands): Delete.
494 (operand_type_init): Expand previous shorthands.
495 (set_bitfield_from_shorthand): Rename back to ...
496 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
497 of operand_type_init[].
498 (set_bitfield): Adjust call to the above function.
499 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
500 RegXMM, RegYMM, RegZMM): Define.
501 * i386-reg.tbl: Expand prior shorthands.
502
a2cebd03
JB		 5032019-10-30 Jan Beulich <jbeulich@suse.com>
504
505 * i386-gen.c (output_i386_opcode): Change order of fields
506 emitted to output.
507 * i386-opc.h (struct insn_template): Move operands field.
508 Convert extension_opcode field to unsigned short.
509 * i386-tbl.h: Re-generate.
510
507916b8
JB		 5112019-10-30 Jan Beulich <jbeulich@suse.com>
512
513 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
514 of W.
515 * i386-opc.h (W): Extend comment.
516 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
517 general purpose variants not allowing for byte operands.
518 * i386-tbl.h: Re-generate.
519
efea62b4
NC		 5202019-10-29 Nick Clifton <nickc@redhat.com>
521
522 * tic30-dis.c (print_branch): Correct size of operand array.
523
9adb2591
NC		 5242019-10-29 Nick Clifton <nickc@redhat.com>
525
526 * d30v-dis.c (print_insn): Check that operand index is valid
527 before attempting to access the operands array.
528
993a00a9
NC		 5292019-10-29 Nick Clifton <nickc@redhat.com>
530
531 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
532 locating the bit to be tested.
533
66a66a17
NC		 5342019-10-29 Nick Clifton <nickc@redhat.com>
535
536 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
537 values.
538 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
539 (print_insn_s12z): Check for illegal size values.
540
1ee3542c
NC		 5412019-10-28 Nick Clifton <nickc@redhat.com>
542
543 * csky-dis.c (csky_chars_to_number): Check for a negative
544 count. Use an unsigned integer to construct the return value.
545
bbf9a0b5
NC		 5462019-10-28 Nick Clifton <nickc@redhat.com>
547
548 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
549 operand buffer. Set value to 15 not 13.
550 (get_register_operand): Use OPERAND_BUFFER_LEN.
551 (get_indirect_operand): Likewise.
552 (print_two_operand): Likewise.
553 (print_three_operand): Likewise.
554 (print_oar_insn): Likewise.
555
d1e304bc
NC		 5562019-10-28 Nick Clifton <nickc@redhat.com>
557
558 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
559 (bit_extract_simple): Likewise.
560 (bit_copy): Likewise.
561 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
562 index_offset array are not accessed.
563
dee33451
NC		 5642019-10-28 Nick Clifton <nickc@redhat.com>
565
566 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
567 operand.
568
27cee81d
NC		 5692019-10-25 Nick Clifton <nickc@redhat.com>
570
571 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
572 access to opcodes.op array element.
573
de6d8dc2
NC		 5742019-10-23 Nick Clifton <nickc@redhat.com>
575
576 * rx-dis.c (get_register_name): Fix spelling typo in error
577 message.
578 (get_condition_name, get_flag_name, get_double_register_name)
579 (get_double_register_high_name, get_double_register_low_name)
580 (get_double_control_register_name, get_double_condition_name)
581 (get_opsize_name, get_size_name): Likewise.
582
6207ed28
NC		 5832019-10-22 Nick Clifton <nickc@redhat.com>
584
585 * rx-dis.c (get_size_name): New function. Provides safe
586 access to name array.
587 (get_opsize_name): Likewise.
588 (print_insn_rx): Use the accessor functions.
589
12234dfd
NC		 5902019-10-16 Nick Clifton <nickc@redhat.com>
591
592 * rx-dis.c (get_register_name): New function. Provides safe
593 access to name array.
594 (get_condition_name, get_flag_name, get_double_register_name)
595 (get_double_register_high_name, get_double_register_low_name)
596 (get_double_control_register_name, get_double_condition_name):
597 Likewise.
598 (print_insn_rx): Use the accessor functions.
599
1d378749
NC		 6002019-10-09 Nick Clifton <nickc@redhat.com>
601
602 PR 25041
603 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
604 instructions.
605
d241b910
JB		 6062019-10-07 Jan Beulich <jbeulich@suse.com>
607
608 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
609 (cmpsd): Likewise. Move EsSeg to other operand.
610 * opcodes/i386-tbl.h: Re-generate.
611
f5c5b7c1
AM		 6122019-09-23 Alan Modra <amodra@gmail.com>
613
614 * m68k-dis.c: Include cpu-m68k.h
615
7beeaeb8
AM		 6162019-09-23 Alan Modra <amodra@gmail.com>
617
618 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
619 "elf/mips.h" earlier.
620
3f9aad11
JB		 6212018-09-20 Jan Beulich <jbeulich@suse.com>
622
623 PR gas/25012
624 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
625 with SReg operand.
626 * i386-tbl.h: Re-generate.
627
fd361982
AM		 6282019-09-18 Alan Modra <amodra@gmail.com>
629
630 * arc-ext.c: Update throughout for bfd section macro changes.
631
e0b2a78c
SM		 6322019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
633
634 * Makefile.in: Re-generate.
635 * configure: Re-generate.
636
7e9ad3a3
JW		 6372019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
638
639 * riscv-opc.c (riscv_opcodes): Change subset field
640 to insn_class field for all instructions.
641 (riscv_insn_types): Likewise.
642
bb695960
PB		 6432019-09-16 Phil Blundell <pb@pbcl.net>
644
645 * configure: Regenerated.
646
8063ab7e
MV		 6472019-09-10 Miod Vallat <miod@online.fr>
648
649 PR 24982
650 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
651
60391a25
PB		 6522019-09-09 Phil Blundell <pb@pbcl.net>
653
654 binutils 2.33 branch created.
655
f44b758d
NC		 6562019-09-03 Nick Clifton <nickc@redhat.com>
657
658 PR 24961
659 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
660 greater than zero before indexing via (bufcnt -1).
661
1e4b5e7d
NC		 6622019-09-03 Nick Clifton <nickc@redhat.com>
663
664 PR 24958
665 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
666 (MAX_SPEC_REG_NAME_LEN): Define.
667 (struct mmix_dis_info): Use defined constants for array lengths.
668 (get_reg_name): New function.
669 (get_sprec_reg_name): New function.
670 (print_insn_mmix): Use new functions.
671
c4a23bf8
SP		 6722019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
673
674 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
675 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
676 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
677
a051e2f3
KT		 6782019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
679
680 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
681 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
682 (aarch64_sys_reg_supported_p): Update checks for the above.
683
08132bdd
SP		 6842019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
685
686 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
687 cases MVE_SQRSHRL and MVE_UQRSHLL.
688 (print_insn_mve): Add case for specifier 'k' to check
689 specific bit of the instruction.
690
d88bdcb4
PA		 6912019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
692
693 PR 24854
694 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
695 encountering an unknown machine type.
696 (print_insn_arc): Handle arc_insn_length returning 0. In error
697 cases return -1 rather than calling abort.
698
bc750500
JB		 6992019-08-07 Jan Beulich <jbeulich@suse.com>
700
701 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
702 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
703 IgnoreSize.
704 * i386-tbl.h: Re-generate.
705
23d188c7
BW		 7062019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
707
708 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
709 instructions.
710
c0d6f62f
JW		 7112019-07-30 Mel Chen <mel.chen@sifive.com>
712
713 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
714 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
715
716 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
717 fscsr.
718
0f3f7167
CZ		 7192019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
720
721 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
722 and MPY class instructions.
723 (parse_option): Add nps400 option.
724 (print_arc_disassembler_options): Add nps400 info.
725
7e126ba3
CZ		 7262019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
727
728 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
729 (bspop): Likewise.
730 (modapp): Likewise.
731 * arc-opc.c (RAD_CHK): Add.
732 * arc-tbl.h: Regenerate.
733
a028026d
KT		 7342019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
735
736 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
737 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
738
ac79ff9e
NC		 7392019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
740
741 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
742 instructions as UNPREDICTABLE.
743
231097b0
JM		 7442019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
745
746 * bpf-desc.c: Regenerated.
747
1d942ae9
JB		 7482019-07-17 Jan Beulich <jbeulich@suse.com>
749
750 * i386-gen.c (static_assert): Define.
751 (main): Use it.
752 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
753 (Opcode_Modifier_Num): ... this.
754 (Mem): Delete.
755
dfd69174
JB		 7562019-07-16 Jan Beulich <jbeulich@suse.com>
757
758 * i386-gen.c (operand_types): Move RegMem ...
759 (opcode_modifiers): ... here.
760 * i386-opc.h (RegMem): Move to opcode modifer enum.
761 (union i386_operand_type): Move regmem field ...
762 (struct i386_opcode_modifier): ... here.
763 * i386-opc.tbl (RegMem): Define.
764 (mov, movq): Move RegMem on segment, control, debug, and test
765 register flavors.
766 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
767 to non-SSE2AVX flavor.
768 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
769 Move RegMem on register only flavors. Drop IgnoreSize from
770 legacy encoding flavors.
771 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
772 flavors.
773 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
774 register only flavors.
775 (vmovd): Move RegMem and drop IgnoreSize on register only
776 flavor. Change opcode and operand order to store form.
777 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
778
21df382b
JB		 7792019-07-16 Jan Beulich <jbeulich@suse.com>
780
781 * i386-gen.c (operand_type_init, operand_types): Replace SReg
782 entries.
783 * i386-opc.h (SReg2, SReg3): Replace by ...
784 (SReg): ... this.
785 (union i386_operand_type): Replace sreg fields.
786 * i386-opc.tbl (mov, ): Use SReg.
787 (push, pop): Likewies. Drop i386 and x86-64 specific segment
788 register flavors.
789 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
790 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
791
3719fd55
JM		 7922019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
793
794 * bpf-desc.c: Regenerate.
795 * bpf-opc.c: Likewise.
796 * bpf-opc.h: Likewise.
797
92434a14
JM		 7982019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
799
800 * bpf-desc.c: Regenerate.
801 * bpf-opc.c: Likewise.
802
43dd7626
HPN		 8032019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
804
805 * arm-dis.c (print_insn_coprocessor): Rename index to
806 index_operand.
807
98602811
JW		 8082019-07-05 Kito Cheng <kito.cheng@sifive.com>
809
810 * riscv-opc.c (riscv_insn_types): Add r4 type.
811
812 * riscv-opc.c (riscv_insn_types): Add b and j type.
813
814 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
815 format for sb type and correct s type.
816
01c1ee4a
RS		 8172019-07-02 Richard Sandiford <richard.sandiford@arm.com>
818
819 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
820 SVE FMOV alias of FCPY.
821
83adff69
RS		 8222019-07-02 Richard Sandiford <richard.sandiford@arm.com>
823
824 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
825 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
826
89418844
RS		 8272019-07-02 Richard Sandiford <richard.sandiford@arm.com>
828
829 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
830 registers in an instruction prefixed by MOVPRFX.
831
41be57ca
MM		 8322019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
833
834 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
835 sve_size_13 icode to account for variant behaviour of
836 pmull{t,b}.
837 * aarch64-dis-2.c: Regenerate.
838 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
839 sve_size_13 icode to account for variant behaviour of
840 pmull{t,b}.
841 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
842 (OP_SVE_VVV_Q_D): Add new qualifier.
843 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
844 (struct aarch64_opcode): Split pmull{t,b} into those requiring
845 AES and those not.
846
9d3bf266
JB		 8472019-07-01 Jan Beulich <jbeulich@suse.com>
848
849 * opcodes/i386-gen.c (operand_type_init): Remove
850 OPERAND_TYPE_VEC_IMM4 entry.
851 (operand_types): Remove Vec_Imm4.
852 * opcodes/i386-opc.h (Vec_Imm4): Delete.
853 (union i386_operand_type): Remove vec_imm4.
854 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
855 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
856
c3949f43
JB		 8572019-07-01 Jan Beulich <jbeulich@suse.com>
858
859 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
860 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
861 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
862 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
863 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
864 monitorx, mwaitx): Drop ImmExt from operand-less forms.
865 * i386-tbl.h: Re-generate.
866
5641ec01
JB		 8672019-07-01 Jan Beulich <jbeulich@suse.com>
868
869 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
870 register operands.
871 * i386-tbl.h: Re-generate.
872
79dec6b7
JB		 8732019-07-01 Jan Beulich <jbeulich@suse.com>
874
875 * i386-opc.tbl (C): New.
876 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
877 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
878 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
879 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
880 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
881 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
882 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
883 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
884 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
885 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
886 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
887 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
888 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
889 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
890 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
891 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
892 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
893 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
894 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
895 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
896 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
897 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
898 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
899 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
900 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
901 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
902 flavors.
903 * i386-tbl.h: Re-generate.
904
a0a1771e
JB		 9052019-07-01 Jan Beulich <jbeulich@suse.com>
906
907 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
908 register operands.
909 * i386-tbl.h: Re-generate.
910
cd546e7b
JB		 9112019-07-01 Jan Beulich <jbeulich@suse.com>
912
913 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
914 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
915 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
916 * i386-tbl.h: Re-generate.
917
e3bba3fc
JB		 9182019-07-01 Jan Beulich <jbeulich@suse.com>
919
920 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
921 Disp8MemShift from register only templates.
922 * i386-tbl.h: Re-generate.
923
36cc073e
JB		 9242019-07-01 Jan Beulich <jbeulich@suse.com>
925
926 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
927 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
928 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
929 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
930 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
931 EVEX_W_0F11_P_3_M_1): Delete.
932 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
933 EVEX_W_0F11_P_3): New.
934 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
935 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
936 MOD_EVEX_0F11_PREFIX_3 table entries.
937 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
938 PREFIX_EVEX_0F11 table entries.
939 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
940 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
941 EVEX_W_0F11_P_3_M_{0,1} table entries.
942
219920a7
JB		 9432019-07-01 Jan Beulich <jbeulich@suse.com>
944
945 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
946 Delete.
947
e395f487
L		 9482019-06-27 H.J. Lu <hongjiu.lu@intel.com>
949
950 PR binutils/24719
951 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
952 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
953 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
954 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
955 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
956 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
957 EVEX_LEN_0F38C7_R_6_P_2_W_1.
958 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
959 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
960 PREFIX_EVEX_0F38C6_REG_6 entries.
961 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
962 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
963 EVEX_W_0F38C7_R_6_P_2 entries.
964 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
965 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
966 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
967 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
968 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
969 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
970 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
971
2b7bcc87
JB		 9722019-06-27 Jan Beulich <jbeulich@suse.com>
973
974 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
975 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
976 VEX_LEN_0F2D_P_3): Delete.
977 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
978 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
979 (prefix_table): ... here.
980
c1dc7af5
JB		 9812019-06-27 Jan Beulich <jbeulich@suse.com>
982
983 * i386-dis.c (Iq): Delete.
984 (Id): New.
985 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
986 TBM insns.
987 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
988 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
989 (OP_E_memory): Also honor needindex when deciding whether an
990 address size prefix needs printing.
991 (OP_I): Remove handling of q_mode. Add handling of d_mode.
992
d7560e2d
JW		 9932019-06-26 Jim Wilson <jimw@sifive.com>
994
995 PR binutils/24739
996 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
997 Set info->display_endian to info->endian_code.
998
2c703856
JB		 9992019-06-25 Jan Beulich <jbeulich@suse.com>
1000
1001 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1002 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1003 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1004 OPERAND_TYPE_ACC64 entries.
1005 * i386-init.h: Re-generate.
1006
54fbadc0
JB		 10072019-06-25 Jan Beulich <jbeulich@suse.com>
1008
1009 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1010 Delete.
1011 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1012 of dqa_mode.
1013 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1014 entries here.
1015 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1016 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1017
a280ab8e
JB		 10182019-06-25 Jan Beulich <jbeulich@suse.com>
1019
1020 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1021 variables.
1022
e1a1babd
JB		 10232019-06-25 Jan Beulich <jbeulich@suse.com>
1024
1025 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1026 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1027 movnti.
d7560e2d 1028 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1029 * i386-tbl.h: Re-generate.
1030
b8364fa7
JB		 10312019-06-25 Jan Beulich <jbeulich@suse.com>
1032
1033 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1034 * i386-tbl.h: Re-generate.
1035
ad692897
L		 10362019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1037
1038 * i386-dis-evex.h: Break into ...
1039 * i386-dis-evex-len.h: New file.
1040 * i386-dis-evex-mod.h: Likewise.
1041 * i386-dis-evex-prefix.h: Likewise.
1042 * i386-dis-evex-reg.h: Likewise.
1043 * i386-dis-evex-w.h: Likewise.
1044 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1045 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1046 i386-dis-evex-mod.h.
1047
f0a6222e
L		 10482019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1049
1050 PR binutils/24700
1051 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1052 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1053 EVEX_W_0F385B_P_2.
1054 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1055 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1056 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1057 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1058 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1059 EVEX_LEN_0F385B_P_2_W_1.
1060 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1061 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1062 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1063 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1064 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1065 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1066 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1067 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1068 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1069 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1070
6e1c90b7
L		 10712019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1072
1073 PR binutils/24691
1074 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1075 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1076 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1077 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1078 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1079 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1080 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1081 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1082 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1083 EVEX_LEN_0F3A43_P_2_W_1.
1084 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1085 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1086 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1087 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1088 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1089 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1090 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1091 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1092 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1093 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1094 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1095 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1096
bcc5a6eb
NC		 10972019-06-14 Nick Clifton <nickc@redhat.com>
1098
1099 * po/fr.po; Updated French translation.
1100
e4c4ac46
SH		 11012019-06-13 Stafford Horne <shorne@gmail.com>
1102
1103 * or1k-asm.c: Regenerated.
1104 * or1k-desc.c: Regenerated.
1105 * or1k-desc.h: Regenerated.
1106 * or1k-dis.c: Regenerated.
1107 * or1k-ibld.c: Regenerated.
1108 * or1k-opc.c: Regenerated.
1109 * or1k-opc.h: Regenerated.
1110 * or1k-opinst.c: Regenerated.
1111
a0e44ef5
PB		 11122019-06-12 Peter Bergner <bergner@linux.ibm.com>
1113
1114 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1115
12efd68d
L		 11162019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1117
1118 PR binutils/24633
1119 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1120 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1121 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1122 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1123 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1124 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1125 EVEX_LEN_0F3A1B_P_2_W_1.
1126 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1127 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1128 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1129 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1130 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1131 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1132 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1133 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1134
63c6fc6c
L		 11352019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1136
1137 PR binutils/24626
1138 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1139 EVEX.vvvv when disassembling VEX and EVEX instructions.
1140 (OP_VEX): Set vex.register_specifier to 0 after readding
1141 vex.register_specifier.
1142 (OP_Vex_2src_1): Likewise.
1143 (OP_Vex_2src_2): Likewise.
1144 (OP_LWP_E): Likewise.
1145 (OP_EX_Vex): Don't check vex.register_specifier.
1146 (OP_XMM_Vex): Likewise.
1147
9186c494
L		 11482019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1149 Lili Cui <lili.cui@intel.com>
1150
1151 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1152 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1153 instructions.
1154 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1155 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1156 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1157 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1158 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1159 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1160 * i386-init.h: Regenerated.
1161 * i386-tbl.h: Likewise.
1162
5d79adc4
L		 11632019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1164 Lili Cui <lili.cui@intel.com>
1165
1166 * doc/c-i386.texi: Document enqcmd.
1167 * testsuite/gas/i386/enqcmd-intel.d: New file.
1168 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1169 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1170 * testsuite/gas/i386/enqcmd.d: Likewise.
1171 * testsuite/gas/i386/enqcmd.s: Likewise.
1172 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1173 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1174 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1175 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1176 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1177 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1178 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1179 and x86-64-enqcmd.
1180
a9d96ab9
AH		 11812019-06-04 Alan Hayward <alan.hayward@arm.com>
1182
1183 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1184
4f6d070a
AM		 11852019-06-03 Alan Modra <amodra@gmail.com>
1186
1187 * ppc-dis.c (prefix_opcd_indices): Correct size.
1188
a2f4b66c
L		 11892019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1190
1191 PR gas/24625
1192 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1193 Disp8ShiftVL.
1194 * i386-tbl.h: Regenerated.
1195
405b5bd8
AM		 11962019-05-24 Alan Modra <amodra@gmail.com>
1197
1198 * po/POTFILES.in: Regenerate.
1199
8acf1435
PB		 12002019-05-24 Peter Bergner <bergner@linux.ibm.com>
1201 Alan Modra <amodra@gmail.com>
1202
1203 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1204 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1205 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1206 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1207 XTOP>): Define and add entries.
1208 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1209 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1210 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1211 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1212
dd7efa79
PB		 12132019-05-24 Peter Bergner <bergner@linux.ibm.com>
1214 Alan Modra <amodra@gmail.com>
1215
1216 * ppc-dis.c (ppc_opts): Add "future" entry.
1217 (PREFIX_OPCD_SEGS): Define.
1218 (prefix_opcd_indices): New array.
1219 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1220 (lookup_prefix): New function.
1221 (print_insn_powerpc): Handle 64-bit prefix instructions.
1222 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1223 (PMRR, POWERXX): Define.
1224 (prefix_opcodes): New instruction table.
1225 (prefix_num_opcodes): New constant.
1226
79472b45
JM		 12272019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1228
1229 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1230 * configure: Regenerated.
1231 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1232 and cpu/bpf.opc.
1233 (HFILES): Add bpf-desc.h and bpf-opc.h.
1234 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1235 bpf-ibld.c and bpf-opc.c.
1236 (BPF_DEPS): Define.
1237 * Makefile.in: Regenerated.
1238 * disassemble.c (ARCH_bpf): Define.
1239 (disassembler): Add case for bfd_arch_bpf.
1240 (disassemble_init_for_target): Likewise.
1241 (enum epbf_isa_attr): Define.
1242 * disassemble.h: extern print_insn_bpf.
1243 * bpf-asm.c: Generated.
1244 * bpf-opc.h: Likewise.
1245 * bpf-opc.c: Likewise.
1246 * bpf-ibld.c: Likewise.
1247 * bpf-dis.c: Likewise.
1248 * bpf-desc.h: Likewise.
1249 * bpf-desc.c: Likewise.
1250
ba6cd17f
SD		 12512019-05-21 Sudakshina Das <sudi.das@arm.com>
1252
1253 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1254 and VMSR with the new operands.
1255
e39c1607
SD		 12562019-05-21 Sudakshina Das <sudi.das@arm.com>
1257
1258 * arm-dis.c (enum mve_instructions): New enum
1259 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1260 and cneg.
1261 (mve_opcodes): New instructions as above.
1262 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1263 csneg and csel.
1264 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1265
23d00a41
SD		 12662019-05-21 Sudakshina Das <sudi.das@arm.com>
1267
1268 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1269 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1270 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1271 uqshl, urshrl and urshr.
1272 (is_mve_okay_in_it): Add new instructions to TRUE list.
1273 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1274 (print_insn_mve): Updated to accept new %j,
1275 %<bitfield>m and %<bitfield>n patterns.
1276
cd4797ee
FS		 12772019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1278
1279 * mips-opc.c (mips_builtin_opcodes): Change source register
1280 constraint for DAUI.
1281
999b073b
NC		 12822019-05-20 Nick Clifton <nickc@redhat.com>
1283
1284 * po/fr.po: Updated French translation.
1285
14b456f2
AV		 12862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1287 Michael Collison <michael.collison@arm.com>
1288
1289 * arm-dis.c (thumb32_opcodes): Add new instructions.
1290 (enum mve_instructions): Likewise.
1291 (enum mve_undefined): Add new reasons.
1292 (is_mve_encoding_conflict): Handle new instructions.
1293 (is_mve_undefined): Likewise.
1294 (is_mve_unpredictable): Likewise.
1295 (print_mve_undefined): Likewise.
1296 (print_mve_size): Likewise.
1297
f49bb598
AV		 12982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1299 Michael Collison <michael.collison@arm.com>
1300
1301 * arm-dis.c (thumb32_opcodes): Add new instructions.
1302 (enum mve_instructions): Likewise.
1303 (is_mve_encoding_conflict): Handle new instructions.
1304 (is_mve_undefined): Likewise.
1305 (is_mve_unpredictable): Likewise.
1306 (print_mve_size): Likewise.
1307
56858bea
AV		 13082019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1309 Michael Collison <michael.collison@arm.com>
1310
1311 * arm-dis.c (thumb32_opcodes): Add new instructions.
1312 (enum mve_instructions): Likewise.
1313 (is_mve_encoding_conflict): Likewise.
1314 (is_mve_unpredictable): Likewise.
1315 (print_mve_size): Likewise.
1316
e523f101
AV		 13172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1318 Michael Collison <michael.collison@arm.com>
1319
1320 * arm-dis.c (thumb32_opcodes): Add new instructions.
1321 (enum mve_instructions): Likewise.
1322 (is_mve_encoding_conflict): Handle new instructions.
1323 (is_mve_undefined): Likewise.
1324 (is_mve_unpredictable): Likewise.
1325 (print_mve_size): Likewise.
1326
66dcaa5d
AV		 13272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1328 Michael Collison <michael.collison@arm.com>
1329
1330 * arm-dis.c (thumb32_opcodes): Add new instructions.
1331 (enum mve_instructions): Likewise.
1332 (is_mve_encoding_conflict): Handle new instructions.
1333 (is_mve_undefined): Likewise.
1334 (is_mve_unpredictable): Likewise.
1335 (print_mve_size): Likewise.
1336 (print_insn_mve): Likewise.
1337
d052b9b7
AV		 13382019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1339 Michael Collison <michael.collison@arm.com>
1340
1341 * arm-dis.c (thumb32_opcodes): Add new instructions.
1342 (print_insn_thumb32): Handle new instructions.
1343
ed63aa17
AV		 13442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1345 Michael Collison <michael.collison@arm.com>
1346
1347 * arm-dis.c (enum mve_instructions): Add new instructions.
1348 (enum mve_undefined): Add new reasons.
1349 (is_mve_encoding_conflict): Handle new instructions.
1350 (is_mve_undefined): Likewise.
1351 (is_mve_unpredictable): Likewise.
1352 (print_mve_undefined): Likewise.
1353 (print_mve_size): Likewise.
1354 (print_mve_shift_n): Likewise.
1355 (print_insn_mve): Likewise.
1356
897b9bbc
AV		 13572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1358 Michael Collison <michael.collison@arm.com>
1359
1360 * arm-dis.c (enum mve_instructions): Add new instructions.
1361 (is_mve_encoding_conflict): Handle new instructions.
1362 (is_mve_unpredictable): Likewise.
1363 (print_mve_rotate): Likewise.
1364 (print_mve_size): Likewise.
1365 (print_insn_mve): Likewise.
1366
1c8f2df8
AV		 13672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1368 Michael Collison <michael.collison@arm.com>
1369
1370 * arm-dis.c (enum mve_instructions): Add new instructions.
1371 (is_mve_encoding_conflict): Handle new instructions.
1372 (is_mve_unpredictable): Likewise.
1373 (print_mve_size): Likewise.
1374 (print_insn_mve): Likewise.
1375
d3b63143
AV		 13762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1377 Michael Collison <michael.collison@arm.com>
1378
1379 * arm-dis.c (enum mve_instructions): Add new instructions.
1380 (enum mve_undefined): Add new reasons.
1381 (is_mve_encoding_conflict): Handle new instructions.
1382 (is_mve_undefined): Likewise.
1383 (is_mve_unpredictable): Likewise.
1384 (print_mve_undefined): Likewise.
1385 (print_mve_size): Likewise.
1386 (print_insn_mve): Likewise.
1387
14925797
AV		 13882019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1389 Michael Collison <michael.collison@arm.com>
1390
1391 * arm-dis.c (enum mve_instructions): Add new instructions.
1392 (is_mve_encoding_conflict): Handle new instructions.
1393 (is_mve_undefined): Likewise.
1394 (is_mve_unpredictable): Likewise.
1395 (print_mve_size): Likewise.
1396 (print_insn_mve): Likewise.
1397
c507f10b
AV		 13982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1399 Michael Collison <michael.collison@arm.com>
1400
1401 * arm-dis.c (enum mve_instructions): Add new instructions.
1402 (enum mve_unpredictable): Add new reasons.
1403 (enum mve_undefined): Likewise.
1404 (is_mve_okay_in_it): Handle new isntructions.
1405 (is_mve_encoding_conflict): Likewise.
1406 (is_mve_undefined): Likewise.
1407 (is_mve_unpredictable): Likewise.
1408 (print_mve_vmov_index): Likewise.
1409 (print_simd_imm8): Likewise.
1410 (print_mve_undefined): Likewise.
1411 (print_mve_unpredictable): Likewise.
1412 (print_mve_size): Likewise.
1413 (print_insn_mve): Likewise.
1414
bf0b396d
AV		 14152019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1416 Michael Collison <michael.collison@arm.com>
1417
1418 * arm-dis.c (enum mve_instructions): Add new instructions.
1419 (enum mve_unpredictable): Add new reasons.
1420 (enum mve_undefined): Likewise.
1421 (is_mve_encoding_conflict): Handle new instructions.
1422 (is_mve_undefined): Likewise.
1423 (is_mve_unpredictable): Likewise.
1424 (print_mve_undefined): Likewise.
1425 (print_mve_unpredictable): Likewise.
1426 (print_mve_rounding_mode): Likewise.
1427 (print_mve_vcvt_size): Likewise.
1428 (print_mve_size): Likewise.
1429 (print_insn_mve): Likewise.
1430
ef1576a1
AV		 14312019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1432 Michael Collison <michael.collison@arm.com>
1433
1434 * arm-dis.c (enum mve_instructions): Add new instructions.
1435 (enum mve_unpredictable): Add new reasons.
1436 (enum mve_undefined): Likewise.
1437 (is_mve_undefined): Handle new instructions.
1438 (is_mve_unpredictable): Likewise.
1439 (print_mve_undefined): Likewise.
1440 (print_mve_unpredictable): Likewise.
1441 (print_mve_size): Likewise.
1442 (print_insn_mve): Likewise.
1443
aef6d006
AV		 14442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1445 Michael Collison <michael.collison@arm.com>
1446
1447 * arm-dis.c (enum mve_instructions): Add new instructions.
1448 (enum mve_undefined): Add new reasons.
1449 (insns): Add new instructions.
1450 (is_mve_encoding_conflict):
1451 (print_mve_vld_str_addr): New print function.
1452 (is_mve_undefined): Handle new instructions.
1453 (is_mve_unpredictable): Likewise.
1454 (print_mve_undefined): Likewise.
1455 (print_mve_size): Likewise.
1456 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1457 (print_insn_mve): Handle new operands.
1458
04d54ace
AV		 14592019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1460 Michael Collison <michael.collison@arm.com>
1461
1462 * arm-dis.c (enum mve_instructions): Add new instructions.
1463 (enum mve_unpredictable): Add new reasons.
1464 (is_mve_encoding_conflict): Handle new instructions.
1465 (is_mve_unpredictable): Likewise.
1466 (mve_opcodes): Add new instructions.
1467 (print_mve_unpredictable): Handle new reasons.
1468 (print_mve_register_blocks): New print function.
1469 (print_mve_size): Handle new instructions.
1470 (print_insn_mve): Likewise.
1471
9743db03
AV		 14722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1473 Michael Collison <michael.collison@arm.com>
1474
1475 * arm-dis.c (enum mve_instructions): Add new instructions.
1476 (enum mve_unpredictable): Add new reasons.
1477 (enum mve_undefined): Likewise.
1478 (is_mve_encoding_conflict): Handle new instructions.
1479 (is_mve_undefined): Likewise.
1480 (is_mve_unpredictable): Likewise.
1481 (coprocessor_opcodes): Move NEON VDUP from here...
1482 (neon_opcodes): ... to here.
1483 (mve_opcodes): Add new instructions.
1484 (print_mve_undefined): Handle new reasons.
1485 (print_mve_unpredictable): Likewise.
1486 (print_mve_size): Handle new instructions.
1487 (print_insn_neon): Handle vdup.
1488 (print_insn_mve): Handle new operands.
1489
143275ea
AV		 14902019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1491 Michael Collison <michael.collison@arm.com>
1492
1493 * arm-dis.c (enum mve_instructions): Add new instructions.
1494 (enum mve_unpredictable): Add new values.
1495 (mve_opcodes): Add new instructions.
1496 (vec_condnames): New array with vector conditions.
1497 (mve_predicatenames): New array with predicate suffixes.
1498 (mve_vec_sizename): New array with vector sizes.
1499 (enum vpt_pred_state): New enum with vector predication states.
1500 (struct vpt_block): New struct type for vpt blocks.
1501 (vpt_block_state): Global struct to keep track of state.
1502 (mve_extract_pred_mask): New helper function.
1503 (num_instructions_vpt_block): Likewise.
1504 (mark_outside_vpt_block): Likewise.
1505 (mark_inside_vpt_block): Likewise.
1506 (invert_next_predicate_state): Likewise.
1507 (update_next_predicate_state): Likewise.
1508 (update_vpt_block_state): Likewise.
1509 (is_vpt_instruction): Likewise.
1510 (is_mve_encoding_conflict): Add entries for new instructions.
1511 (is_mve_unpredictable): Likewise.
1512 (print_mve_unpredictable): Handle new cases.
1513 (print_instruction_predicate): Likewise.
1514 (print_mve_size): New function.
1515 (print_vec_condition): New function.
1516 (print_insn_mve): Handle vpt blocks and new print operands.
1517
f08d8ce3
AV		 15182019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1519
1520 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1521 8, 14 and 15 for Armv8.1-M Mainline.
1522
73cd51e5
AV		 15232019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1524 Michael Collison <michael.collison@arm.com>
1525
1526 * arm-dis.c (enum mve_instructions): New enum.
1527 (enum mve_unpredictable): Likewise.
1528 (enum mve_undefined): Likewise.
1529 (struct mopcode32): New struct.
1530 (is_mve_okay_in_it): New function.
1531 (is_mve_architecture): Likewise.
1532 (arm_decode_field): Likewise.
1533 (arm_decode_field_multiple): Likewise.
1534 (is_mve_encoding_conflict): Likewise.
1535 (is_mve_undefined): Likewise.
1536 (is_mve_unpredictable): Likewise.
1537 (print_mve_undefined): Likewise.
1538 (print_mve_unpredictable): Likewise.
1539 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1540 (print_insn_mve): New function.
1541 (print_insn_thumb32): Handle MVE architecture.
1542 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1543
3076e594
NC		 15442019-05-10 Nick Clifton <nickc@redhat.com>
1545
1546 PR 24538
1547 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1548 end of the table prematurely.
1549
387e7624
FS		 15502019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1551
1552 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1553 macros for R6.
1554
0067be51
AM		 15552019-05-11 Alan Modra <amodra@gmail.com>
1556
1557 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1558 when -Mraw is in effect.
1559
42e6288f
MM		 15602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1561
1562 * aarch64-dis-2.c: Regenerate.
1563 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1564 (OP_SVE_BBB): New variant set.
1565 (OP_SVE_DDDD): New variant set.
1566 (OP_SVE_HHH): New variant set.
1567 (OP_SVE_HHHU): New variant set.
1568 (OP_SVE_SSS): New variant set.
1569 (OP_SVE_SSSU): New variant set.
1570 (OP_SVE_SHH): New variant set.
1571 (OP_SVE_SBBU): New variant set.
1572 (OP_SVE_DSS): New variant set.
1573 (OP_SVE_DHHU): New variant set.
1574 (OP_SVE_VMV_HSD_BHS): New variant set.
1575 (OP_SVE_VVU_HSD_BHS): New variant set.
1576 (OP_SVE_VVVU_SD_BH): New variant set.
1577 (OP_SVE_VVVU_BHSD): New variant set.
1578 (OP_SVE_VVV_QHD_DBS): New variant set.
1579 (OP_SVE_VVV_HSD_BHS): New variant set.
1580 (OP_SVE_VVV_HSD_BHS2): New variant set.
1581 (OP_SVE_VVV_BHS_HSD): New variant set.
1582 (OP_SVE_VV_BHS_HSD): New variant set.
1583 (OP_SVE_VVV_SD): New variant set.
1584 (OP_SVE_VVU_BHS_HSD): New variant set.
1585 (OP_SVE_VZVV_SD): New variant set.
1586 (OP_SVE_VZVV_BH): New variant set.
1587 (OP_SVE_VZV_SD): New variant set.
1588 (aarch64_opcode_table): Add sve2 instructions.
1589
28ed815a
MM		 15902019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1591
1592 * aarch64-asm-2.c: Regenerated.
1593 * aarch64-dis-2.c: Regenerated.
1594 * aarch64-opc-2.c: Regenerated.
1595 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1596 for SVE_SHLIMM_UNPRED_22.
1597 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1598 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1599 operand.
1600
fd1dc4a0
MM		 16012019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1602
1603 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1604 sve_size_tsz_bhs iclass encode.
1605 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1606 sve_size_tsz_bhs iclass decode.
1607
31e36ab3
MM		 16082019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1609
1610 * aarch64-asm-2.c: Regenerated.
1611 * aarch64-dis-2.c: Regenerated.
1612 * aarch64-opc-2.c: Regenerated.
1613 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1614 for SVE_Zm4_11_INDEX.
1615 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1616 (fields): Handle SVE_i2h field.
1617 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1618 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1619
1be5f94f
MM		 16202019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1621
1622 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1623 sve_shift_tsz_bhsd iclass encode.
1624 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1625 sve_shift_tsz_bhsd iclass decode.
1626
3c17238b
MM		 16272019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1628
1629 * aarch64-asm-2.c: Regenerated.
1630 * aarch64-dis-2.c: Regenerated.
1631 * aarch64-opc-2.c: Regenerated.
1632 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1633 (aarch64_encode_variant_using_iclass): Handle
1634 sve_shift_tsz_hsd iclass encode.
1635 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1636 sve_shift_tsz_hsd iclass decode.
1637 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1638 for SVE_SHRIMM_UNPRED_22.
1639 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1640 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1641 operand.
1642
cd50a87a
MM		 16432019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1644
1645 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1646 sve_size_013 iclass encode.
1647 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1648 sve_size_013 iclass decode.
1649
3c705960
MM		 16502019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1651
1652 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1653 sve_size_bh iclass encode.
1654 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1655 sve_size_bh iclass decode.
1656
0a57e14f
MM		 16572019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1658
1659 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1660 sve_size_sd2 iclass encode.
1661 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1662 sve_size_sd2 iclass decode.
1663 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1664 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1665
c469c864
MM		 16662019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1667
1668 * aarch64-asm-2.c: Regenerated.
1669 * aarch64-dis-2.c: Regenerated.
1670 * aarch64-opc-2.c: Regenerated.
1671 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1672 for SVE_ADDR_ZX.
1673 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1674 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1675
116adc27
MM		 16762019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1677
1678 * aarch64-asm-2.c: Regenerated.
1679 * aarch64-dis-2.c: Regenerated.
1680 * aarch64-opc-2.c: Regenerated.
1681 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1682 for SVE_Zm3_11_INDEX.
1683 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1684 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1685 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1686 fields.
1687 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1688
3bd82c86
MM		 16892019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1690
1691 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1692 sve_size_hsd2 iclass encode.
1693 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1694 sve_size_hsd2 iclass decode.
1695 * aarch64-opc.c (fields): Handle SVE_size field.
1696 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1697
adccc507
MM		 16982019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1699
1700 * aarch64-asm-2.c: Regenerated.
1701 * aarch64-dis-2.c: Regenerated.
1702 * aarch64-opc-2.c: Regenerated.
1703 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1704 for SVE_IMM_ROT3.
1705 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1706 (fields): Handle SVE_rot3 field.
1707 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1708 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1709
5cd99750
MM		 17102019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1711
1712 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1713 instructions.
1714
7ce2460a
MM		 17152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1716
1717 * aarch64-tbl.h
1718 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1719 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1720 aarch64_feature_sve2bitperm): New feature sets.
1721 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1722 for feature set addresses.
1723 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1724 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1725
41cee089
FS		 17262019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1727 Faraz Shahbazker <fshahbazker@wavecomp.com>
1728
1729 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1730 argument and set ASE_EVA_R6 appropriately.
1731 (set_default_mips_dis_options): Pass ISA to above.
1732 (parse_mips_dis_option): Likewise.
1733 * mips-opc.c (EVAR6): New macro.
1734 (mips_builtin_opcodes): Add llwpe, scwpe.
1735
b83b4b13
SD		 17362019-05-01 Sudakshina Das <sudi.das@arm.com>
1737
1738 * aarch64-asm-2.c: Regenerated.
1739 * aarch64-dis-2.c: Regenerated.
1740 * aarch64-opc-2.c: Regenerated.
1741 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1742 AARCH64_OPND_TME_UIMM16.
1743 (aarch64_print_operand): Likewise.
1744 * aarch64-tbl.h (QL_IMM_NIL): New.
1745 (TME): New.
1746 (_TME_INSN): New.
1747 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1748
4a90ce95
JD		 17492019-04-29 John Darrington <john@darrington.wattle.id.au>
1750
1751 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1752
a45328b9
AB		 17532019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1754 Faraz Shahbazker <fshahbazker@wavecomp.com>
1755
1756 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1757
d10be0cb
JD		 17582019-04-24 John Darrington <john@darrington.wattle.id.au>
1759
1760 * s12z-opc.h: Add extern "C" bracketing to help
1761 users who wish to use this interface in c++ code.
1762
a679f24e
JD		 17632019-04-24 John Darrington <john@darrington.wattle.id.au>
1764
1765 * s12z-opc.c (bm_decode): Handle bit map operations with the
1766 "reserved0" mode.
1767
32c36c3c
AV		 17682019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1769
1770 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1771 specifier. Add entries for VLDR and VSTR of system registers.
1772 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1773 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1774 of %J and %K format specifier.
1775
efd6b359
AV		 17762019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1777
1778 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1779 Add new entries for VSCCLRM instruction.
1780 (print_insn_coprocessor): Handle new %C format control code.
1781
6b0dd094
AV		 17822019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1783
1784 * arm-dis.c (enum isa): New enum.
1785 (struct sopcode32): New structure.
1786 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1787 set isa field of all current entries to ANY.
1788 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1789 Only match an entry if its isa field allows the current mode.
1790
4b5a202f
AV		 17912019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1792
1793 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1794 CLRM.
1795 (print_insn_thumb32): Add logic to print %n CLRM register list.
1796
60f993ce
AV		 17972019-04-15 Sudakshina Das <sudi.das@arm.com>
1798
1799 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1800 and %Q patterns.
1801
f6b2b12d
AV		 18022019-04-15 Sudakshina Das <sudi.das@arm.com>
1803
1804 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1805 (print_insn_thumb32): Edit the switch case for %Z.
1806
1889da70
AV		 18072019-04-15 Sudakshina Das <sudi.das@arm.com>
1808
1809 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1810
65d1bc05
AV		 18112019-04-15 Sudakshina Das <sudi.das@arm.com>
1812
1813 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1814
1caf72a5
AV		 18152019-04-15 Sudakshina Das <sudi.das@arm.com>
1816
1817 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1818
f1c7f421
AV		 18192019-04-15 Sudakshina Das <sudi.das@arm.com>
1820
1821 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1822 Arm register with r13 and r15 unpredictable.
1823 (thumb32_opcodes): New instructions for bfx and bflx.
1824
4389b29a
AV		 18252019-04-15 Sudakshina Das <sudi.das@arm.com>
1826
1827 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1828
e5d6e09e
AV		 18292019-04-15 Sudakshina Das <sudi.das@arm.com>
1830
1831 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1832
e12437dc
AV		 18332019-04-15 Sudakshina Das <sudi.das@arm.com>
1834
1835 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1836
031254f2
AV		 18372019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1838
1839 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1840
e5a557ac
JD		 18412019-04-12 John Darrington <john@darrington.wattle.id.au>
1842
1843 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1844 "optr". ("operator" is a reserved word in c++).
1845
bd7ceb8d
SD		 18462019-04-11 Sudakshina Das <sudi.das@arm.com>
1847
1848 * aarch64-opc.c (aarch64_print_operand): Add case for
1849 AARCH64_OPND_Rt_SP.
1850 (verify_constraints): Likewise.
1851 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1852 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1853 to accept Rt|SP as first operand.
1854 (AARCH64_OPERANDS): Add new Rt_SP.
1855 * aarch64-asm-2.c: Regenerated.
1856 * aarch64-dis-2.c: Regenerated.
1857 * aarch64-opc-2.c: Regenerated.
1858
e54010f1
SD		 18592019-04-11 Sudakshina Das <sudi.das@arm.com>
1860
1861 * aarch64-asm-2.c: Regenerated.
1862 * aarch64-dis-2.c: Likewise.
1863 * aarch64-opc-2.c: Likewise.
1864 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1865
7e96e219
RS		 18662019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1867
1868 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1869
6f2791d5
L		 18702019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1871
1872 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1873 * i386-init.h: Regenerated.
1874
e392bad3
AM		 18752019-04-07 Alan Modra <amodra@gmail.com>
1876
1877 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1878 op_separator to control printing of spaces, comma and parens
1879 rather than need_comma, need_paren and spaces vars.
1880
dffaa15c
AM		 18812019-04-07 Alan Modra <amodra@gmail.com>
1882
1883 PR 24421
1884 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1885 (print_insn_neon, print_insn_arm): Likewise.
1886
d6aab7a1
XG		 18872019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1888
1889 * i386-dis-evex.h (evex_table): Updated to support BF16
1890 instructions.
1891 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1892 and EVEX_W_0F3872_P_3.
1893 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1894 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1895 * i386-opc.h (enum): Add CpuAVX512_BF16.
1896 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1897 * i386-opc.tbl: Add AVX512 BF16 instructions.
1898 * i386-init.h: Regenerated.
1899 * i386-tbl.h: Likewise.
1900
66e85460
AM		 19012019-04-05 Alan Modra <amodra@gmail.com>
1902
1903 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1904 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1905 to favour printing of "-" branch hint when using the "y" bit.
1906 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1907
c2b1c275
AM		 19082019-04-05 Alan Modra <amodra@gmail.com>
1909
1910 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1911 opcode until first operand is output.
1912
aae9718e
PB		 19132019-04-04 Peter Bergner <bergner@linux.ibm.com>
1914
1915 PR gas/24349
1916 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1917 (valid_bo_post_v2): Add support for 'at' branch hints.
1918 (insert_bo): Only error on branch on ctr.
1919 (get_bo_hint_mask): New function.
1920 (insert_boe): Add new 'branch_taken' formal argument. Add support
1921 for inserting 'at' branch hints.
1922 (extract_boe): Add new 'branch_taken' formal argument. Add support
1923 for extracting 'at' branch hints.
1924 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1925 (BOE): Delete operand.
1926 (BOM, BOP): New operands.
1927 (RM): Update value.
1928 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1929 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1930 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1931 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1932 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1933 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1934 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1935 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1936 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1937 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1938 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1939 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1940 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1941 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1942 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1943 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1944 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1945 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1946 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1947 bttarl+>: New extended mnemonics.
1948
96a86c01
AM		 19492019-03-28 Alan Modra <amodra@gmail.com>
1950
1951 PR 24390
1952 * ppc-opc.c (BTF): Define.
1953 (powerpc_opcodes): Use for mtfsb*.
1954 * ppc-dis.c (print_insn_powerpc): Print fields with both
1955 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1956
796d6298
TC		 19572019-03-25 Tamar Christina <tamar.christina@arm.com>
1958
1959 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1960 (mapping_symbol_for_insn): Implement new algorithm.
1961 (print_insn): Remove duplicate code.
1962
60df3720
TC		 19632019-03-25 Tamar Christina <tamar.christina@arm.com>
1964
1965 * aarch64-dis.c (print_insn_aarch64):
1966 Implement override.
1967
51457761
TC		 19682019-03-25 Tamar Christina <tamar.christina@arm.com>
1969
1970 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1971 order.
1972
53b2f36b
TC		 19732019-03-25 Tamar Christina <tamar.christina@arm.com>
1974
1975 * aarch64-dis.c (last_stop_offset): New.
1976 (print_insn_aarch64): Use stop_offset.
1977
89199bb5
L		 19782019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1979
1980 PR gas/24359
1981 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1982 CPU_ANY_AVX2_FLAGS.
1983 * i386-init.h: Regenerated.
1984
97ed31ae
L		 19852019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1986
1987 PR gas/24348
1988 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1989 vmovdqu16, vmovdqu32 and vmovdqu64.
1990 * i386-tbl.h: Regenerated.
1991
0919bfe9
AK		 19922019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1993
1994 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1995 from vstrszb, vstrszh, and vstrszf.
1996
19972019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1998
1999 * s390-opc.txt: Add instruction descriptions.
2000
21820ebe
JW		 20012019-02-08 Jim Wilson <jimw@sifive.com>
2002
2003 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2004 <bne>: Likewise.
2005
f7dd2fb2
TC		 20062019-02-07 Tamar Christina <tamar.christina@arm.com>
2007
2008 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2009
6456d318
TC		 20102019-02-07 Tamar Christina <tamar.christina@arm.com>
2011
2012 PR binutils/23212
2013 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2014 * aarch64-opc.c (verify_elem_sd): New.
2015 (fields): Add FLD_sz entr.
2016 * aarch64-tbl.h (_SIMD_INSN): New.
2017 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2018 fmulx scalar and vector by element isns.
2019
4a83b610
NC		 20202019-02-07 Nick Clifton <nickc@redhat.com>
2021
2022 * po/sv.po: Updated Swedish translation.
2023
fc60b8c8
AK		 20242019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2025
2026 * s390-mkopc.c (main): Accept arch13 as cpu string.
2027 * s390-opc.c: Add new instruction formats and instruction opcode
2028 masks.
2029 * s390-opc.txt: Add new arch13 instructions.
2030
e10620d3
TC		 20312019-01-25 Sudakshina Das <sudi.das@arm.com>
2032
2033 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2034 (aarch64_opcode): Change encoding for stg, stzg
2035 st2g and st2zg.
2036 * aarch64-asm-2.c: Regenerated.
2037 * aarch64-dis-2.c: Regenerated.
2038 * aarch64-opc-2.c: Regenerated.
2039
20a4ca55
SD		 20402019-01-25 Sudakshina Das <sudi.das@arm.com>
2041
2042 * aarch64-asm-2.c: Regenerated.
2043 * aarch64-dis-2.c: Likewise.
2044 * aarch64-opc-2.c: Likewise.
2045 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2046
550fd7bf
SD		 20472019-01-25 Sudakshina Das <sudi.das@arm.com>
2048 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2049
2050 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2051 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2052 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2053 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2054 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2055 case for ldstgv_indexed.
2056 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2057 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2058 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2059 * aarch64-asm-2.c: Regenerated.
2060 * aarch64-dis-2.c: Regenerated.
2061 * aarch64-opc-2.c: Regenerated.
2062
d9938630
NC		 20632019-01-23 Nick Clifton <nickc@redhat.com>
2064
2065 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2066
375cd423
NC		 20672019-01-21 Nick Clifton <nickc@redhat.com>
2068
2069 * po/de.po: Updated German translation.
2070 * po/uk.po: Updated Ukranian translation.
2071
57299f48
CX		 20722019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2073 * mips-dis.c (mips_arch_choices): Fix typo in
2074 gs464, gs464e and gs264e descriptors.
2075
f48dfe41
NC		 20762019-01-19 Nick Clifton <nickc@redhat.com>
2077
2078 * configure: Regenerate.
2079 * po/opcodes.pot: Regenerate.
2080
f974f26c
NC		 20812018-06-24 Nick Clifton <nickc@redhat.com>
2082
2083 2.32 branch created.
2084
39f286cd
JD		 20852019-01-09 John Darrington <john@darrington.wattle.id.au>
2086
448b8ca8
JD		 2087 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2088 if it is null.
2089 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2090 zero.
2091
3107326d
AP		 20922019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2093
2094 * configure: Regenerate.
2095
7e9ca91e
AM		 20962019-01-07 Alan Modra <amodra@gmail.com>
2097
2098 * configure: Regenerate.
2099 * po/POTFILES.in: Regenerate.
2100
ef1ad42b
JD		 21012019-01-03 John Darrington <john@darrington.wattle.id.au>
2102
2103 * s12z-opc.c: New file.
2104 * s12z-opc.h: New file.
2105 * s12z-dis.c: Removed all code not directly related to display
2106 of instructions. Used the interface provided by the new files
2107 instead.
2108 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2109 * Makefile.in: Regenerate.
ef1ad42b 2110 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2111 * configure: Regenerate.
ef1ad42b 2112
82704155
AM		 21132019-01-01 Alan Modra <amodra@gmail.com>
2114
2115 Update year range in copyright notice of all files.
2116
d5c04e1b 2117For older changes see ChangeLog-2018
3499769a 2118\f
d5c04e1b 2119Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2120
2121Copying and distribution of this file, with or without modification,
2122are permitted in any medium without royalty provided the copyright
2123notice and this notice are preserved.
2124
2125Local Variables:
2126mode: change-log
2127left-margin: 8
2128fill-column: 74
2129version-control: never
2130End:
GDB Binutils - Deliverables
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