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PR7044
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
8e79c3df
CM		 12008-11-18 Catherine Moore <clm@codesourcery.com>
2
3 * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt
4 instructions.
5 (neon_opcodes): Likewise.
6 (print_insn_coprocessor): Print 't' or 'b' for vcvt
7 instructions.
8
d387240a
TG		 92008-11-14 Tristan Gingold <gingold@adacore.com>
10
11 * makefile.vms (OBJS): Update list of objects.
12 (DEFS): Update
13 (CFLAGS): Update.
14
4dc48ef6
CF		 152008-11-06 Chao-ying Fu <fu@mips.com>
16
17 * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these
18 before sync.
19 (sync): New instruction with 5-bit sync type.
20 * mips-dis.c (print_insn_args: Add case '1' to print 5-bit values.
21
c8941035
NC		 222008-11-06 Nick Clifton <nickc@redhat.com>
23
24 * avr-dis.c: Replace uses of sprintf without a format string with
25 calls to strcpy.
26
a7bea99d
L		 272008-11-03 H.J. Lu <hongjiu.lu@intel.com>
28
29 * i386-opc.tbl: Add cmovpe and cmovpo.
30 * i386-tbl.h: Regenerated.
31
4267b19f
NC		 322008-10-22 Nick Clifton <nickc@redhat.com>
33
34 PR 6937
35 * configure.in (SHARED_LIBADD): Revert previous change.
36 Add a comment explaining why.
37 (SHARED_DEPENDENCIES): Revert previous change.
38 * configure: Regenerate.
39
8a9629d0
NC		 402008-10-10 Nick Clifton <nickc@redhat.com>
41
42 PR 6937
43 * configure.in (SHARED_LIBADD): Add libiberty.a.
44 (SHARED_DEPENDENCIES): Add libiberty.a.
45
c587b3f9
L		 462008-09-30 H.J. Lu <hongjiu.lu@intel.com>
47
48 * i386-gen.c: Include "hashtab.h".
49 (next_field): Take a new argument, last. Check last.
50 (process_i386_cpu_flag): Updated.
51 (process_i386_opcode_modifier): Likewise.
52 (process_i386_operand_type): Likewise.
53 (process_i386_registers): Likewise.
54 (output_i386_opcode): New.
55 (opcode_hash_entry): Likewise.
56 (opcode_hash_table): Likewise.
57 (opcode_hash_hash): Likewise.
58 (opcode_hash_eq): Likewise.
59 (process_i386_opcodes): Use opcode hash table and opcode array.
60
34b23dab
AK		 612008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
62
63 * s390-opc.txt (stdy, stey): Fix description
64
782e11fd
AM		 652008-09-30 Alan Modra <amodra@bigpond.net.au>
66
67 * Makefile.am: Run "make dep-am".
68 * Makefile.in: Regenerate.
69
1927a18f
L		 702008-09-29 H.J. Lu <hongjiu.lu@intel.com>
71
72 * aclocal.m4: Regenerated.
73 * configure: Likewise.
74 * Makefile.in: Likewise.
75
afac680a
NC		 762008-09-29 Nick Clifton <nickc@redhat.com>
77
78 * po/vi.po: Updated Vietnamese translation.
79 * po/fr.po: Updated French translation.
80
b40d5eb9
AK		 812008-09-26 Florian Krohm <fkrohm@us.ibm.com>
82
83 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
84 (cfxr, cfdr, cfer, clclu): Add esa flag.
85 (sqd): Instruction added.
86 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
87 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
88
d0411736
AM		 892008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
90
91 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
92 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
93
3e126784
L		 942008-09-11 H.J. Lu <hongjiu.lu@intel.com>
95
96 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
97 * i386-tbl.h: Regenerated.
98
ddab3d59
JB		 992008-08-28 Jan Beulich <jbeulich@novell.com>
100
101 * i386-dis.c (dis386): Adjust far return mnemonics.
102 * i386-opc.tbl: Add retf.
103 * i386-tbl.h: Re-generate.
104
b19d5385
JB		 1052008-08-28 Jan Beulich <jbeulich@novell.com>
106
107 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
108
1ca35711
L		 1092008-08-28 H.J. Lu <hongjiu.lu@intel.com>
110
111 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
112 * ia64-gen.c (lookup_specifier): Likewise.
113
114 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
115 * ia64-raw.tbl: Likewise.
116 * ia64-waw.tbl: Likewise.
117 * ia64-asmtab.c: Regenerated.
118
515c56e7
L		 1192008-08-27 H.J. Lu <hongjiu.lu@intel.com>
120
121 * i386-opc.tbl: Correct fidivr operand size.
122
123 * i386-tbl.h: Regenerated.
124
da594c4a
AM		 1252008-08-24 Alan Modra <amodra@bigpond.net.au>
126
127 * configure.in: Update a number of obsolete autoconf macros.
128 * aclocal.m4: Regenerate.
129
a5ff0eb2
L		 1302008-08-20 H.J. Lu <hongjiu.lu@intel.com>
131
132 AVX Programming Reference (August, 2008)
133 * i386-dis.c (PREFIX_VEX_38DB): New.
134 (PREFIX_VEX_38DC): Likewise.
135 (PREFIX_VEX_38DD): Likewise.
136 (PREFIX_VEX_38DE): Likewise.
137 (PREFIX_VEX_38DF): Likewise.
138 (PREFIX_VEX_3ADF): Likewise.
139 (VEX_LEN_38DB_P_2): Likewise.
140 (VEX_LEN_38DC_P_2): Likewise.
141 (VEX_LEN_38DD_P_2): Likewise.
142 (VEX_LEN_38DE_P_2): Likewise.
143 (VEX_LEN_38DF_P_2): Likewise.
144 (VEX_LEN_3ADF_P_2): Likewise.
145 (PREFIX_VEX_3A04): Updated.
146 (VEX_LEN_3A06_P_2): Likewise.
147 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
148 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
149 (x86_64_table): Likewise.
150 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
151 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
152 VEX_LEN_3ADF_P_2.
153
154 * i386-opc.tbl: Add AES + AVX instructions.
155 * i386-init.h: Regenerated.
156 * i386-tbl.h: Likewise.
157
7dc6076f
AK		 1582008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
159
160 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
161 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
162
7357c5b6
AM		 1632008-08-15 Alan Modra <amodra@bigpond.net.au>
164
165 PR 6526
166 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
167 * Makefile.in: Regenerate.
168 * aclocal.m4: Regenerate.
169 * config.in: Regenerate.
170 * configure: Regenerate.
171
899d85be
AM		 1722008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
173
174 PR 6825
175 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
176
dfb07592
L		 1772008-08-12 H.J. Lu <hongjiu.lu@intel.com>
178
179 * i386-opc.tbl: Add syscall and sysret for Cpu64.
180
181 * i386-tbl.h: Regenerated.
182
323ee3f4
AM		 1832008-08-04 Alan Modra <amodra@bigpond.net.au>
184
185 * Makefile.am (POTFILES.in): Set LC_ALL=C.
186 * Makefile.in: Regenerate.
187 * po/POTFILES.in: Regenerate.
188
9b4e5766
PB		 1892008-08-01 Peter Bergner <bergner@vnet.ibm.com>
190
191 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
192 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
193 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
194 * ppc-opc.c (insert_xt6): New static function.
195 (extract_xt6): Likewise.
196 (insert_xa6): Likewise.
197 (extract_xa6: Likewise.
198 (insert_xb6): Likewise.
199 (extract_xb6): Likewise.
200 (insert_xb6s): Likewise.
201 (extract_xb6s): Likewise.
202 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
203 XX3DM_MASK, PPCVSX): New.
204 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
205 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
206
20fd6e2e
PA		 2072008-08-01 Pedro Alves <pedro@codesourcery.com>
208
209 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
210 * Makefile.in: Regenerate.
211
a656ed5b
L		 2122008-08-01 H.J. Lu <hongjiu.lu@intel.com>
213
214 * i386-reg.tbl: Use Dw2Inval on AVX registers.
215 * i386-tbl.h: Regenerated.
216
081ba1b3
AM		 2172008-07-30 Michael J. Eager <eager@eagercon.com>
218
219 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
220 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
221 (insert_sprg, PPC405): Use PPC_OPCODE_405.
222 (powerpc_opcodes): Add Xilinx APU related opcodes.
223
0af1713e
AM		 2242008-07-30 Alan Modra <amodra@bigpond.net.au>
225
226 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
227
30c09090
RS		 2282008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
229
230 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
231
c27e721e
AN		 2322008-07-07 Adam Nemet <anemet@caviumnetworks.com>
233
234 * mips-opc.c (CP): New macro.
235 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
236 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
237 dmtc2 Octeon instructions.
238
bd2e2557
SS		 2392008-07-07 Stan Shebs <stan@codesourcery.com>
240
241 * dis-init.c (init_disassemble_info): Init endian_code field.
242 * arm-dis.c (print_insn): Disassemble code according to
243 setting of endian_code.
244 (print_insn_big_arm): Detect when BE8 extension flag has been set.
245
6ba2a415
RS		 2462008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
247
248 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
249 for ELF symbols.
250
c8187e15
PB		 2512008-06-25 Peter Bergner <bergner@vnet.ibm.com>
252
253 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
254 (print_ppc_disassembler_options): Likewise.
255 * ppc-opc.c (PPC464): Define.
256 (powerpc_opcodes): Add mfdcrux and mtdcrux.
257
7a283e07
RW		 2582008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
259
260 * configure: Regenerate.
261
fa452fa6
PB		 2622008-06-13 Peter Bergner <bergner@vnet.ibm.com>
263
264 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
265 ppc_cpu_t typedef.
266 (struct dis_private): New.
267 (POWERPC_DIALECT): New define.
268 (powerpc_dialect): Renamed to...
269 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
270 struct dis_private.
271 (print_insn_big_powerpc): Update for using structure in
272 info->private_data.
273 (print_insn_little_powerpc): Likewise.
274 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
275 (skip_optional_operands): Likewise.
276 (print_insn_powerpc): Likewise. Remove initialization of dialect.
277 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
278 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
279 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
280 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
281 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
282 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
283 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
284 param to be of type ppc_cpu_t. Update prototype.
285
bb35fb24
NC		 2862008-06-12 Adam Nemet <anemet@caviumnetworks.com>
287
288 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
289 +s, +S.
290 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
291 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
292 syncw, syncws, vm3mulu, vm0 and vmulu.
293
dd3cbb7e
NC		 294 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
295 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
296 seqi, sne and snei.
297
a5dabbb0
L		 2982008-05-30 H.J. Lu <hongjiu.lu@intel.com>
299
300 * i386-opc.tbl: Add vmovd with 64bit operand.
301 * i386-tbl.h: Regenerated.
302
725a9891
MS		 3032008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
304
305 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
306
cbc80391
L		 3072008-05-22 H.J. Lu <hongjiu.lu@intel.com>
308
309 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
310 * i386-tbl.h: Regenerated.
311
116615c5
L		 3122008-05-22 H.J. Lu <hongjiu.lu@intel.com>
313
314 PR gas/6517
315 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
316 into 32bit and 64bit. Remove Reg64|Qword and add
317 IgnoreSize|No_qSuf on 32bit version.
318 * i386-tbl.h: Regenerated.
319
d9479f2d
L		 3202008-05-21 H.J. Lu <hongjiu.lu@intel.com>
321
322 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
323 * i386-tbl.h: Regenerated.
324
3ce6fddb
NC		 3252008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
326
327 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
328
8944f3c2
AM		 3292008-05-14 Alan Modra <amodra@bigpond.net.au>
330
331 * Makefile.am: Run "make dep-am".
332 * Makefile.in: Regenerate.
333
f1f8f695
L		 3342008-05-02 H.J. Lu <hongjiu.lu@intel.com>
335
336 * i386-dis.c (MOVBE_Fixup): New.
337 (Mo): Likewise.
338 (PREFIX_0F3880): Likewise.
339 (PREFIX_0F3881): Likewise.
340 (PREFIX_0F38F0): Updated.
341 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
342 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
343 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
344
345 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
346 CPU_EPT_FLAGS.
347 (cpu_flags): Add CpuMovbe and CpuEPT.
348
349 * i386-opc.h (CpuMovbe): New.
350 (CpuEPT): Likewise.
351 (CpuLM): Updated.
352 (i386_cpu_flags): Add cpumovbe and cpuept.
353
354 * i386-opc.tbl: Add entries for movbe and EPT instructions.
355 * i386-init.h: Regenerated.
356 * i386-tbl.h: Likewise.
357
89aa3097
AN		 3582008-04-29 Adam Nemet <anemet@caviumnetworks.com>
359
360 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
361 the two drem and the two dremu macros.
362
39c5c168
AN		 3632008-04-28 Adam Nemet <anemet@caviumnetworks.com>
364
365 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
366 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
367 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
368 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
369
f04d18b7
DM		 3702008-04-25 David S. Miller <davem@davemloft.net>
371
372 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
373 instead of %sys_tick_cmpr, as suggested in architecture manuals.
374
6194aaab
L		 3752008-04-23 Paolo Bonzini <bonzini@gnu.org>
376
377 * aclocal.m4: Regenerate.
378 * configure: Regenerate.
379
1a6b486f
DM		 3802008-04-23 David S. Miller <davem@davemloft.net>
381
382 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
383 extended values.
384 (prefetch_table): Add missing values.
385
81f8a913
L		 3862008-04-22 H.J. Lu <hongjiu.lu@intel.com>
387
388 * i386-gen.c (opcode_modifiers): Add NoAVX.
389
390 * i386-opc.h (NoAVX): New.
391 (OldGcc): Updated.
392 (i386_opcode_modifier): Add noavx.
393
394 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
395 instructions which don't have AVX equivalent.
396 * i386-tbl.h: Regenerated.
397
dae39acc
L		 3982008-04-18 H.J. Lu <hongjiu.lu@intel.com>
399
400 * i386-dis.c (OP_VEX_FMA): New.
401 (OP_EX_VexImmW): Likewise.
402 (VexFMA): Likewise.
403 (Vex128FMA): Likewise.
404 (EXVexImmW): Likewise.
405 (get_vex_imm8): Likewise.
406 (OP_EX_VexReg): Likewise.
407 (vex_i4_done): Renamed to ...
408 (vex_w_done): This.
409 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
410 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
411 FMA instructions.
412 (print_insn): Updated.
413 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
414 (OP_REG_VexI4): Check invalid high registers.
415
ce886ab1
DR		 4162008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
417 Michael Meissner <michael.meissner@amd.com>
418
419 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
420 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 421
19a6653c
AM		 4222008-04-14 Edmar Wienskoski <edmar@freescale.com>
423
424 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
425 accept Power E500MC instructions.
426 (print_ppc_disassembler_options): Document -Me500mc.
427 * ppc-opc.c (DUIS, DUI, T): New.
428 (XRT, XRTRA): Likewise.
429 (E500MC): Likewise.
430 (powerpc_opcodes): Add new Power E500MC instructions.
431
112b7c50
AK		 4322008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
433
434 * s390-dis.c (init_disasm): Evaluate disassembler_options.
435 (print_s390_disassembler_options): New function.
436 * disassemble.c (disassembler_usage): Invoke
437 print_s390_disassembler_options.
438
7ff42648
AK		 4392008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
440
441 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
442 of local variables used for mnemonic parsing: prefix, suffix and
443 number.
444
45a5551e
AK		 4452008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
446
447 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
448 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
449 (s390_crb_extensions): New extensions table.
450 (insertExpandedMnemonic): Handle '$' tag.
451 * s390-opc.txt: Remove conditional jump variants which can now
452 be expanded automatically.
453 Replace '*' tag with '$' in the compare and branch instructions.
454
06c8514a
L		 4552008-04-07 H.J. Lu <hongjiu.lu@intel.com>
456
457 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
458 (PREFIX_VEX_3AXX): Likewis.
459
b122c285
L		 4602008-04-07 H.J. Lu <hongjiu.lu@intel.com>
461
462 * i386-opc.tbl: Remove 4 extra blank lines.
463
594ab6a3
L		 4642008-04-04 H.J. Lu <hongjiu.lu@intel.com>
465
466 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
467 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
468 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
469 * i386-opc.tbl: Likewise.
470
471 * i386-opc.h (CpuCLMUL): Renamed to ...
472 (CpuPCLMUL): This.
473 (CpuFMA): Updated.
474 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
475
476 * i386-init.h: Regenerated.
477
c0f3af97
L		 4782008-04-03 H.J. Lu <hongjiu.lu@intel.com>
479
480 * i386-dis.c (OP_E_register): New.
481 (OP_E_memory): Likewise.
482 (OP_VEX): Likewise.
483 (OP_EX_Vex): Likewise.
484 (OP_EX_VexW): Likewise.
485 (OP_XMM_Vex): Likewise.
486 (OP_XMM_VexW): Likewise.
487 (OP_REG_VexI4): Likewise.
488 (PCLMUL_Fixup): Likewise.
489 (VEXI4_Fixup): Likewise.
490 (VZERO_Fixup): Likewise.
491 (VCMP_Fixup): Likewise.
492 (VPERMIL2_Fixup): Likewise.
493 (rex_original): Likewise.
494 (rex_ignored): Likewise.
495 (Mxmm): Likewise.
496 (XMM): Likewise.
497 (EXxmm): Likewise.
498 (EXxmmq): Likewise.
499 (EXymmq): Likewise.
500 (Vex): Likewise.
501 (Vex128): Likewise.
502 (Vex256): Likewise.
503 (VexI4): Likewise.
504 (EXdVex): Likewise.
505 (EXqVex): Likewise.
506 (EXVexW): Likewise.
507 (EXdVexW): Likewise.
508 (EXqVexW): Likewise.
509 (XMVex): Likewise.
510 (XMVexW): Likewise.
511 (XMVexI4): Likewise.
512 (PCLMUL): Likewise.
513 (VZERO): Likewise.
514 (VCMP): Likewise.
515 (VPERMIL2): Likewise.
516 (xmm_mode): Likewise.
517 (xmmq_mode): Likewise.
518 (ymmq_mode): Likewise.
519 (vex_mode): Likewise.
520 (vex128_mode): Likewise.
521 (vex256_mode): Likewise.
522 (USE_VEX_C4_TABLE): Likewise.
523 (USE_VEX_C5_TABLE): Likewise.
524 (USE_VEX_LEN_TABLE): Likewise.
525 (VEX_C4_TABLE): Likewise.
526 (VEX_C5_TABLE): Likewise.
527 (VEX_LEN_TABLE): Likewise.
528 (REG_VEX_XX): Likewise.
529 (MOD_VEX_XXX): Likewise.
530 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
531 (PREFIX_0F3A44): Likewise.
532 (PREFIX_0F3ADF): Likewise.
533 (PREFIX_VEX_XXX): Likewise.
534 (VEX_OF): Likewise.
535 (VEX_OF38): Likewise.
536 (VEX_OF3A): Likewise.
537 (VEX_LEN_XXX): Likewise.
538 (vex): Likewise.
539 (need_vex): Likewise.
540 (need_vex_reg): Likewise.
541 (vex_i4_done): Likewise.
542 (vex_table): Likewise.
543 (vex_len_table): Likewise.
544 (OP_REG_VexI4): Likewise.
545 (vex_cmp_op): Likewise.
546 (pclmul_op): Likewise.
547 (vpermil2_op): Likewise.
548 (m_mode): Updated.
549 (es_reg): Likewise.
550 (PREFIX_0F38F0): Likewise.
551 (PREFIX_0F3A60): Likewise.
552 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
553 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
554 and PREFIX_VEX_XXX entries.
555 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
556 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
557 PREFIX_0F3ADF.
558 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
559 Add MOD_VEX_XXX entries.
560 (ckprefix): Initialize rex_original and rex_ignored. Store the
561 REX byte in rex_original.
562 (get_valid_dis386): Handle the implicit prefix in VEX prefix
563 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
564 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
565 calling get_valid_dis386. Use rex_original and rex_ignored when
566 printing out REX.
567 (putop): Handle "XY".
568 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
569 ymmq_mode.
570 (OP_E_extended): Updated to use OP_E_register and
571 OP_E_memory.
572 (OP_XMM): Handle VEX.
573 (OP_EX): Likewise.
574 (XMM_Fixup): Likewise.
575 (CMP_Fixup): Use ARRAY_SIZE.
576
577 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
578 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
579 (operand_type_init): Add OPERAND_TYPE_REGYMM and
580 OPERAND_TYPE_VEX_IMM4.
581 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
582 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
583 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
584 VexImmExt and SSE2AVX.
585 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
586
587 * i386-opc.h (CpuAVX): New.
588 (CpuAES): Likewise.
589 (CpuCLMUL): Likewise.
590 (CpuFMA): Likewise.
591 (Vex): Likewise.
592 (Vex256): Likewise.
593 (VexNDS): Likewise.
594 (VexNDD): Likewise.
595 (VexW0): Likewise.
596 (VexW1): Likewise.
597 (Vex0F): Likewise.
598 (Vex0F38): Likewise.
599 (Vex0F3A): Likewise.
600 (Vex3Sources): Likewise.
601 (VexImmExt): Likewise.
602 (SSE2AVX): Likewise.
603 (RegYMM): Likewise.
604 (Ymmword): Likewise.
605 (Vex_Imm4): Likewise.
606 (Implicit1stXmm0): Likewise.
607 (CpuXsave): Updated.
608 (CpuLM): Likewise.
609 (ByteOkIntel): Likewise.
610 (OldGcc): Likewise.
611 (Control): Likewise.
612 (Unspecified): Likewise.
613 (OTMax): Likewise.
614 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
615 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
616 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
617 vex3sources, veximmext and sse2avx.
618 (i386_operand_type): Add regymm, ymmword and vex_imm4.
619
620 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
621
622 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
623
624 * i386-init.h: Regenerated.
625 * i386-tbl.h: Likewise.
626
b21c9cb4
BS		 6272008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
628
629 From Robin Getz <robin.getz@analog.com>
630 * bfin-dis.c (bu32): Typedef.
631 (enum const_forms_t): Add c_uimm32 and c_huimm32.
632 (constant_formats[]): Add uimm32 and huimm16.
633 (fmtconst_val): New.
634 (uimm32): Define.
635 (huimm32): Define.
636 (imm16_val): Define.
637 (luimm16_val): Define.
638 (struct saved_state): Define.
639 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
640 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
641 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
642 (get_allreg): New.
643 (decode_LDIMMhalf_0): Print out the whole register value.
644
ee171c8f
BS		 645 From Jie Zhang <jie.zhang@analog.com>
646 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
647 multiply and multiply-accumulate to data register instruction.
648
086134ec
BS		 649 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
650 c_imm32, c_huimm32e): Define.
651 (constant_formats): Add flags for printing decimal, leading spaces, and
652 exact symbols.
653 (comment, parallel): Add global flags in all disassembly.
654 (fmtconst): Take advantage of new flags, and print default in hex.
655 (fmtconst_val): Likewise.
656 (decode_macfunc): Be consistant with spaces, tabs, comments,
657 capitalization in disassembly, fix minor coding style issues.
658 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
659 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
660 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
661 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
662 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
663 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
664 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
665 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
666 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
667 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
668 _print_insn_bfin, print_insn_bfin): Likewise.
669
58c85be7
RW		 6702008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
671
672 * aclocal.m4: Regenerate.
673 * configure: Likewise.
674 * Makefile.in: Likewise.
675
50e7d84b
AM		 6762008-03-13 Alan Modra <amodra@bigpond.net.au>
677
678 * Makefile.am: Run "make dep-am".
679 * Makefile.in: Regenerate.
680 * configure: Regenerate.
681
de866fcc
AM		 6822008-03-07 Alan Modra <amodra@bigpond.net.au>
683
684 * ppc-opc.c (powerpc_opcodes): Order and format.
685
28dbc079
L		 6862008-03-01 H.J. Lu <hongjiu.lu@intel.com>
687
688 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
689 * i386-tbl.h: Regenerated.
690
849830bd
L		 6912008-02-23 H.J. Lu <hongjiu.lu@intel.com>
692
693 * i386-opc.tbl: Disallow 16-bit near indirect branches for
694 x86-64.
695 * i386-tbl.h: Regenerated.
696
743ddb6b
JB		 6972008-02-21 Jan Beulich <jbeulich@novell.com>
698
699 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
700 and Fword for far indirect jmp. Allow Reg16 and Word for near
701 indirect jmp on x86-64. Disallow Fword for lcall.
702 * i386-tbl.h: Re-generate.
703
796d5313
NC		 7042008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
705
706 * cr16-opc.c (cr16_num_optab): Defined
707
65da13b5
L		 7082008-02-16 H.J. Lu <hongjiu.lu@intel.com>
709
710 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
711 * i386-init.h: Regenerated.
712
0e336180
NC		 7132008-02-14 Nick Clifton <nickc@redhat.com>
714
715 PR binutils/5524
716 * configure.in (SHARED_LIBADD): Select the correct host specific
717 file extension for shared libraries.
718 * configure: Regenerate.
719
b7240065
JB		 7202008-02-13 Jan Beulich <jbeulich@novell.com>
721
722 * i386-opc.h (RegFlat): New.
723 * i386-reg.tbl (flat): Add.
724 * i386-tbl.h: Re-generate.
725
34b772a6
JB		 7262008-02-13 Jan Beulich <jbeulich@novell.com>
727
728 * i386-dis.c (a_mode): New.
729 (cond_jump_mode): Adjust.
730 (Ma): Change to a_mode.
731 (intel_operand_size): Handle a_mode.
732 * i386-opc.tbl: Allow Dword and Qword for bound.
733 * i386-tbl.h: Re-generate.
734
a60de03c
JB		 7352008-02-13 Jan Beulich <jbeulich@novell.com>
736
737 * i386-gen.c (process_i386_registers): Process new fields.
738 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
739 unsigned char. Add dw2_regnum and Dw2Inval.
740 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
741 register names.
742 * i386-tbl.h: Re-generate.
743
f03fe4c1
L		 7442008-02-11 H.J. Lu <hongjiu.lu@intel.com>
745
4b6bc8eb 746 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 747 * i386-init.h: Updated.
748
475a2301
L		 7492008-02-11 H.J. Lu <hongjiu.lu@intel.com>
750
751 * i386-gen.c (cpu_flags): Add CpuXsave.
752
753 * i386-opc.h (CpuXsave): New.
4b6bc8eb 754 (CpuLM): Updated.
475a2301
L		 755 (i386_cpu_flags): Add cpuxsave.
756
757 * i386-dis.c (MOD_0FAE_REG_4): New.
758 (RM_0F01_REG_2): Likewise.
759 (MOD_0FAE_REG_5): Updated.
760 (RM_0F01_REG_3): Likewise.
761 (reg_table): Use MOD_0FAE_REG_4.
762 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
763 for xrstor.
764 (rm_table): Add RM_0F01_REG_2.
765
766 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
767 * i386-init.h: Regenerated.
768 * i386-tbl.h: Likewise.
769
595785c6 7702008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 771
595785c6
JB		 772 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
773 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
774 * i386-tbl.h: Re-generate.
775
bb8541b9
L		 7762008-02-04 H.J. Lu <hongjiu.lu@intel.com>
777
778 PR 5715
779 * configure: Regenerated.
780
57b592a3
AN		 7812008-02-04 Adam Nemet <anemet@caviumnetworks.com>
782
783 * mips-dis.c: Update copyright.
784 (mips_arch_choices): Add Octeon.
785 * mips-opc.c: Update copyright.
786 (IOCT): New macro.
787 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
788
930bb4cf
AM		 7892008-01-29 Alan Modra <amodra@bigpond.net.au>
790
791 * ppc-opc.c: Support optional L form mtmsr.
792
82c18208
L		 7932008-01-24 H.J. Lu <hongjiu.lu@intel.com>
794
795 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
796
599121aa
L		 7972008-01-23 H.J. Lu <hongjiu.lu@intel.com>
798
799 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
800 * i386-init.h: Regenerated.
801
80098f51
TG		 8022008-01-23 Tristan Gingold <gingold@adacore.com>
803
804 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
805 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
806
115c7c25
L		 8072008-01-22 H.J. Lu <hongjiu.lu@intel.com>
808
809 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
810 (cpu_flags): Likewise.
811
812 * i386-opc.h (CpuMMX2): Removed.
813 (CpuSSE): Updated.
814
815 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
816 * i386-init.h: Regenerated.
817 * i386-tbl.h: Likewise.
818
6305a203
L		 8192008-01-22 H.J. Lu <hongjiu.lu@intel.com>
820
821 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
822 CPU_SMX_FLAGS.
823 * i386-init.h: Regenerated.
824
fd07a1c8
L		 8252008-01-15 H.J. Lu <hongjiu.lu@intel.com>
826
827 * i386-opc.tbl: Use Qword on movddup.
828 * i386-tbl.h: Regenerated.
829
321fd21e
L		 8302008-01-15 H.J. Lu <hongjiu.lu@intel.com>
831
832 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
833 * i386-tbl.h: Regenerated.
834
4ee52178
L		 8352008-01-15 H.J. Lu <hongjiu.lu@intel.com>
836
837 * i386-dis.c (Mx): New.
838 (PREFIX_0FC3): Likewise.
839 (PREFIX_0FC7_REG_6): Updated.
840 (dis386_twobyte): Use PREFIX_0FC3.
841 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
842 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
843 movntss.
844
5c07affc
L		 8452008-01-14 H.J. Lu <hongjiu.lu@intel.com>
846
847 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
848 (operand_types): Add Mem.
849
850 * i386-opc.h (IntelSyntax): New.
851 * i386-opc.h (Mem): New.
852 (Byte): Updated.
853 (Opcode_Modifier_Max): Updated.
854 (i386_opcode_modifier): Add intelsyntax.
855 (i386_operand_type): Add mem.
856
857 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
858 instructions.
859
860 * i386-reg.tbl: Add size for accumulator.
861
862 * i386-init.h: Regenerated.
863 * i386-tbl.h: Likewise.
864
0d6a2f58
L		 8652008-01-13 H.J. Lu <hongjiu.lu@intel.com>
866
867 * i386-opc.h (Byte): Fix a typo.
868
7d5e4556
L		 8692008-01-12 H.J. Lu <hongjiu.lu@intel.com>
870
871 PR gas/5534
872 * i386-gen.c (operand_type_init): Add Dword to
873 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
874 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
875 Qword and Xmmword.
876 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
877 Xmmword, Unspecified and Anysize.
878 (set_bitfield): Make Mmword an alias of Qword. Make Oword
879 an alias of Xmmword.
880
881 * i386-opc.h (CheckSize): Removed.
882 (Byte): Updated.
883 (Word): Likewise.
884 (Dword): Likewise.
885 (Qword): Likewise.
886 (Xmmword): Likewise.
887 (FWait): Updated.
888 (OTMax): Likewise.
889 (i386_opcode_modifier): Remove checksize, byte, word, dword,
890 qword and xmmword.
891 (Fword): New.
892 (TBYTE): Likewise.
893 (Unspecified): Likewise.
894 (Anysize): Likewise.
895 (i386_operand_type): Add byte, word, dword, fword, qword,
896 tbyte xmmword, unspecified and anysize.
897
898 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
899 Tbyte, Xmmword, Unspecified and Anysize.
900
901 * i386-reg.tbl: Add size for accumulator.
902
903 * i386-init.h: Regenerated.
904 * i386-tbl.h: Likewise.
905
b5b1fc4f
L		 9062008-01-10 H.J. Lu <hongjiu.lu@intel.com>
907
908 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
909 (REG_0F18): Updated.
910 (reg_table): Updated.
911 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
912 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
913
50e8458f
L		 9142008-01-08 H.J. Lu <hongjiu.lu@intel.com>
915
916 * i386-gen.c (set_bitfield): Use fail () on error.
917
3d4d5afa
L		 9182008-01-08 H.J. Lu <hongjiu.lu@intel.com>
919
920 * i386-gen.c (lineno): New.
921 (filename): Likewise.
922 (set_bitfield): Report filename and line numer on error.
923 (process_i386_opcodes): Set filename and update lineno.
924 (process_i386_registers): Likewise.
925
e1d4d893
L		 9262008-01-05 H.J. Lu <hongjiu.lu@intel.com>
927
928 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
929 ATTSyntax.
930
931 * i386-opc.h (IntelMnemonic): Renamed to ..
932 (ATTSyntax): This
933 (Opcode_Modifier_Max): Updated.
934 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
935 and intelsyntax.
936
8944f3c2 937 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 938 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
939 * i386-tbl.h: Regenerated.
940
6f143e4d
L		 9412008-01-04 H.J. Lu <hongjiu.lu@intel.com>
942
943 * i386-gen.c: Update copyright to 2008.
944 * i386-opc.h: Likewise.
945 * i386-opc.tbl: Likewise.
946
947 * i386-init.h: Regenerated.
948 * i386-tbl.h: Likewise.
949
c6add537
L		 9502008-01-04 H.J. Lu <hongjiu.lu@intel.com>
951
952 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
953 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
954 * i386-tbl.h: Regenerated.
955
3629bb00
L		 9562008-01-03 H.J. Lu <hongjiu.lu@intel.com>
957
958 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
959 CpuSSE4_2_Or_ABM.
960 (cpu_flags): Likewise.
961
962 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
963 (CpuSSE4_2_Or_ABM): Likewise.
964 (CpuLM): Updated.
965 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
966
967 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
968 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
969 and CpuPadLock, respectively.
970 * i386-init.h: Regenerated.
971 * i386-tbl.h: Likewise.
972
24995bd6
L		 9732008-01-03 H.J. Lu <hongjiu.lu@intel.com>
974
975 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
976
977 * i386-opc.h (No_xSuf): Removed.
978 (CheckSize): Updated.
979
980 * i386-tbl.h: Regenerated.
981
e0329a22
L		 9822008-01-02 H.J. Lu <hongjiu.lu@intel.com>
983
984 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
985 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
986 CPU_SSE5_FLAGS.
987 (cpu_flags): Add CpuSSE4_2_Or_ABM.
988
989 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
990 (CpuLM): Updated.
991 (i386_cpu_flags): Add cpusse4_2_or_abm.
992
993 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
994 CpuABM|CpuSSE4_2 on popcnt.
995 * i386-init.h: Regenerated.
996 * i386-tbl.h: Likewise.
997
f2a9c676
L		 9982008-01-02 H.J. Lu <hongjiu.lu@intel.com>
999
1000 * i386-opc.h: Update comments.
1001
d978b5be
L		 10022008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1003
1004 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
1005 * i386-opc.h: Likewise.
1006 * i386-opc.tbl: Likewise.
1007
582d5edd
L		 10082008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1009
1010 PR gas/5534
1011 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
1012 Byte, Word, Dword, QWord and Xmmword.
1013
1014 * i386-opc.h (No_xSuf): New.
1015 (CheckSize): Likewise.
1016 (Byte): Likewise.
1017 (Word): Likewise.
1018 (Dword): Likewise.
1019 (QWord): Likewise.
1020 (Xmmword): Likewise.
1021 (FWait): Updated.
1022 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
1023 Dword, QWord and Xmmword.
1024
1025 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
1026 used.
1027 * i386-tbl.h: Regenerated.
1028
3fe15143
MK		 10292008-01-02 Mark Kettenis <kettenis@gnu.org>
1030
1031 * m88k-dis.c (instructions): Fix fcvt.* instructions.
1032 From Miod Vallat.
1033
6c7ac64e 1034For older changes see ChangeLog-2007
252b5132
RH		 1035\f
1036Local Variables:
2f6d2f85
NC		 1037mode: change-log
1038left-margin: 8
1039fill-column: 74
252b5132
RH		 1040version-control: never
1041End:
GDB Binutils - Deliverables
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