Configury changes: update src repository (binutils, gdb, and rda) to use
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
20e95c23
DJ
12006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
2
3 * Makefile.am (INCLUDES): Use @INCINTL@.
4 * acinclude.m4: Include new gettext macros.
5 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
6 Remove local code for po/Makefile.
7 * Makefile.in, aclocal.m4, configure: Regenerated.
8
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92006-05-30 Nick Clifton <nickc@redhat.com>
10
11 * po/es.po: Updated Spanish translation.
12
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132006-05-25 Richard Sandiford <richard@codesourcery.com>
14
15 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
16 and fmovem entries. Put register list entries before immediate
17 mask entries. Use "l" rather than "L" in the fmovem entries.
18 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
19 out from INFO.
20 (m68k_scan_mask): New function, split out from...
21 (print_insn_m68k): ...here. If no architecture has been set,
22 first try printing an m680x0 instruction, then try a Coldfire one.
23
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242006-05-24 Nick Clifton <nickc@redhat.com>
25
26 * po/ga.po: Updated Irish translation.
27
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282006-05-22 Nick Clifton <nickc@redhat.com>
29
30 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
31
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322006-05-22 Nick Clifton <nickc@redhat.com>
33
34 * po/nl.po: Updated translation.
35
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362006-05-18 Alan Modra <amodra@bigpond.net.au>
37
38 * avr-dis.c: Formatting fix.
39
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402006-05-14 Thiemo Seufer <ths@mips.com>
41
42 * mips16-opc.c (I1, I32, I64): New shortcut defines.
43 (mips16_opcodes): Change membership of instructions to their
44 lowest baseline ISA.
45
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462006-05-09 H.J. Lu <hongjiu.lu@intel.com>
47
48 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
49
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502006-05-05 Julian Brown <julian@codesourcery.com>
51
52 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
53 vldm/vstm.
54
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552006-05-05 Thiemo Seufer <ths@mips.com>
56 David Ung <davidu@mips.com>
57
58 * mips-opc.c: Add macro for cache instruction.
59
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602006-05-04 Thiemo Seufer <ths@mips.com>
61 Nigel Stephens <nigel@mips.com>
62 David Ung <davidu@mips.com>
63
64 * mips-dis.c (mips_arch_choices): Add smartmips instruction
65 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
66 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
67 MIPS64R2.
68 * mips-opc.c: fix random typos in comments.
69 (INSN_SMARTMIPS): New defines.
70 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
71 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
72 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
73 FP_S and FP_D flags to denote single and double register
74 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
75 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
76 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
77 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
78 release 2 ISAs.
79 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
80
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812006-05-03 Thiemo Seufer <ths@mips.com>
82
83 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
84
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852006-05-02 Thiemo Seufer <ths@mips.com>
86 Nigel Stephens <nigel@mips.com>
87 David Ung <davidu@mips.com>
88
89 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
90 (print_mips16_insn_arg): Force mips16 to odd addresses.
91
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922006-04-30 Thiemo Seufer <ths@mips.com>
93 David Ung <davidu@mips.com>
94
95 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
96 "udi0" to "udi15".
97 * mips-dis.c (print_insn_args): Adds udi argument handling.
98
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992006-04-28 James E Wilson <wilson@specifix.com>
100
101 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
102 error message.
103
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1042006-04-28 Thiemo Seufer <ths@mips.com>
105 David Ung <davidu@mips.com>
bdb09db1 106 Nigel Stephens <nigel@mips.com>
59c455b3
TS
107
108 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
109 names.
110
cc0ca239 1112006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 112 Nigel Stephens <nigel@mips.com>
cc0ca239
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113 David Ung <davidu@mips.com>
114
115 * mips-dis.c (print_insn_args): Add mips_opcode argument.
116 (print_insn_mips): Adjust print_insn_args call.
117
0d09bfe6 1182006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 119 Nigel Stephens <nigel@mips.com>
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120
121 * mips-dis.c (print_insn_args): Print $fcc only for FP
122 instructions, use $cc elsewise.
123
654c225a 1242006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 125 Nigel Stephens <nigel@mips.com>
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126
127 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
128 Map MIPS16 registers to O32 names.
129 (print_mips16_insn_arg): Use mips16_reg_names.
130
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1312006-04-26 Julian Brown <julian@codesourcery.com>
132
133 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
134 VMOV.
135
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1362006-04-26 Nathan Sidwell <nathan@codesourcery.com>
137 Julian Brown <julian@codesourcery.com>
138
139 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
140 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
141 Add unified load/store instruction names.
142 (neon_opcode_table): New.
143 (arm_opcodes): Expand meaning of %<bitfield>['`?].
144 (arm_decode_bitfield): New.
145 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
146 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
147 (print_insn_neon): New.
148 (print_insn_arm): Adjust print_insn_coprocessor call. Call
149 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
150 (print_insn_thumb32): Likewise.
151
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1522006-04-19 Alan Modra <amodra@bigpond.net.au>
153
154 * Makefile.am: Run "make dep-am".
155 * Makefile.in: Regenerate.
156
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1572006-04-19 Alan Modra <amodra@bigpond.net.au>
158
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159 * avr-dis.c (avr_operand): Warning fix.
160
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161 * configure: Regenerate.
162
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1632006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
164
165 * po/POTFILES.in: Regenerated.
166
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1672006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
168
169 PR binutils/2454
170 * avr-dis.c (avr_operand): Arrange for a comment to appear before
171 the symolic form of an address, so that the output of objdump -d
172 can be reassembled.
173
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1742006-04-10 DJ Delorie <dj@redhat.com>
175
176 * m32c-asm.c: Regenerate.
177
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1782006-04-06 Carlos O'Donell <carlos@codesourcery.com>
179
180 * Makefile.am: Add install-html target.
181 * Makefile.in: Regenerate.
182
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1832006-04-06 Nick Clifton <nickc@redhat.com>
184
185 * po/vi/po: Updated Vietnamese translation.
186
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1872006-03-31 Paul Koning <ni1d@arrl.net>
188
189 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
190
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1912006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
192
193 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
194 logic to identify halfword shifts.
195
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1962006-03-16 Paul Brook <paul@codesourcery.com>
197
198 * arm-dis.c (arm_opcodes): Rename swi to svc.
199 (thumb_opcodes): Ditto.
200
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2012006-03-13 DJ Delorie <dj@redhat.com>
202
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203 * m32c-asm.c: Regenerate.
204 * m32c-desc.c: Likewise.
205 * m32c-desc.h: Likewise.
206 * m32c-dis.c: Likewise.
207 * m32c-ibld.c: Likewise.
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DD
208 * m32c-opc.c: Likewise.
209 * m32c-opc.h: Likewise.
210
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2112006-03-10 DJ Delorie <dj@redhat.com>
212
213 * m32c-desc.c: Regenerate with mul.l, mulu.l.
214 * m32c-opc.c: Likewise.
215 * m32c-opc.h: Likewise.
216
217
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2182006-03-09 Nick Clifton <nickc@redhat.com>
219
220 * po/sv.po: Updated Swedish translation.
221
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2222006-03-07 H.J. Lu <hongjiu.lu@intel.com>
223
224 PR binutils/2428
225 * i386-dis.c (REP_Fixup): New function.
226 (AL): Remove duplicate.
227 (Xbr): New.
228 (Xvr): Likewise.
229 (Ybr): Likewise.
230 (Yvr): Likewise.
231 (indirDXr): Likewise.
232 (ALr): Likewise.
233 (eAXr): Likewise.
234 (dis386): Updated entries of ins, outs, movs, lods and stos.
235
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2362006-03-05 Nick Clifton <nickc@redhat.com>
237
238 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
239 signed 32-bit value into an unsigned 32-bit field when the host is
240 a 64-bit machine.
241 * fr30-ibld.c: Regenerate.
242 * frv-ibld.c: Regenerate.
243 * ip2k-ibld.c: Regenerate.
244 * iq2000-asm.c: Regenerate.
245 * iq2000-ibld.c: Regenerate.
246 * m32c-ibld.c: Regenerate.
247 * m32r-ibld.c: Regenerate.
248 * openrisc-ibld.c: Regenerate.
249 * xc16x-ibld.c: Regenerate.
250 * xstormy16-ibld.c: Regenerate.
251
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2522006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
253
254 * xc16x-asm.c: Regenerate.
255 * xc16x-dis.c: Regenerate.
c7d41dc5 256
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2572006-02-27 Carlos O'Donell <carlos@codesourcery.com>
258
259 * po/Make-in: Add html target.
260
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2612006-02-27 H.J. Lu <hongjiu.lu@intel.com>
262
263 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
264 Intel Merom New Instructions.
265 (THREE_BYTE_0): Likewise.
266 (THREE_BYTE_1): Likewise.
267 (three_byte_table): Likewise.
268 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
269 THREE_BYTE_1 for entry 0x3a.
270 (twobyte_has_modrm): Updated.
271 (twobyte_uses_SSE_prefix): Likewise.
272 (print_insn): Handle 3-byte opcodes used by Intel Merom New
273 Instructions.
274
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2752006-02-24 David S. Miller <davem@sunset.davemloft.net>
276
277 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
278 (v9_hpriv_reg_names): New table.
279 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
280 New cases '$' and '%' for read/write hyperprivileged register.
281 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
282 window handling and rdhpr/wrhpr instructions.
283
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DD
2842006-02-24 DJ Delorie <dj@redhat.com>
285
286 * m32c-desc.c: Regenerate with linker relaxation attributes.
287 * m32c-desc.h: Likewise.
288 * m32c-dis.c: Likewise.
289 * m32c-opc.c: Likewise.
290
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PB
2912006-02-24 Paul Brook <paul@codesourcery.com>
292
293 * arm-dis.c (arm_opcodes): Add V7 instructions.
294 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
295 (print_arm_address): New function.
296 (print_insn_arm): Use it. Add 'P' and 'U' cases.
297 (psr_name): New function.
298 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
299
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3002006-02-23 H.J. Lu <hongjiu.lu@intel.com>
301
302 * ia64-opc-i.c (bXc): New.
303 (mXc): Likewise.
304 (OpX2TaTbYaXcC): Likewise.
305 (TF). Likewise.
306 (TFCM). Likewise.
307 (ia64_opcodes_i): Add instructions for tf.
308
309 * ia64-opc.h (IMMU5b): New.
310
311 * ia64-asmtab.c: Regenerated.
312
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3132006-02-23 H.J. Lu <hongjiu.lu@intel.com>
314
315 * ia64-gen.c: Update copyright years.
316 * ia64-opc-b.c: Likewise.
317
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3182006-02-22 H.J. Lu <hongjiu.lu@intel.com>
319
320 * ia64-gen.c (lookup_regindex): Handle ".vm".
321 (print_dependency_table): Handle '\"'.
322
323 * ia64-ic.tbl: Updated from SDM 2.2.
324 * ia64-raw.tbl: Likewise.
325 * ia64-waw.tbl: Likewise.
326 * ia64-asmtab.c: Regenerated.
327
328 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
329
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3302006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
331 Anil Paranjape <anilp1@kpitcummins.com>
332 Shilin Shakti <shilins@kpitcummins.com>
333
334 * xc16x-desc.h: New file
335 * xc16x-desc.c: New file
336 * xc16x-opc.h: New file
337 * xc16x-opc.c: New file
338 * xc16x-ibld.c: New file
339 * xc16x-asm.c: New file
340 * xc16x-dis.c: New file
341 * Makefile.am: Entries for xc16x
342 * Makefile.in: Regenerate
343 * cofigure.in: Add xc16x target information.
344 * configure: Regenerate.
345 * disassemble.c: Add xc16x target information.
346
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3472006-02-11 H.J. Lu <hongjiu.lu@intel.com>
348
349 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
350 moves.
351
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3522006-02-11 H.J. Lu <hongjiu.lu@intel.com>
353
354 * i386-dis.c ('Z'): Add a new macro.
355 (dis386_twobyte): Use "movZ" for control register moves.
356
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3572006-02-10 Nick Clifton <nickc@redhat.com>
358
359 * iq2000-asm.c: Regenerate.
360
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3612006-02-07 Nathan Sidwell <nathan@codesourcery.com>
362
363 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
364
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3652006-01-26 David Ung <davidu@mips.com>
366
367 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
368 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
369 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
370 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
371 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
372
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3732006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
374
375 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
376 ld_d_r, pref_xd_cb): Use signed char to hold data to be
377 disassembled.
378 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
379 buffer overflows when disassembling instructions like
380 ld (ix+123),0x23
381 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
382 operand, if the offset is negative.
383
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AM
3842006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
385
386 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
387 unsigned char to hold data to be disassembled.
388
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3892006-01-17 Andreas Schwab <schwab@suse.de>
390
391 PR binutils/1486
392 * disassemble.c (disassemble_init_for_target): Set
393 disassembler_needs_relocs for bfd_arch_arm.
394
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PB
3952006-01-16 Paul Brook <paul@codesourcery.com>
396
e88d958a 397 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
c2fe9327
PB
398 f?add?, and f?sub? instructions.
399
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4002006-01-16 Nick Clifton <nickc@redhat.com>
401
402 * po/zh_CN.po: New Chinese (simplified) translation.
403 * configure.in (ALL_LINGUAS): Add "zh_CH".
404 * configure: Regenerate.
405
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4062006-01-05 Paul Brook <paul@codesourcery.com>
407
408 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
409
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4102006-01-06 DJ Delorie <dj@redhat.com>
411
412 * m32c-desc.c: Regenerate.
413 * m32c-opc.c: Regenerate.
414 * m32c-opc.h: Regenerate.
415
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4162006-01-03 DJ Delorie <dj@redhat.com>
417
418 * cgen-ibld.in (extract_normal): Avoid memory range errors.
419 * m32c-ibld.c: Regenerated.
420
e88d958a 421For older changes see ChangeLog-2005
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422\f
423Local Variables:
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424mode: change-log
425left-margin: 8
426fill-column: 74
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427version-control: never
428End:
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