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Change the type of the aarch64_feature_set typedef to unsigned long long so that...
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c0e7cef7
NC		 12017-11-08 Tamar Christina <tamar.christina@arm.com>
2
3 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
4 (aarch64_feature_sha2, aarch64_feature_aes): New.
5 (SHA2, AES): New.
6 (AES_INSN, SHA2_INSN): New.
7 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
8 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
9 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
10 Change to SHA2_INS.
11
dec41383
JW		 122017-11-08 Jiong Wang <jiong.wang@arm.com>
13 Tamar Christina <tamar.christina@arm.com>
14
15 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
16 FP16 instructions, including vfmal.f16 and vfmsl.f16.
17
52eab766
AB		 182017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
19
20 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
21
6003e27e
AM		 222017-11-07 Alan Modra <amodra@gmail.com>
23
24 * opintl.h: Formatting, comment fixes.
25 (gettext, ngettext): Redefine when ENABLE_NLS.
26 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
27 (_): Define using gettext.
28 (textdomain, bindtextdomain): Use safer "do nothing".
29
fdddd290 302017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
31
32 * arc-dis.c (print_hex): New variable.
33 (parse_option): Check for hex option.
34 (print_insn_arc): Use hexadecimal representation for short
35 immediate values when requested.
36 (print_arc_disassembler_options): Add hex option to the list.
37
3334eba7 382017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
39
40 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
41 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
42 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
43 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
44 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
45 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
46 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
47 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
48 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
49 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
50 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
51 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
52 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
53 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
54 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
55 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
56 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
57 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
58 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
59 Changed opcodes.
60 (prealloc, prefetch*): Place them before ld instruction.
61 * arc-opc.c (skip_this_opcode): Add ARITH class.
62
e5d70d6b
AM		 632017-10-25 Alan Modra <amodra@gmail.com>
64
65 PR 22348
66 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
67 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
68 (imm4flag, size_changed): Likewise.
69 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
70 (words, allWords, processing_argument_number): Likewise.
71 (cst4flag, size_changed): Likewise.
72 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
73 (crx_cst4_maps): Rename from cst4_maps.
74 (crx_no_op_insn): Rename from no_op_insn.
75
63a25ea0
AW		 762017-10-24 Andrew Waterman <andrew@sifive.com>
77
78 * riscv-opc.c (match_c_addi16sp) : New function.
79 (match_c_addi4spn): New function.
80 (match_c_lui): Don't allow 0-immediate encodings.
81 (riscv_opcodes) <addi>: Use the above functions.
82 <add>: Likewise.
83 <c.addi4spn>: Likewise.
84 <c.addi16sp>: Likewise.
85
fe4e2a3c
IT		 862017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
87
88 * i386-init.h: Regenerate
89 * i386-tbl.h: Likewise
90
2739ef6d
IT		 912017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
92
93 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
94 (enum): Add EVEX_W_0F3854_P_2.
95 * i386-dis-evex.h (evex_table): Updated.
96 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
97 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
98 (cpu_flags): Add CpuAVX512_BITALG.
99 * i386-opc.h (enum): Add CpuAVX512_BITALG.
100 (i386_cpu_flags): Add cpuavx512_bitalg..
101 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
102 * i386-init.h: Regenerate.
103 * i386-tbl.h: Likewise.
104
1052017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
106
107 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
108 * i386-dis-evex.h (evex_table): Updated.
109 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
110 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
111 (cpu_flags): Add CpuAVX512_VNNI.
112 * i386-opc.h (enum): Add CpuAVX512_VNNI.
113 (i386_cpu_flags): Add cpuavx512_vnni.
114 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
115 * i386-init.h: Regenerate.
116 * i386-tbl.h: Likewise.
117
1182017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
119
120 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
121 (enum): Remove VEX_LEN_0F3A44_P_2.
122 (vex_len_table): Ditto.
123 (enum): Remove VEX_W_0F3A44_P_2.
124 (vew_w_table): Ditto.
125 (prefix_table): Adjust instructions (see prefixes above).
126 * i386-dis-evex.h (evex_table):
127 Add new instructions (see prefixes above).
128 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
129 (bitfield_cpu_flags): Ditto.
130 * i386-opc.h (enum): Ditto.
131 (i386_cpu_flags): Ditto.
132 (CpuUnused): Comment out to avoid zero-width field problem.
133 * i386-opc.tbl (vpclmulqdq): New instruction.
134 * i386-init.h: Regenerate.
135 * i386-tbl.h: Ditto.
136
1372017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
138
139 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
140 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
141 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
142 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
143 (vex_len_table): Ditto.
144 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
145 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
146 (vew_w_table): Ditto.
147 (prefix_table): Adjust instructions (see prefixes above).
148 * i386-dis-evex.h (evex_table):
149 Add new instructions (see prefixes above).
150 * i386-gen.c (cpu_flag_init): Add VAES.
151 (bitfield_cpu_flags): Ditto.
152 * i386-opc.h (enum): Ditto.
153 (i386_cpu_flags): Ditto.
154 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
155 * i386-init.h: Regenerate.
156 * i386-tbl.h: Ditto.
157
1582017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
159
160 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
161 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
162 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
163 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
164 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
165 (prefix_table): Updated (see prefixes above).
166 (three_byte_table): Likewise.
167 (vex_w_table): Likewise.
168 * i386-dis-evex.h: Likewise.
169 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
170 (cpu_flags): Add CpuGFNI.
171 * i386-opc.h (enum): Add CpuGFNI.
172 (i386_cpu_flags): Add cpugfni.
173 * i386-opc.tbl: Add Intel GFNI instructions.
174 * i386-init.h: Regenerate.
175 * i386-tbl.h: Likewise.
176
1772017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
178
179 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
180 Define EXbScalar and EXwScalar for OP_EX.
181 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
182 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
183 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
184 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
185 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
186 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
187 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
188 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
189 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
190 (OP_E_memory): Likewise.
191 * i386-dis-evex.h: Updated.
192 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
193 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
194 (cpu_flags): Add CpuAVX512_VBMI2.
195 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
196 (i386_cpu_flags): Add cpuavx512_vbmi2.
197 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
198 * i386-init.h: Regenerate.
199 * i386-tbl.h: Likewise.
200
2a6969e1
EB		 2012017-10-18 Eric Botcazou <ebotcazou@adacore.com>
202
203 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
204
3b4b0a62
JB		 2052017-10-12 James Bowman <james.bowman@ftdichip.com>
206
207 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
208 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
209 K15. Add jmpix pattern.
210
8e464506
AK		 2112017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
212
213 * s390-opc.txt (prno, tpei, irbm): New instructions added.
214
ee6767da
AK		 2152017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
216
217 * s390-opc.c (INSTR_SI_RD): New macro.
218 (INSTR_S_RD): Adjust example instruction.
219 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
220 SI_RD.
221
d2e6c9a3
AF		 2222017-10-01 Alexander Fedotov <alfedotov@gmail.com>
223
224 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
225 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
226 VLE multimple load/store instructions. Old e_ldm* variants are
227 kept as aliases.
228 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
229
8e43602e
NC		 2302017-09-27 Nick Clifton <nickc@redhat.com>
231
232 PR 22179
233 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
234 names for the fmv.x.s and fmv.s.x instructions respectively.
235
58a0b827
NC		 2362017-09-26 do <do@nerilex.org>
237
238 PR 22123
239 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
240 be used on CPUs that have emacs support.
241
57a024f4
SDJ		 2422017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
243
244 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
245
4ec521f2
KLC		 2462017-09-09 Kamil Rytarowski <n54@gmx.com>
247
248 * nds32-asm.c: Rename __BIT() to N32_BIT().
249 * nds32-asm.h: Likewise.
250 * nds32-dis.c: Likewise.
251
4e9ac44a
L		 2522017-09-09 H.J. Lu <hongjiu.lu@intel.com>
253
254 * i386-dis.c (last_active_prefix): Removed.
255 (ckprefix): Don't set last_active_prefix.
256 (NOTRACK_Fixup): Don't check last_active_prefix.
257
b55f3386
NC		 2582017-08-31 Nick Clifton <nickc@redhat.com>
259
260 * po/fr.po: Updated French translation.
261
59e8523b
JB		 2622017-08-31 James Bowman <james.bowman@ftdichip.com>
263
264 * ft32-dis.c (print_insn_ft32): Correct display of non-address
265 fields.
266
74081948
AF		 2672017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
268 Edmar Wienskoski <edmar.wienskoski@nxp.com>
269
270 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
271 PPC_OPCODE_EFS2 flag to "e200z4" entry.
272 New entries efs2 and spe2.
273 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
274 (SPE2_OPCD_SEGS): New macro.
275 (spe2_opcd_indices): New.
276 (disassemble_init_powerpc): Handle SPE2 opcodes.
277 (lookup_spe2): New function.
278 (print_insn_powerpc): call lookup_spe2.
279 * ppc-opc.c (insert_evuimm1_ex0): New function.
280 (extract_evuimm1_ex0): Likewise.
281 (insert_evuimm_lt8): Likewise.
282 (extract_evuimm_lt8): Likewise.
283 (insert_off_spe2): Likewise.
284 (extract_off_spe2): Likewise.
285 (insert_Ddd): Likewise.
286 (extract_Ddd): Likewise.
287 (DD): New operand.
288 (EVUIMM_LT8): Likewise.
289 (EVUIMM_LT16): Adjust.
290 (MMMM): New operand.
291 (EVUIMM_1): Likewise.
292 (EVUIMM_1_EX0): Likewise.
293 (EVUIMM_2): Adjust.
294 (NNN): New operand.
295 (VX_OFF_SPE2): Likewise.
296 (BBB): Likewise.
297 (DDD): Likewise.
298 (VX_MASK_DDD): New mask.
299 (HH): New operand.
300 (VX_RA_CONST): New macro.
301 (VX_RA_CONST_MASK): Likewise.
302 (VX_RB_CONST): Likewise.
303 (VX_RB_CONST_MASK): Likewise.
304 (VX_OFF_SPE2_MASK): Likewise.
305 (VX_SPE_CRFD): Likewise.
306 (VX_SPE_CRFD_MASK VX): Likewise.
307 (VX_SPE2_CLR): Likewise.
308 (VX_SPE2_CLR_MASK): Likewise.
309 (VX_SPE2_SPLATB): Likewise.
310 (VX_SPE2_SPLATB_MASK): Likewise.
311 (VX_SPE2_OCTET): Likewise.
312 (VX_SPE2_OCTET_MASK): Likewise.
313 (VX_SPE2_DDHH): Likewise.
314 (VX_SPE2_DDHH_MASK): Likewise.
315 (VX_SPE2_HH): Likewise.
316 (VX_SPE2_HH_MASK): Likewise.
317 (VX_SPE2_EVMAR): Likewise.
318 (VX_SPE2_EVMAR_MASK): Likewise.
319 (PPCSPE2): Likewise.
320 (PPCEFS2): Likewise.
321 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
322 (powerpc_macros): Map old SPE instructions have new names
323 with the same opcodes. Add SPE2 instructions which just are
324 mapped to SPE2.
325 (spe2_opcodes): Add SPE2 opcodes.
326
b80c7270
AM		 3272017-08-23 Alan Modra <amodra@gmail.com>
328
329 * ppc-opc.c: Formatting and comment fixes. Move insert and
330 extract functions earlier, deleting forward declarations.
331 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
332 RA_MASK.
333
67d888f5
PD		 3342017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
335
336 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
337
e3c2f928
AF		 3382017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
339 Edmar Wienskoski <edmar.wienskoski@nxp.com>
340
341 * ppc-opc.c (insert_evuimm2_ex0): New function.
342 (extract_evuimm2_ex0): Likewise.
343 (insert_evuimm4_ex0): Likewise.
344 (extract_evuimm4_ex0): Likewise.
345 (insert_evuimm8_ex0): Likewise.
346 (extract_evuimm8_ex0): Likewise.
347 (insert_evuimm_lt16): Likewise.
348 (extract_evuimm_lt16): Likewise.
349 (insert_rD_rS_even): Likewise.
350 (extract_rD_rS_even): Likewise.
351 (insert_off_lsp): Likewise.
352 (extract_off_lsp): Likewise.
353 (RD_EVEN): New operand.
354 (RS_EVEN): Likewise.
355 (RSQ): Adjust.
356 (EVUIMM_LT16): New operand.
357 (HTM_SI): Adjust.
358 (EVUIMM_2_EX0): New operand.
359 (EVUIMM_4): Adjust.
360 (EVUIMM_4_EX0): New operand.
361 (EVUIMM_8): Adjust.
362 (EVUIMM_8_EX0): New operand.
363 (WS): Adjust.
364 (VX_OFF): New operand.
365 (VX_LSP): New macro.
366 (VX_LSP_MASK): Likewise.
367 (VX_LSP_OFF_MASK): Likewise.
368 (PPC_OPCODE_LSP): Likewise.
369 (vle_opcodes): Add LSP opcodes.
370 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
371
cc4a945a
JW		 3722017-08-09 Jiong Wang <jiong.wang@arm.com>
373
374 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
375 register operands in CRC instructions.
376 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
377 comments.
378
b28b8b5e
L		 3792017-08-07 H.J. Lu <hongjiu.lu@intel.com>
380
381 * disassemble.c (disassembler): Mark big and mach with
382 ATTRIBUTE_UNUSED.
383
e347efc3
MR		 3842017-08-07 Maciej W. Rozycki <macro@imgtec.com>
385
386 * disassemble.c (disassembler): Remove arch/mach/endian
387 assertions.
388
7cbc739c
NC		 3892017-07-25 Nick Clifton <nickc@redhat.com>
390
391 PR 21739
392 * arc-opc.c (insert_rhv2): Use lower case first letter in error
393 message.
394 (insert_r0): Likewise.
395 (insert_r1): Likewise.
396 (insert_r2): Likewise.
397 (insert_r3): Likewise.
398 (insert_sp): Likewise.
399 (insert_gp): Likewise.
400 (insert_pcl): Likewise.
401 (insert_blink): Likewise.
402 (insert_ilink1): Likewise.
403 (insert_ilink2): Likewise.
404 (insert_ras): Likewise.
405 (insert_rbs): Likewise.
406 (insert_rcs): Likewise.
407 (insert_simm3s): Likewise.
408 (insert_rrange): Likewise.
409 (insert_r13el): Likewise.
410 (insert_fpel): Likewise.
411 (insert_blinkel): Likewise.
412 (insert_pclel): Likewise.
413 (insert_nps_bitop_size_2b): Likewise.
414 (insert_nps_imm_offset): Likewise.
415 (insert_nps_imm_entry): Likewise.
416 (insert_nps_size_16bit): Likewise.
417 (insert_nps_##NAME##_pos): Likewise.
418 (insert_nps_##NAME): Likewise.
419 (insert_nps_bitop_ins_ext): Likewise.
420 (insert_nps_##NAME): Likewise.
421 (insert_nps_min_hofs): Likewise.
422 (insert_nps_##NAME): Likewise.
423 (insert_nps_rbdouble_64): Likewise.
424 (insert_nps_misc_imm_offset): Likewise.
425 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
426 option description.
427
7684e580
JW		 4282017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
429 Jiong Wang <jiong.wang@arm.com>
430
431 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
432 correct the print.
433 * aarch64-dis-2.c: Regenerated.
434
47826cdb
AK		 4352017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
436
437 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
438 table.
439
2d2dbad0
NC		 4402017-07-20 Nick Clifton <nickc@redhat.com>
441
442 * po/de.po: Updated German translation.
443
70b448ba 4442017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
445
446 * arc-regs.h (sec_stat): New aux register.
447 (aux_kernel_sp): Likewise.
448 (aux_sec_u_sp): Likewise.
449 (aux_sec_k_sp): Likewise.
450 (sec_vecbase_build): Likewise.
451 (nsc_table_top): Likewise.
452 (nsc_table_base): Likewise.
453 (ersec_stat): Likewise.
454 (aux_sec_except): Likewise.
455
7179e0e6
CZ		 4562017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
457
458 * arc-opc.c (extract_uimm12_20): New function.
459 (UIMM12_20): New operand.
460 (SIMM3_5_S): Adjust.
461 * arc-tbl.h (sjli): Add new instruction.
462
684d5a10
JEM		 4632017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
464 John Eric Martin <John.Martin@emmicro-us.com>
465
466 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
467 (UIMM3_23): Adjust accordingly.
468 * arc-regs.h: Add/correct jli_base register.
469 * arc-tbl.h (jli_s): Likewise.
470
de194d85
YC		 4712017-07-18 Nick Clifton <nickc@redhat.com>
472
473 PR 21775
474 * aarch64-opc.c: Fix spelling typos.
475 * i386-dis.c: Likewise.
476
0f6329bd
RB		 4772017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
478
479 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
480 max_addr_offset and octets variables to size_t.
481
429d795d
AM		 4822017-07-12 Alan Modra <amodra@gmail.com>
483
484 * po/da.po: Update from translationproject.org/latest/opcodes/.
485 * po/de.po: Likewise.
486 * po/es.po: Likewise.
487 * po/fi.po: Likewise.
488 * po/fr.po: Likewise.
489 * po/id.po: Likewise.
490 * po/it.po: Likewise.
491 * po/nl.po: Likewise.
492 * po/pt_BR.po: Likewise.
493 * po/ro.po: Likewise.
494 * po/sv.po: Likewise.
495 * po/tr.po: Likewise.
496 * po/uk.po: Likewise.
497 * po/vi.po: Likewise.
498 * po/zh_CN.po: Likewise.
499
4162bb66
AM		 5002017-07-11 Yao Qi <yao.qi@linaro.org>
501 Alan Modra <amodra@gmail.com>
502
503 * cgen.sh: Mark generated files read-only.
504 * epiphany-asm.c: Regenerate.
505 * epiphany-desc.c: Regenerate.
506 * epiphany-desc.h: Regenerate.
507 * epiphany-dis.c: Regenerate.
508 * epiphany-ibld.c: Regenerate.
509 * epiphany-opc.c: Regenerate.
510 * epiphany-opc.h: Regenerate.
511 * fr30-asm.c: Regenerate.
512 * fr30-desc.c: Regenerate.
513 * fr30-desc.h: Regenerate.
514 * fr30-dis.c: Regenerate.
515 * fr30-ibld.c: Regenerate.
516 * fr30-opc.c: Regenerate.
517 * fr30-opc.h: Regenerate.
518 * frv-asm.c: Regenerate.
519 * frv-desc.c: Regenerate.
520 * frv-desc.h: Regenerate.
521 * frv-dis.c: Regenerate.
522 * frv-ibld.c: Regenerate.
523 * frv-opc.c: Regenerate.
524 * frv-opc.h: Regenerate.
525 * ip2k-asm.c: Regenerate.
526 * ip2k-desc.c: Regenerate.
527 * ip2k-desc.h: Regenerate.
528 * ip2k-dis.c: Regenerate.
529 * ip2k-ibld.c: Regenerate.
530 * ip2k-opc.c: Regenerate.
531 * ip2k-opc.h: Regenerate.
532 * iq2000-asm.c: Regenerate.
533 * iq2000-desc.c: Regenerate.
534 * iq2000-desc.h: Regenerate.
535 * iq2000-dis.c: Regenerate.
536 * iq2000-ibld.c: Regenerate.
537 * iq2000-opc.c: Regenerate.
538 * iq2000-opc.h: Regenerate.
539 * lm32-asm.c: Regenerate.
540 * lm32-desc.c: Regenerate.
541 * lm32-desc.h: Regenerate.
542 * lm32-dis.c: Regenerate.
543 * lm32-ibld.c: Regenerate.
544 * lm32-opc.c: Regenerate.
545 * lm32-opc.h: Regenerate.
546 * lm32-opinst.c: Regenerate.
547 * m32c-asm.c: Regenerate.
548 * m32c-desc.c: Regenerate.
549 * m32c-desc.h: Regenerate.
550 * m32c-dis.c: Regenerate.
551 * m32c-ibld.c: Regenerate.
552 * m32c-opc.c: Regenerate.
553 * m32c-opc.h: Regenerate.
554 * m32r-asm.c: Regenerate.
555 * m32r-desc.c: Regenerate.
556 * m32r-desc.h: Regenerate.
557 * m32r-dis.c: Regenerate.
558 * m32r-ibld.c: Regenerate.
559 * m32r-opc.c: Regenerate.
560 * m32r-opc.h: Regenerate.
561 * m32r-opinst.c: Regenerate.
562 * mep-asm.c: Regenerate.
563 * mep-desc.c: Regenerate.
564 * mep-desc.h: Regenerate.
565 * mep-dis.c: Regenerate.
566 * mep-ibld.c: Regenerate.
567 * mep-opc.c: Regenerate.
568 * mep-opc.h: Regenerate.
569 * mt-asm.c: Regenerate.
570 * mt-desc.c: Regenerate.
571 * mt-desc.h: Regenerate.
572 * mt-dis.c: Regenerate.
573 * mt-ibld.c: Regenerate.
574 * mt-opc.c: Regenerate.
575 * mt-opc.h: Regenerate.
576 * or1k-asm.c: Regenerate.
577 * or1k-desc.c: Regenerate.
578 * or1k-desc.h: Regenerate.
579 * or1k-dis.c: Regenerate.
580 * or1k-ibld.c: Regenerate.
581 * or1k-opc.c: Regenerate.
582 * or1k-opc.h: Regenerate.
583 * or1k-opinst.c: Regenerate.
584 * xc16x-asm.c: Regenerate.
585 * xc16x-desc.c: Regenerate.
586 * xc16x-desc.h: Regenerate.
587 * xc16x-dis.c: Regenerate.
588 * xc16x-ibld.c: Regenerate.
589 * xc16x-opc.c: Regenerate.
590 * xc16x-opc.h: Regenerate.
591 * xstormy16-asm.c: Regenerate.
592 * xstormy16-desc.c: Regenerate.
593 * xstormy16-desc.h: Regenerate.
594 * xstormy16-dis.c: Regenerate.
595 * xstormy16-ibld.c: Regenerate.
596 * xstormy16-opc.c: Regenerate.
597 * xstormy16-opc.h: Regenerate.
598
7639175c
AM		 5992017-07-07 Alan Modra <amodra@gmail.com>
600
601 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
602 * m32c-dis.c: Regenerate.
603 * mep-dis.c: Regenerate.
604
e4bdd679
BP		 6052017-07-05 Borislav Petkov <bp@suse.de>
606
607 * i386-dis.c: Enable ModRM.reg /6 aliases.
608
60c96dbf
RR		 6092017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
610
611 * opcodes/arm-dis.c: Support MVFR2 in disassembly
612 with vmrs and vmsr.
613
0d702cfe
TG		 6142017-07-04 Tristan Gingold <gingold@adacore.com>
615
616 * configure: Regenerate.
617
15e6ed8c
TG		 6182017-07-03 Tristan Gingold <gingold@adacore.com>
619
620 * po/opcodes.pot: Regenerate.
621
b1d3c886
MR		 6222017-06-30 Maciej W. Rozycki <macro@imgtec.com>
623
624 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
625 entries to the MSA ASE instruction block.
626
909b4e3d
MR		 6272017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
628 Maciej W. Rozycki <macro@imgtec.com>
629
630 * micromips-opc.c (XPA, XPAVZ): New macros.
631 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
632 "mthgc0".
633
f5b2fd52
MR		 6342017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
635 Maciej W. Rozycki <macro@imgtec.com>
636
637 * micromips-opc.c (I36): New macro.
638 (micromips_opcodes): Add "eretnc".
639
9785fc2a
MR		 6402017-06-30 Maciej W. Rozycki <macro@imgtec.com>
641 Andrew Bennett <andrew.bennett@imgtec.com>
642
643 * mips-dis.c (mips_calculate_combination_ases): Handle the
644 ASE_XPA_VIRT flag.
645 (parse_mips_ase_option): New function.
646 (parse_mips_dis_option): Factor out ASE option handling to the
647 new function. Call `mips_calculate_combination_ases'.
648 * mips-opc.c (XPAVZ): New macro.
649 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
650 "mfhgc0", "mthc0" and "mthgc0".
651
60804c53
MR		 6522017-06-29 Maciej W. Rozycki <macro@imgtec.com>
653
654 * mips-dis.c (mips_calculate_combination_ases): New function.
655 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
656 calculation to the new function.
657 (set_default_mips_dis_options): Call the new function.
658
2e74f9dd
AK		 6592017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
660
661 * arc-dis.c (parse_disassembler_options): Use
662 FOR_EACH_DISASSEMBLER_OPTION.
663
e1e94c49
AK		 6642017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
665
666 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
667 disassembler option strings.
668 (parse_cpu_option): Likewise.
669
65a55fbb
TC		 6702017-06-28 Tamar Christina <tamar.christina@arm.com>
671
672 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
673 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
674 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
675 (aarch64_feature_dotprod, DOT_INSN): New.
676 (udot, sdot): New.
677 * aarch64-dis-2.c: Regenerated.
678
c604a79a
JW		 6792017-06-28 Jiong Wang <jiong.wang@arm.com>
680
681 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
682
38bf472a
MR		 6832017-06-28 Maciej W. Rozycki <macro@imgtec.com>
684 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 685 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 686
687 * mips-formats.h (INT_BIAS): New macro.
688 (INT_ADJ): Redefine in INT_BIAS terms.
689 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
690 (mips_print_save_restore): New function.
691 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
692 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
693 call.
694 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
695 (print_mips16_insn_arg): Call `mips_print_save_restore' for
696 OP_SAVE_RESTORE_LIST handling, factored out from here.
697 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
698 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
699 (mips_builtin_opcodes): Add "restore" and "save" entries.
700 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
701 (IAMR2): New macro.
702 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
703
9bdfdbf9
AW		 7042017-06-23 Andrew Waterman <andrew@sifive.com>
705
706 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
707 alias; do not mark SLTI instruction as an alias.
708
2234eee6
L		 7092017-06-21 H.J. Lu <hongjiu.lu@intel.com>
710
711 * i386-dis.c (RM_0FAE_REG_5): Removed.
712 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
713 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
714 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
715 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
716 PREFIX_MOD_3_0F01_REG_5_RM_0.
717 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
718 PREFIX_MOD_3_0FAE_REG_5.
719 (mod_table): Update MOD_0FAE_REG_5.
720 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
721 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
722 * i386-tbl.h: Regenerated.
723
c2f76402
L		 7242017-06-21 H.J. Lu <hongjiu.lu@intel.com>
725
726 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
727 * i386-opc.tbl: Likewise.
728 * i386-tbl.h: Regenerated.
729
9fef80d6
L		 7302017-06-21 H.J. Lu <hongjiu.lu@intel.com>
731
732 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
733 and "jmp{&|}".
734 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
735 prefix.
736
0f6d864d
NC		 7372017-06-19 Nick Clifton <nickc@redhat.com>
738
739 PR binutils/21614
740 * score-dis.c (score_opcodes): Add sentinel.
741
e197589b
AM		 7422017-06-16 Alan Modra <amodra@gmail.com>
743
744 * rx-decode.c: Regenerate.
745
0d96e4df
L		 7462017-06-15 H.J. Lu <hongjiu.lu@intel.com>
747
748 PR binutils/21594
749 * i386-dis.c (OP_E_register): Check valid bnd register.
750 (OP_G): Likewise.
751
cd3ea7c6
NC		 7522017-06-15 Nick Clifton <nickc@redhat.com>
753
754 PR binutils/21595
755 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
756 range value.
757
63323b5b
NC		 7582017-06-15 Nick Clifton <nickc@redhat.com>
759
760 PR binutils/21588
761 * rl78-decode.opc (OP_BUF_LEN): Define.
762 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
763 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
764 array.
765 * rl78-decode.c: Regenerate.
766
08c7881b
NC		 7672017-06-15 Nick Clifton <nickc@redhat.com>
768
769 PR binutils/21586
770 * bfin-dis.c (gregs): Clip index to prevent overflow.
771 (regs): Likewise.
772 (regs_lo): Likewise.
773 (regs_hi): Likewise.
774
e64519d1
NC		 7752017-06-14 Nick Clifton <nickc@redhat.com>
776
777 PR binutils/21576
778 * score7-dis.c (score_opcodes): Add sentinel.
779
6394c606
YQ		 7802017-06-14 Yao Qi <yao.qi@linaro.org>
781
782 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
783 * arm-dis.c: Likewise.
784 * ia64-dis.c: Likewise.
785 * mips-dis.c: Likewise.
786 * spu-dis.c: Likewise.
787 * disassemble.h (print_insn_aarch64): New declaration, moved from
788 include/dis-asm.h.
789 (print_insn_big_arm, print_insn_big_mips): Likewise.
790 (print_insn_i386, print_insn_ia64): Likewise.
791 (print_insn_little_arm, print_insn_little_mips): Likewise.
792
db5fa770
NC		 7932017-06-14 Nick Clifton <nickc@redhat.com>
794
795 PR binutils/21587
796 * rx-decode.opc: Include libiberty.h
797 (GET_SCALE): New macro - validates access to SCALE array.
798 (GET_PSCALE): New macro - validates access to PSCALE array.
799 (DIs, SIs, S2Is, rx_disp): Use new macros.
800 * rx-decode.c: Regenerate.
801
05c966f3
AV		 8022017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
803
804 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
805
10045478
AK		 8062017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
807
808 * arc-dis.c (enforced_isa_mask): Declare.
809 (cpu_types): Likewise.
810 (parse_cpu_option): New function.
811 (parse_disassembler_options): Use it.
812 (print_insn_arc): Use enforced_isa_mask.
813 (print_arc_disassembler_options): Document new options.
814
88c1242d
YQ		 8152017-05-24 Yao Qi <yao.qi@linaro.org>
816
817 * alpha-dis.c: Include disassemble.h, don't include
818 dis-asm.h.
819 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
820 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
821 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
822 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
823 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
824 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
825 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
826 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
827 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
828 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
829 * moxie-dis.c, msp430-dis.c, mt-dis.c:
830 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
831 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
832 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
833 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
834 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
835 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
836 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
837 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
838 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
839 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
840 * z80-dis.c, z8k-dis.c: Likewise.
841 * disassemble.h: New file.
842
ab20fa4a
YQ		 8432017-05-24 Yao Qi <yao.qi@linaro.org>
844
845 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
846 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
847
003ca0fd
YQ		 8482017-05-24 Yao Qi <yao.qi@linaro.org>
849
850 * disassemble.c (disassembler): Add arguments a, big and mach.
851 Use them.
852
04ef582a
L		 8532017-05-22 H.J. Lu <hongjiu.lu@intel.com>
854
855 * i386-dis.c (NOTRACK_Fixup): New.
856 (NOTRACK): Likewise.
857 (NOTRACK_PREFIX): Likewise.
858 (last_active_prefix): Likewise.
859 (reg_table): Use NOTRACK on indirect call and jmp.
860 (ckprefix): Set last_active_prefix.
861 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
862 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
863 * i386-opc.h (NoTrackPrefixOk): New.
864 (i386_opcode_modifier): Add notrackprefixok.
865 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
866 Add notrack.
867 * i386-tbl.h: Regenerated.
868
64517994
JM		 8692017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
870
871 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
872 (X_IMM2): Define.
873 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
874 bfd_mach_sparc_v9m8.
875 (print_insn_sparc): Handle new operand types.
876 * sparc-opc.c (MASK_M8): Define.
877 (v6): Add MASK_M8.
878 (v6notlet): Likewise.
879 (v7): Likewise.
880 (v8): Likewise.
881 (v9): Likewise.
882 (v9a): Likewise.
883 (v9b): Likewise.
884 (v9c): Likewise.
885 (v9d): Likewise.
886 (v9e): Likewise.
887 (v9v): Likewise.
888 (v9m): Likewise.
889 (v9andleon): Likewise.
890 (m8): Define.
891 (HWS_VM8): Define.
892 (HWS2_VM8): Likewise.
893 (sparc_opcode_archs): Add entry for "m8".
894 (sparc_opcodes): Add OSA2017 and M8 instructions
895 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
896 fpx{ll,ra,rl}64x,
897 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
898 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
899 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
900 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
901 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
902 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
903 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
904 ASI_CORE_SELECT_COMMIT_NHT.
905
535b785f
AM		 9062017-05-18 Alan Modra <amodra@gmail.com>
907
908 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
909 * aarch64-dis.c: Likewise.
910 * aarch64-gen.c: Likewise.
911 * aarch64-opc.c: Likewise.
912
25499ac7
MR		 9132017-05-15 Maciej W. Rozycki <macro@imgtec.com>
914 Matthew Fortune <matthew.fortune@imgtec.com>
915
916 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
917 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
918 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
919 (print_insn_arg) <OP_REG28>: Add handler.
920 (validate_insn_args) <OP_REG28>: Handle.
921 (print_mips16_insn_arg): Handle MIPS16 instructions that require
922 32-bit encoding and 9-bit immediates.
923 (print_insn_mips16): Handle MIPS16 instructions that require
924 32-bit encoding and MFC0/MTC0 operand decoding.
925 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
926 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
927 (RD_C0, WR_C0, E2, E2MT): New macros.
928 (mips16_opcodes): Add entries for MIPS16e2 instructions:
929 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
930 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
931 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
932 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
933 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
934 instructions, "swl", "swr", "sync" and its "sync_acquire",
935 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
936 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
937 regular/extended entries for original MIPS16 ISA revision
938 instructions whose extended forms are subdecoded in the MIPS16e2
939 ISA revision: "li", "sll" and "srl".
940
fdfb4752
MR		 9412017-05-15 Maciej W. Rozycki <macro@imgtec.com>
942
943 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
944 reference in CP0 move operand decoding.
945
a4f89915
MR		 9462017-05-12 Maciej W. Rozycki <macro@imgtec.com>
947
948 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
949 type to hexadecimal.
950 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
951
99e2d67a
MR		 9522017-05-11 Maciej W. Rozycki <macro@imgtec.com>
953
954 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
955 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
956 "sync_rmb" and "sync_wmb" as aliases.
957 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
958 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
959
53a346d8
CZ		 9602017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
961
962 * arc-dis.c (parse_option): Update quarkse_em option..
963 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
964 QUARKSE1.
965 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
966
f91d48de
KC		 9672017-05-03 Kito Cheng <kito.cheng@gmail.com>
968
969 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
970
43e379d7
MC		 9712017-05-01 Michael Clark <michaeljclark@mac.com>
972
973 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
974 register.
975
a4ddc54e
MR		 9762017-05-02 Maciej W. Rozycki <macro@imgtec.com>
977
978 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
979 and branches and not synthetic data instructions.
980
fe50e98c
BE		 9812017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
982
983 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
984
126124cc
CZ		 9852017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
986
987 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
988 * arc-opc.c (insert_r13el): New function.
989 (R13_EL): Define.
990 * arc-tbl.h: Add new enter/leave variants.
991
be6a24d8
CZ		 9922017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
993
994 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
995
0348fd79
MR		 9962017-04-25 Maciej W. Rozycki <macro@imgtec.com>
997
998 * mips-dis.c (print_mips_disassembler_options): Add
999 `no-aliases'.
1000
6e3d1f07
MR		 10012017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1002
1003 * mips16-opc.c (AL): New macro.
1004 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1005 of "ld" and "lw" as aliases.
1006
957f6b39
TC		 10072017-04-24 Tamar Christina <tamar.christina@arm.com>
1008
1009 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1010 arguments.
1011
a8cc8a54
AM		 10122017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1013 Alan Modra <amodra@gmail.com>
1014
1015 * ppc-opc.c (ELEV): Define.
1016 (vle_opcodes): Add se_rfgi and e_sc.
1017 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1018 for E200Z4.
1019
3ab87b68
JM		 10202017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1021
1022 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1023
792f174f
NC		 10242017-04-21 Nick Clifton <nickc@redhat.com>
1025
1026 PR binutils/21380
1027 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1028 LD3R and LD4R.
1029
42742084
AM		 10302017-04-13 Alan Modra <amodra@gmail.com>
1031
1032 * epiphany-desc.c: Regenerate.
1033 * fr30-desc.c: Regenerate.
1034 * frv-desc.c: Regenerate.
1035 * ip2k-desc.c: Regenerate.
1036 * iq2000-desc.c: Regenerate.
1037 * lm32-desc.c: Regenerate.
1038 * m32c-desc.c: Regenerate.
1039 * m32r-desc.c: Regenerate.
1040 * mep-desc.c: Regenerate.
1041 * mt-desc.c: Regenerate.
1042 * or1k-desc.c: Regenerate.
1043 * xc16x-desc.c: Regenerate.
1044 * xstormy16-desc.c: Regenerate.
1045
9a85b496
AM		 10462017-04-11 Alan Modra <amodra@gmail.com>
1047
ef85eab0 1048 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 1049 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1050 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 1051 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1052 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 1053 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1054 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 1055 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 1056 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 1057
62adc510
AM		 10582017-04-10 Alan Modra <amodra@gmail.com>
1059
1060 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1061 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1062 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1063 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1064
aa808707
PC		 10652017-04-09 Pip Cet <pipcet@gmail.com>
1066
1067 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1068 appropriate floating-point precision directly.
1069
ac8f0f72
AM		 10702017-04-07 Alan Modra <amodra@gmail.com>
1071
1072 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1073 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1074 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1075 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1076 vector instructions with E6500 not PPCVEC2.
1077
62ecb94c
PC		 10782017-04-06 Pip Cet <pipcet@gmail.com>
1079
1080 * Makefile.am: Add wasm32-dis.c.
1081 * configure.ac: Add wasm32-dis.c to wasm32 target.
1082 * disassemble.c: Add wasm32 disassembler code.
1083 * wasm32-dis.c: New file.
1084 * Makefile.in: Regenerate.
1085 * configure: Regenerate.
1086 * po/POTFILES.in: Regenerate.
1087 * po/opcodes.pot: Regenerate.
1088
f995bbe8
PA		 10892017-04-05 Pedro Alves <palves@redhat.com>
1090
1091 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1092 * arm-dis.c (parse_arm_disassembler_options): Constify.
1093 * ppc-dis.c (powerpc_init_dialect): Constify local.
1094 * vax-dis.c (parse_disassembler_options): Constify.
1095
b5292032
PD		 10962017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1097
1098 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1099 RISCV_GP_SYMBOL.
1100
f96bd6c2
PC		 11012017-03-30 Pip Cet <pipcet@gmail.com>
1102
1103 * configure.ac: Add (empty) bfd_wasm32_arch target.
1104 * configure: Regenerate
1105 * po/opcodes.pot: Regenerate.
1106
f7c514a3
JM		 11072017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1108
1109 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1110 OSA2015.
1111 * opcodes/sparc-opc.c (asi_table): New ASIs.
1112
52be03fd
AM		 11132017-03-29 Alan Modra <amodra@gmail.com>
1114
1115 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1116 "raw" option.
1117 (lookup_powerpc): Don't special case -1 dialect. Handle
1118 PPC_OPCODE_RAW.
1119 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1120 lookup_powerpc call, pass it on second.
1121
9b753937
AM		 11222017-03-27 Alan Modra <amodra@gmail.com>
1123
1124 PR 21303
1125 * ppc-dis.c (struct ppc_mopt): Comment.
1126 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1127
c0c31e91
RZ		 11282017-03-27 Rinat Zelig <rinat@mellanox.com>
1129
1130 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1131 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1132 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1133 (insert_nps_misc_imm_offset): New function.
1134 (extract_nps_misc imm_offset): New function.
1135 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1136 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1137
2253c8f0
AK		 11382017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1139
1140 * s390-mkopc.c (main): Remove vx2 check.
1141 * s390-opc.txt: Remove vx2 instruction flags.
1142
645d3342
RZ		 11432017-03-21 Rinat Zelig <rinat@mellanox.com>
1144
1145 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1146 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1147 (insert_nps_imm_offset): New function.
1148 (extract_nps_imm_offset): New function.
1149 (insert_nps_imm_entry): New function.
1150 (extract_nps_imm_entry): New function.
1151
4b94dd2d
AM		 11522017-03-17 Alan Modra <amodra@gmail.com>
1153
1154 PR 21248
1155 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1156 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1157 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1158
b416fe87
KC		 11592017-03-14 Kito Cheng <kito.cheng@gmail.com>
1160
1161 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1162 <c.andi>: Likewise.
1163 <c.addiw> Likewise.
1164
03b039a5
KC		 11652017-03-14 Kito Cheng <kito.cheng@gmail.com>
1166
1167 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1168
2c232b83
AW		 11692017-03-13 Andrew Waterman <andrew@sifive.com>
1170
1171 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1172 <srl> Likewise.
1173 <srai> Likewise.
1174 <sra> Likewise.
1175
86fa6981
L		 11762017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1177
1178 * i386-gen.c (opcode_modifiers): Replace S with Load.
1179 * i386-opc.h (S): Removed.
1180 (Load): New.
1181 (i386_opcode_modifier): Replace s with load.
1182 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1183 and {evex}. Replace S with Load.
1184 * i386-tbl.h: Regenerated.
1185
c1fe188b
L		 11862017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1187
1188 * i386-opc.tbl: Use CpuCET on rdsspq.
1189 * i386-tbl.h: Regenerated.
1190
4b8b687e
PB		 11912017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1192
1193 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1194 <vsx>: Do not use PPC_OPCODE_VSX3;
1195
1437d063
PB		 11962017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1197
1198 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1199
603555e5
L		 12002017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1201
1202 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1203 (MOD_0F1E_PREFIX_1): Likewise.
1204 (MOD_0F38F5_PREFIX_2): Likewise.
1205 (MOD_0F38F6_PREFIX_0): Likewise.
1206 (RM_0F1E_MOD_3_REG_7): Likewise.
1207 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1208 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1209 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1210 (PREFIX_0F1E): Likewise.
1211 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1212 (PREFIX_0F38F5): Likewise.
1213 (dis386_twobyte): Use PREFIX_0F1E.
1214 (reg_table): Add REG_0F1E_MOD_3.
1215 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1216 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1217 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1218 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1219 (three_byte_table): Use PREFIX_0F38F5.
1220 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1221 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1222 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1223 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1224 PREFIX_MOD_3_0F01_REG_5_RM_2.
1225 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1226 (cpu_flags): Add CpuCET.
1227 * i386-opc.h (CpuCET): New enum.
1228 (CpuUnused): Commented out.
1229 (i386_cpu_flags): Add cpucet.
1230 * i386-opc.tbl: Add Intel CET instructions.
1231 * i386-init.h: Regenerated.
1232 * i386-tbl.h: Likewise.
1233
73f07bff
AM		 12342017-03-06 Alan Modra <amodra@gmail.com>
1235
1236 PR 21124
1237 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1238 (extract_raq, extract_ras, extract_rbx): New functions.
1239 (powerpc_operands): Use opposite corresponding insert function.
1240 (Q_MASK): Define.
1241 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1242 register restriction.
1243
65b48a81
PB		 12442017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1245
1246 * disassemble.c Include "safe-ctype.h".
1247 (disassemble_init_for_target): Handle s390 init.
1248 (remove_whitespace_and_extra_commas): New function.
1249 (disassembler_options_cmp): Likewise.
1250 * arm-dis.c: Include "libiberty.h".
1251 (NUM_ELEM): Delete.
1252 (regnames): Use long disassembler style names.
1253 Add force-thumb and no-force-thumb options.
1254 (NUM_ARM_REGNAMES): Rename from this...
1255 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1256 (get_arm_regname_num_options): Delete.
1257 (set_arm_regname_option): Likewise.
1258 (get_arm_regnames): Likewise.
1259 (parse_disassembler_options): Likewise.
1260 (parse_arm_disassembler_option): Rename from this...
1261 (parse_arm_disassembler_options): ...to this. Make static.
1262 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1263 (print_insn): Use parse_arm_disassembler_options.
1264 (disassembler_options_arm): New function.
1265 (print_arm_disassembler_options): Handle updated regnames.
1266 * ppc-dis.c: Include "libiberty.h".
1267 (ppc_opts): Add "32" and "64" entries.
1268 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1269 (powerpc_init_dialect): Add break to switch statement.
1270 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1271 (disassembler_options_powerpc): New function.
1272 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1273 Remove printing of "32" and "64".
1274 * s390-dis.c: Include "libiberty.h".
1275 (init_flag): Remove unneeded variable.
1276 (struct s390_options_t): New structure type.
1277 (options): New structure.
1278 (init_disasm): Rename from this...
1279 (disassemble_init_s390): ...to this. Add initializations for
1280 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1281 (print_insn_s390): Delete call to init_disasm.
1282 (disassembler_options_s390): New function.
1283 (print_s390_disassembler_options): Print using information from
1284 struct 'options'.
1285 * po/opcodes.pot: Regenerate.
1286
15c7c1d8
JB		 12872017-02-28 Jan Beulich <jbeulich@suse.com>
1288
1289 * i386-dis.c (PCMPESTR_Fixup): New.
1290 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1291 (prefix_table): Use PCMPESTR_Fixup.
1292 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1293 PCMPESTR_Fixup.
1294 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1295 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1296 Split 64-bit and non-64-bit variants.
1297 * opcodes/i386-tbl.h: Re-generate.
1298
582e12bf
RS		 12992017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1300
1301 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1302 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1303 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1304 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1305 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1306 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1307 (OP_SVE_V_HSD): New macros.
1308 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1309 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1310 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1311 (aarch64_opcode_table): Add new SVE instructions.
1312 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1313 for rotation operands. Add new SVE operands.
1314 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1315 (ins_sve_quad_index): Likewise.
1316 (ins_imm_rotate): Split into...
1317 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1318 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1319 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1320 functions.
1321 (aarch64_ins_sve_addr_ri_s4): New function.
1322 (aarch64_ins_sve_quad_index): Likewise.
1323 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1324 * aarch64-asm-2.c: Regenerate.
1325 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1326 (ext_sve_quad_index): Likewise.
1327 (ext_imm_rotate): Split into...
1328 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1329 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1330 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1331 functions.
1332 (aarch64_ext_sve_addr_ri_s4): New function.
1333 (aarch64_ext_sve_quad_index): Likewise.
1334 (aarch64_ext_sve_index): Allow quad indices.
1335 (do_misc_decoding): Likewise.
1336 * aarch64-dis-2.c: Regenerate.
1337 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1338 aarch64_field_kinds.
1339 (OPD_F_OD_MASK): Widen by one bit.
1340 (OPD_F_NO_ZR): Bump accordingly.
1341 (get_operand_field_width): New function.
1342 * aarch64-opc.c (fields): Add new SVE fields.
1343 (operand_general_constraint_met_p): Handle new SVE operands.
1344 (aarch64_print_operand): Likewise.
1345 * aarch64-opc-2.c: Regenerate.
1346
f482d304
RS		 13472017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1348
1349 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1350 (aarch64_feature_compnum): ...this.
1351 (SIMD_V8_3): Replace with...
1352 (COMPNUM): ...this.
1353 (CNUM_INSN): New macro.
1354 (aarch64_opcode_table): Use it for the complex number instructions.
1355
7db2c588
JB		 13562017-02-24 Jan Beulich <jbeulich@suse.com>
1357
1358 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1359
1e9d41d4
SL		 13602017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1361
1362 Add support for associating SPARC ASIs with an architecture level.
1363 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1364 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1365 decoding of SPARC ASIs.
1366
53c4d625
JB		 13672017-02-23 Jan Beulich <jbeulich@suse.com>
1368
1369 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1370 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1371
11648de5
JB		 13722017-02-21 Jan Beulich <jbeulich@suse.com>
1373
1374 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1375 1 (instead of to itself). Correct typo.
1376
f98d33be
AW		 13772017-02-14 Andrew Waterman <andrew@sifive.com>
1378
1379 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1380 pseudoinstructions.
1381
773fb663
RS		 13822017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1383
1384 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1385 (aarch64_sys_reg_supported_p): Handle them.
1386
cc07cda6
CZ		 13872017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1388
1389 * arc-opc.c (UIMM6_20R): Define.
1390 (SIMM12_20): Use above.
1391 (SIMM12_20R): Define.
1392 (SIMM3_5_S): Use above.
1393 (UIMM7_A32_11R_S): Define.
1394 (UIMM7_9_S): Use above.
1395 (UIMM3_13R_S): Define.
1396 (SIMM11_A32_7_S): Use above.
1397 (SIMM9_8R): Define.
1398 (UIMM10_A32_8_S): Use above.
1399 (UIMM8_8R_S): Define.
1400 (W6): Use above.
1401 (arc_relax_opcodes): Use all above defines.
1402
66a5a740
VG		 14032017-02-15 Vineet Gupta <vgupta@synopsys.com>
1404
1405 * arc-regs.h: Distinguish some of the registers different on
1406 ARC700 and HS38 cpus.
1407
7e0de605
AM		 14082017-02-14 Alan Modra <amodra@gmail.com>
1409
1410 PR 21118
1411 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1412 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1413
54064fdb
AM		 14142017-02-11 Stafford Horne <shorne@gmail.com>
1415 Alan Modra <amodra@gmail.com>
1416
1417 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1418 Use insn_bytes_value and insn_int_value directly instead. Don't
1419 free allocated memory until function exit.
1420
dce75bf9
NP		 14212017-02-10 Nicholas Piggin <npiggin@gmail.com>
1422
1423 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1424
1b7e3d2f
NC		 14252017-02-03 Nick Clifton <nickc@redhat.com>
1426
1427 PR 21096
1428 * aarch64-opc.c (print_register_list): Ensure that the register
1429 list index will fir into the tb buffer.
1430 (print_register_offset_address): Likewise.
1431 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1432
8ec5cf65
AD		 14332017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1434
1435 PR 21056
1436 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1437 instructions when the previous fetch packet ends with a 32-bit
1438 instruction.
1439
a1aa5e81
DD		 14402017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1441
1442 * pru-opc.c: Remove vague reference to a future GDB port.
1443
add3afb2
NC		 14442017-01-20 Nick Clifton <nickc@redhat.com>
1445
1446 * po/ga.po: Updated Irish translation.
1447
c13a63b0
SN		 14482017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1449
1450 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1451
9608051a
YQ		 14522017-01-13 Yao Qi <yao.qi@linaro.org>
1453
1454 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1455 if FETCH_DATA returns 0.
1456 (m68k_scan_mask): Likewise.
1457 (print_insn_m68k): Update code to handle -1 return value.
1458
f622ea96
YQ		 14592017-01-13 Yao Qi <yao.qi@linaro.org>
1460
1461 * m68k-dis.c (enum print_insn_arg_error): New.
1462 (NEXTBYTE): Replace -3 with
1463 PRINT_INSN_ARG_MEMORY_ERROR.
1464 (NEXTULONG): Likewise.
1465 (NEXTSINGLE): Likewise.
1466 (NEXTDOUBLE): Likewise.
1467 (NEXTDOUBLE): Likewise.
1468 (NEXTPACKED): Likewise.
1469 (FETCH_ARG): Likewise.
1470 (FETCH_DATA): Update comments.
1471 (print_insn_arg): Update comments. Replace magic numbers with
1472 enum.
1473 (match_insn_m68k): Likewise.
1474
620214f7
IT		 14752017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1476
1477 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1478 * i386-dis-evex.h (evex_table): Updated.
1479 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1480 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1481 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1482 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1483 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1484 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1485 * i386-init.h: Regenerate.
1486 * i386-tbl.h: Ditto.
1487
d95014a2
YQ		 14882017-01-12 Yao Qi <yao.qi@linaro.org>
1489
1490 * msp430-dis.c (msp430_singleoperand): Return -1 if
1491 msp430dis_opcode_signed returns false.
1492 (msp430_doubleoperand): Likewise.
1493 (msp430_branchinstr): Return -1 if
1494 msp430dis_opcode_unsigned returns false.
1495 (msp430x_calla_instr): Likewise.
1496 (print_insn_msp430): Likewise.
1497
0ae60c3e
NC		 14982017-01-05 Nick Clifton <nickc@redhat.com>
1499
1500 PR 20946
1501 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1502 could not be matched.
1503 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1504 NULL.
1505
d74d4880
SN		 15062017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1507
1508 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1509 (aarch64_opcode_table): Use RCPC_INSN.
1510
cc917fd9
KC		 15112017-01-03 Kito Cheng <kito.cheng@gmail.com>
1512
1513 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1514 extension.
1515 * riscv-opcodes/all-opcodes: Likewise.
1516
b52d3cfc
DP		 15172017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1518
1519 * riscv-dis.c (print_insn_args): Add fall through comment.
1520
f90c58d5
NC		 15212017-01-03 Nick Clifton <nickc@redhat.com>
1522
1523 * po/sr.po: New Serbian translation.
1524 * configure.ac (ALL_LINGUAS): Add sr.
1525 * configure: Regenerate.
1526
f47b0d4a
AM		 15272017-01-02 Alan Modra <amodra@gmail.com>
1528
1529 * epiphany-desc.h: Regenerate.
1530 * epiphany-opc.h: Regenerate.
1531 * fr30-desc.h: Regenerate.
1532 * fr30-opc.h: Regenerate.
1533 * frv-desc.h: Regenerate.
1534 * frv-opc.h: Regenerate.
1535 * ip2k-desc.h: Regenerate.
1536 * ip2k-opc.h: Regenerate.
1537 * iq2000-desc.h: Regenerate.
1538 * iq2000-opc.h: Regenerate.
1539 * lm32-desc.h: Regenerate.
1540 * lm32-opc.h: Regenerate.
1541 * m32c-desc.h: Regenerate.
1542 * m32c-opc.h: Regenerate.
1543 * m32r-desc.h: Regenerate.
1544 * m32r-opc.h: Regenerate.
1545 * mep-desc.h: Regenerate.
1546 * mep-opc.h: Regenerate.
1547 * mt-desc.h: Regenerate.
1548 * mt-opc.h: Regenerate.
1549 * or1k-desc.h: Regenerate.
1550 * or1k-opc.h: Regenerate.
1551 * xc16x-desc.h: Regenerate.
1552 * xc16x-opc.h: Regenerate.
1553 * xstormy16-desc.h: Regenerate.
1554 * xstormy16-opc.h: Regenerate.
1555
2571583a
AM		 15562017-01-02 Alan Modra <amodra@gmail.com>
1557
1558 Update year range in copyright notice of all files.
1559
5c1ad6b5 1560For older changes see ChangeLog-2016
3499769a 1561\f
5c1ad6b5 1562Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1563
1564Copying and distribution of this file, with or without modification,
1565are permitted in any medium without royalty provided the copyright
1566notice and this notice are preserved.
1567
1568Local Variables:
1569mode: change-log
1570left-margin: 8
1571fill-column: 74
1572version-control: never
1573End:
GDB Binutils - Deliverables
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