projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* cli/cli-decode.c (lookup_cmd_1): Use memcpy.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
30c09090
RS		 12008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
4
c27e721e
AN		 52008-07-07 Adam Nemet <anemet@caviumnetworks.com>
6
7 * mips-opc.c (CP): New macro.
8 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
9 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
10 dmtc2 Octeon instructions.
11
bd2e2557
SS		 122008-07-07 Stan Shebs <stan@codesourcery.com>
13
14 * dis-init.c (init_disassemble_info): Init endian_code field.
15 * arm-dis.c (print_insn): Disassemble code according to
16 setting of endian_code.
17 (print_insn_big_arm): Detect when BE8 extension flag has been set.
18
6ba2a415
RS		 192008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
20
21 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
22 for ELF symbols.
23
c8187e15
PB		 242008-06-25 Peter Bergner <bergner@vnet.ibm.com>
25
26 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
27 (print_ppc_disassembler_options): Likewise.
28 * ppc-opc.c (PPC464): Define.
29 (powerpc_opcodes): Add mfdcrux and mtdcrux.
30
7a283e07
RW		 312008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
32
33 * configure: Regenerate.
34
fa452fa6
PB		 352008-06-13 Peter Bergner <bergner@vnet.ibm.com>
36
37 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
38 ppc_cpu_t typedef.
39 (struct dis_private): New.
40 (POWERPC_DIALECT): New define.
41 (powerpc_dialect): Renamed to...
42 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
43 struct dis_private.
44 (print_insn_big_powerpc): Update for using structure in
45 info->private_data.
46 (print_insn_little_powerpc): Likewise.
47 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
48 (skip_optional_operands): Likewise.
49 (print_insn_powerpc): Likewise. Remove initialization of dialect.
50 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
51 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
52 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
53 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
54 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
55 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
56 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
57 param to be of type ppc_cpu_t. Update prototype.
58
bb35fb24
NC		 592008-06-12 Adam Nemet <anemet@caviumnetworks.com>
60
61 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
62 +s, +S.
63 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
64 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
65 syncw, syncws, vm3mulu, vm0 and vmulu.
66
dd3cbb7e
NC		 67 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
68 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
69 seqi, sne and snei.
70
a5dabbb0
L		 712008-05-30 H.J. Lu <hongjiu.lu@intel.com>
72
73 * i386-opc.tbl: Add vmovd with 64bit operand.
74 * i386-tbl.h: Regenerated.
75
725a9891
MS		 762008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
77
78 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
79
cbc80391
L		 802008-05-22 H.J. Lu <hongjiu.lu@intel.com>
81
82 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
83 * i386-tbl.h: Regenerated.
84
116615c5
L		 852008-05-22 H.J. Lu <hongjiu.lu@intel.com>
86
87 PR gas/6517
88 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
89 into 32bit and 64bit. Remove Reg64|Qword and add
90 IgnoreSize|No_qSuf on 32bit version.
91 * i386-tbl.h: Regenerated.
92
d9479f2d
L		 932008-05-21 H.J. Lu <hongjiu.lu@intel.com>
94
95 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
96 * i386-tbl.h: Regenerated.
97
3ce6fddb
NC		 982008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
99
100 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
101
8944f3c2
AM		 1022008-05-14 Alan Modra <amodra@bigpond.net.au>
103
104 * Makefile.am: Run "make dep-am".
105 * Makefile.in: Regenerate.
106
f1f8f695
L		 1072008-05-02 H.J. Lu <hongjiu.lu@intel.com>
108
109 * i386-dis.c (MOVBE_Fixup): New.
110 (Mo): Likewise.
111 (PREFIX_0F3880): Likewise.
112 (PREFIX_0F3881): Likewise.
113 (PREFIX_0F38F0): Updated.
114 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
115 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
116 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
117
118 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
119 CPU_EPT_FLAGS.
120 (cpu_flags): Add CpuMovbe and CpuEPT.
121
122 * i386-opc.h (CpuMovbe): New.
123 (CpuEPT): Likewise.
124 (CpuLM): Updated.
125 (i386_cpu_flags): Add cpumovbe and cpuept.
126
127 * i386-opc.tbl: Add entries for movbe and EPT instructions.
128 * i386-init.h: Regenerated.
129 * i386-tbl.h: Likewise.
130
89aa3097
AN		 1312008-04-29 Adam Nemet <anemet@caviumnetworks.com>
132
133 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
134 the two drem and the two dremu macros.
135
39c5c168
AN		 1362008-04-28 Adam Nemet <anemet@caviumnetworks.com>
137
138 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
139 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
140 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
141 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
142
f04d18b7
DM		 1432008-04-25 David S. Miller <davem@davemloft.net>
144
145 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
146 instead of %sys_tick_cmpr, as suggested in architecture manuals.
147
6194aaab
L		 1482008-04-23 Paolo Bonzini <bonzini@gnu.org>
149
150 * aclocal.m4: Regenerate.
151 * configure: Regenerate.
152
1a6b486f
DM		 1532008-04-23 David S. Miller <davem@davemloft.net>
154
155 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
156 extended values.
157 (prefetch_table): Add missing values.
158
81f8a913
L		 1592008-04-22 H.J. Lu <hongjiu.lu@intel.com>
160
161 * i386-gen.c (opcode_modifiers): Add NoAVX.
162
163 * i386-opc.h (NoAVX): New.
164 (OldGcc): Updated.
165 (i386_opcode_modifier): Add noavx.
166
167 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
168 instructions which don't have AVX equivalent.
169 * i386-tbl.h: Regenerated.
170
dae39acc
L		 1712008-04-18 H.J. Lu <hongjiu.lu@intel.com>
172
173 * i386-dis.c (OP_VEX_FMA): New.
174 (OP_EX_VexImmW): Likewise.
175 (VexFMA): Likewise.
176 (Vex128FMA): Likewise.
177 (EXVexImmW): Likewise.
178 (get_vex_imm8): Likewise.
179 (OP_EX_VexReg): Likewise.
180 (vex_i4_done): Renamed to ...
181 (vex_w_done): This.
182 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
183 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
184 FMA instructions.
185 (print_insn): Updated.
186 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
187 (OP_REG_VexI4): Check invalid high registers.
188
ce886ab1
DR		 1892008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
190 Michael Meissner <michael.meissner@amd.com>
191
192 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
193 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 194
19a6653c
AM		 1952008-04-14 Edmar Wienskoski <edmar@freescale.com>
196
197 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
198 accept Power E500MC instructions.
199 (print_ppc_disassembler_options): Document -Me500mc.
200 * ppc-opc.c (DUIS, DUI, T): New.
201 (XRT, XRTRA): Likewise.
202 (E500MC): Likewise.
203 (powerpc_opcodes): Add new Power E500MC instructions.
204
112b7c50
AK		 2052008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
206
207 * s390-dis.c (init_disasm): Evaluate disassembler_options.
208 (print_s390_disassembler_options): New function.
209 * disassemble.c (disassembler_usage): Invoke
210 print_s390_disassembler_options.
211
7ff42648
AK		 2122008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
213
214 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
215 of local variables used for mnemonic parsing: prefix, suffix and
216 number.
217
45a5551e
AK		 2182008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
219
220 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
221 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
222 (s390_crb_extensions): New extensions table.
223 (insertExpandedMnemonic): Handle '$' tag.
224 * s390-opc.txt: Remove conditional jump variants which can now
225 be expanded automatically.
226 Replace '*' tag with '$' in the compare and branch instructions.
227
06c8514a
L		 2282008-04-07 H.J. Lu <hongjiu.lu@intel.com>
229
230 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
231 (PREFIX_VEX_3AXX): Likewis.
232
b122c285
L		 2332008-04-07 H.J. Lu <hongjiu.lu@intel.com>
234
235 * i386-opc.tbl: Remove 4 extra blank lines.
236
594ab6a3
L		 2372008-04-04 H.J. Lu <hongjiu.lu@intel.com>
238
239 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
240 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
241 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
242 * i386-opc.tbl: Likewise.
243
244 * i386-opc.h (CpuCLMUL): Renamed to ...
245 (CpuPCLMUL): This.
246 (CpuFMA): Updated.
247 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
248
249 * i386-init.h: Regenerated.
250
c0f3af97
L		 2512008-04-03 H.J. Lu <hongjiu.lu@intel.com>
252
253 * i386-dis.c (OP_E_register): New.
254 (OP_E_memory): Likewise.
255 (OP_VEX): Likewise.
256 (OP_EX_Vex): Likewise.
257 (OP_EX_VexW): Likewise.
258 (OP_XMM_Vex): Likewise.
259 (OP_XMM_VexW): Likewise.
260 (OP_REG_VexI4): Likewise.
261 (PCLMUL_Fixup): Likewise.
262 (VEXI4_Fixup): Likewise.
263 (VZERO_Fixup): Likewise.
264 (VCMP_Fixup): Likewise.
265 (VPERMIL2_Fixup): Likewise.
266 (rex_original): Likewise.
267 (rex_ignored): Likewise.
268 (Mxmm): Likewise.
269 (XMM): Likewise.
270 (EXxmm): Likewise.
271 (EXxmmq): Likewise.
272 (EXymmq): Likewise.
273 (Vex): Likewise.
274 (Vex128): Likewise.
275 (Vex256): Likewise.
276 (VexI4): Likewise.
277 (EXdVex): Likewise.
278 (EXqVex): Likewise.
279 (EXVexW): Likewise.
280 (EXdVexW): Likewise.
281 (EXqVexW): Likewise.
282 (XMVex): Likewise.
283 (XMVexW): Likewise.
284 (XMVexI4): Likewise.
285 (PCLMUL): Likewise.
286 (VZERO): Likewise.
287 (VCMP): Likewise.
288 (VPERMIL2): Likewise.
289 (xmm_mode): Likewise.
290 (xmmq_mode): Likewise.
291 (ymmq_mode): Likewise.
292 (vex_mode): Likewise.
293 (vex128_mode): Likewise.
294 (vex256_mode): Likewise.
295 (USE_VEX_C4_TABLE): Likewise.
296 (USE_VEX_C5_TABLE): Likewise.
297 (USE_VEX_LEN_TABLE): Likewise.
298 (VEX_C4_TABLE): Likewise.
299 (VEX_C5_TABLE): Likewise.
300 (VEX_LEN_TABLE): Likewise.
301 (REG_VEX_XX): Likewise.
302 (MOD_VEX_XXX): Likewise.
303 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
304 (PREFIX_0F3A44): Likewise.
305 (PREFIX_0F3ADF): Likewise.
306 (PREFIX_VEX_XXX): Likewise.
307 (VEX_OF): Likewise.
308 (VEX_OF38): Likewise.
309 (VEX_OF3A): Likewise.
310 (VEX_LEN_XXX): Likewise.
311 (vex): Likewise.
312 (need_vex): Likewise.
313 (need_vex_reg): Likewise.
314 (vex_i4_done): Likewise.
315 (vex_table): Likewise.
316 (vex_len_table): Likewise.
317 (OP_REG_VexI4): Likewise.
318 (vex_cmp_op): Likewise.
319 (pclmul_op): Likewise.
320 (vpermil2_op): Likewise.
321 (m_mode): Updated.
322 (es_reg): Likewise.
323 (PREFIX_0F38F0): Likewise.
324 (PREFIX_0F3A60): Likewise.
325 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
326 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
327 and PREFIX_VEX_XXX entries.
328 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
329 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
330 PREFIX_0F3ADF.
331 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
332 Add MOD_VEX_XXX entries.
333 (ckprefix): Initialize rex_original and rex_ignored. Store the
334 REX byte in rex_original.
335 (get_valid_dis386): Handle the implicit prefix in VEX prefix
336 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
337 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
338 calling get_valid_dis386. Use rex_original and rex_ignored when
339 printing out REX.
340 (putop): Handle "XY".
341 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
342 ymmq_mode.
343 (OP_E_extended): Updated to use OP_E_register and
344 OP_E_memory.
345 (OP_XMM): Handle VEX.
346 (OP_EX): Likewise.
347 (XMM_Fixup): Likewise.
348 (CMP_Fixup): Use ARRAY_SIZE.
349
350 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
351 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
352 (operand_type_init): Add OPERAND_TYPE_REGYMM and
353 OPERAND_TYPE_VEX_IMM4.
354 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
355 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
356 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
357 VexImmExt and SSE2AVX.
358 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
359
360 * i386-opc.h (CpuAVX): New.
361 (CpuAES): Likewise.
362 (CpuCLMUL): Likewise.
363 (CpuFMA): Likewise.
364 (Vex): Likewise.
365 (Vex256): Likewise.
366 (VexNDS): Likewise.
367 (VexNDD): Likewise.
368 (VexW0): Likewise.
369 (VexW1): Likewise.
370 (Vex0F): Likewise.
371 (Vex0F38): Likewise.
372 (Vex0F3A): Likewise.
373 (Vex3Sources): Likewise.
374 (VexImmExt): Likewise.
375 (SSE2AVX): Likewise.
376 (RegYMM): Likewise.
377 (Ymmword): Likewise.
378 (Vex_Imm4): Likewise.
379 (Implicit1stXmm0): Likewise.
380 (CpuXsave): Updated.
381 (CpuLM): Likewise.
382 (ByteOkIntel): Likewise.
383 (OldGcc): Likewise.
384 (Control): Likewise.
385 (Unspecified): Likewise.
386 (OTMax): Likewise.
387 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
388 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
389 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
390 vex3sources, veximmext and sse2avx.
391 (i386_operand_type): Add regymm, ymmword and vex_imm4.
392
393 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
394
395 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
396
397 * i386-init.h: Regenerated.
398 * i386-tbl.h: Likewise.
399
b21c9cb4
BS		 4002008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
401
402 From Robin Getz <robin.getz@analog.com>
403 * bfin-dis.c (bu32): Typedef.
404 (enum const_forms_t): Add c_uimm32 and c_huimm32.
405 (constant_formats[]): Add uimm32 and huimm16.
406 (fmtconst_val): New.
407 (uimm32): Define.
408 (huimm32): Define.
409 (imm16_val): Define.
410 (luimm16_val): Define.
411 (struct saved_state): Define.
412 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
413 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
414 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
415 (get_allreg): New.
416 (decode_LDIMMhalf_0): Print out the whole register value.
417
ee171c8f
BS		 418 From Jie Zhang <jie.zhang@analog.com>
419 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
420 multiply and multiply-accumulate to data register instruction.
421
086134ec
BS		 422 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
423 c_imm32, c_huimm32e): Define.
424 (constant_formats): Add flags for printing decimal, leading spaces, and
425 exact symbols.
426 (comment, parallel): Add global flags in all disassembly.
427 (fmtconst): Take advantage of new flags, and print default in hex.
428 (fmtconst_val): Likewise.
429 (decode_macfunc): Be consistant with spaces, tabs, comments,
430 capitalization in disassembly, fix minor coding style issues.
431 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
432 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
433 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
434 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
435 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
436 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
437 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
438 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
439 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
440 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
441 _print_insn_bfin, print_insn_bfin): Likewise.
442
58c85be7
RW		 4432008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
444
445 * aclocal.m4: Regenerate.
446 * configure: Likewise.
447 * Makefile.in: Likewise.
448
50e7d84b
AM		 4492008-03-13 Alan Modra <amodra@bigpond.net.au>
450
451 * Makefile.am: Run "make dep-am".
452 * Makefile.in: Regenerate.
453 * configure: Regenerate.
454
de866fcc
AM		 4552008-03-07 Alan Modra <amodra@bigpond.net.au>
456
457 * ppc-opc.c (powerpc_opcodes): Order and format.
458
28dbc079
L		 4592008-03-01 H.J. Lu <hongjiu.lu@intel.com>
460
461 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
462 * i386-tbl.h: Regenerated.
463
849830bd
L		 4642008-02-23 H.J. Lu <hongjiu.lu@intel.com>
465
466 * i386-opc.tbl: Disallow 16-bit near indirect branches for
467 x86-64.
468 * i386-tbl.h: Regenerated.
469
743ddb6b
JB		 4702008-02-21 Jan Beulich <jbeulich@novell.com>
471
472 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
473 and Fword for far indirect jmp. Allow Reg16 and Word for near
474 indirect jmp on x86-64. Disallow Fword for lcall.
475 * i386-tbl.h: Re-generate.
476
796d5313
NC		 4772008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
478
479 * cr16-opc.c (cr16_num_optab): Defined
480
65da13b5
L		 4812008-02-16 H.J. Lu <hongjiu.lu@intel.com>
482
483 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
484 * i386-init.h: Regenerated.
485
0e336180
NC		 4862008-02-14 Nick Clifton <nickc@redhat.com>
487
488 PR binutils/5524
489 * configure.in (SHARED_LIBADD): Select the correct host specific
490 file extension for shared libraries.
491 * configure: Regenerate.
492
b7240065
JB		 4932008-02-13 Jan Beulich <jbeulich@novell.com>
494
495 * i386-opc.h (RegFlat): New.
496 * i386-reg.tbl (flat): Add.
497 * i386-tbl.h: Re-generate.
498
34b772a6
JB		 4992008-02-13 Jan Beulich <jbeulich@novell.com>
500
501 * i386-dis.c (a_mode): New.
502 (cond_jump_mode): Adjust.
503 (Ma): Change to a_mode.
504 (intel_operand_size): Handle a_mode.
505 * i386-opc.tbl: Allow Dword and Qword for bound.
506 * i386-tbl.h: Re-generate.
507
a60de03c
JB		 5082008-02-13 Jan Beulich <jbeulich@novell.com>
509
510 * i386-gen.c (process_i386_registers): Process new fields.
511 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
512 unsigned char. Add dw2_regnum and Dw2Inval.
513 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
514 register names.
515 * i386-tbl.h: Re-generate.
516
f03fe4c1
L		 5172008-02-11 H.J. Lu <hongjiu.lu@intel.com>
518
4b6bc8eb 519 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 520 * i386-init.h: Updated.
521
475a2301
L		 5222008-02-11 H.J. Lu <hongjiu.lu@intel.com>
523
524 * i386-gen.c (cpu_flags): Add CpuXsave.
525
526 * i386-opc.h (CpuXsave): New.
4b6bc8eb 527 (CpuLM): Updated.
475a2301
L		 528 (i386_cpu_flags): Add cpuxsave.
529
530 * i386-dis.c (MOD_0FAE_REG_4): New.
531 (RM_0F01_REG_2): Likewise.
532 (MOD_0FAE_REG_5): Updated.
533 (RM_0F01_REG_3): Likewise.
534 (reg_table): Use MOD_0FAE_REG_4.
535 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
536 for xrstor.
537 (rm_table): Add RM_0F01_REG_2.
538
539 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
540 * i386-init.h: Regenerated.
541 * i386-tbl.h: Likewise.
542
595785c6 5432008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 544
595785c6
JB		 545 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
546 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
547 * i386-tbl.h: Re-generate.
548
bb8541b9
L		 5492008-02-04 H.J. Lu <hongjiu.lu@intel.com>
550
551 PR 5715
552 * configure: Regenerated.
553
57b592a3
AN		 5542008-02-04 Adam Nemet <anemet@caviumnetworks.com>
555
556 * mips-dis.c: Update copyright.
557 (mips_arch_choices): Add Octeon.
558 * mips-opc.c: Update copyright.
559 (IOCT): New macro.
560 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
561
930bb4cf
AM		 5622008-01-29 Alan Modra <amodra@bigpond.net.au>
563
564 * ppc-opc.c: Support optional L form mtmsr.
565
82c18208
L		 5662008-01-24 H.J. Lu <hongjiu.lu@intel.com>
567
568 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
569
599121aa
L		 5702008-01-23 H.J. Lu <hongjiu.lu@intel.com>
571
572 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
573 * i386-init.h: Regenerated.
574
80098f51
TG		 5752008-01-23 Tristan Gingold <gingold@adacore.com>
576
577 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
578 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
579
115c7c25
L		 5802008-01-22 H.J. Lu <hongjiu.lu@intel.com>
581
582 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
583 (cpu_flags): Likewise.
584
585 * i386-opc.h (CpuMMX2): Removed.
586 (CpuSSE): Updated.
587
588 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
589 * i386-init.h: Regenerated.
590 * i386-tbl.h: Likewise.
591
6305a203
L		 5922008-01-22 H.J. Lu <hongjiu.lu@intel.com>
593
594 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
595 CPU_SMX_FLAGS.
596 * i386-init.h: Regenerated.
597
fd07a1c8
L		 5982008-01-15 H.J. Lu <hongjiu.lu@intel.com>
599
600 * i386-opc.tbl: Use Qword on movddup.
601 * i386-tbl.h: Regenerated.
602
321fd21e
L		 6032008-01-15 H.J. Lu <hongjiu.lu@intel.com>
604
605 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
606 * i386-tbl.h: Regenerated.
607
4ee52178
L		 6082008-01-15 H.J. Lu <hongjiu.lu@intel.com>
609
610 * i386-dis.c (Mx): New.
611 (PREFIX_0FC3): Likewise.
612 (PREFIX_0FC7_REG_6): Updated.
613 (dis386_twobyte): Use PREFIX_0FC3.
614 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
615 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
616 movntss.
617
5c07affc
L		 6182008-01-14 H.J. Lu <hongjiu.lu@intel.com>
619
620 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
621 (operand_types): Add Mem.
622
623 * i386-opc.h (IntelSyntax): New.
624 * i386-opc.h (Mem): New.
625 (Byte): Updated.
626 (Opcode_Modifier_Max): Updated.
627 (i386_opcode_modifier): Add intelsyntax.
628 (i386_operand_type): Add mem.
629
630 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
631 instructions.
632
633 * i386-reg.tbl: Add size for accumulator.
634
635 * i386-init.h: Regenerated.
636 * i386-tbl.h: Likewise.
637
0d6a2f58
L		 6382008-01-13 H.J. Lu <hongjiu.lu@intel.com>
639
640 * i386-opc.h (Byte): Fix a typo.
641
7d5e4556
L		 6422008-01-12 H.J. Lu <hongjiu.lu@intel.com>
643
644 PR gas/5534
645 * i386-gen.c (operand_type_init): Add Dword to
646 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
647 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
648 Qword and Xmmword.
649 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
650 Xmmword, Unspecified and Anysize.
651 (set_bitfield): Make Mmword an alias of Qword. Make Oword
652 an alias of Xmmword.
653
654 * i386-opc.h (CheckSize): Removed.
655 (Byte): Updated.
656 (Word): Likewise.
657 (Dword): Likewise.
658 (Qword): Likewise.
659 (Xmmword): Likewise.
660 (FWait): Updated.
661 (OTMax): Likewise.
662 (i386_opcode_modifier): Remove checksize, byte, word, dword,
663 qword and xmmword.
664 (Fword): New.
665 (TBYTE): Likewise.
666 (Unspecified): Likewise.
667 (Anysize): Likewise.
668 (i386_operand_type): Add byte, word, dword, fword, qword,
669 tbyte xmmword, unspecified and anysize.
670
671 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
672 Tbyte, Xmmword, Unspecified and Anysize.
673
674 * i386-reg.tbl: Add size for accumulator.
675
676 * i386-init.h: Regenerated.
677 * i386-tbl.h: Likewise.
678
b5b1fc4f
L		 6792008-01-10 H.J. Lu <hongjiu.lu@intel.com>
680
681 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
682 (REG_0F18): Updated.
683 (reg_table): Updated.
684 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
685 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
686
50e8458f
L		 6872008-01-08 H.J. Lu <hongjiu.lu@intel.com>
688
689 * i386-gen.c (set_bitfield): Use fail () on error.
690
3d4d5afa
L		 6912008-01-08 H.J. Lu <hongjiu.lu@intel.com>
692
693 * i386-gen.c (lineno): New.
694 (filename): Likewise.
695 (set_bitfield): Report filename and line numer on error.
696 (process_i386_opcodes): Set filename and update lineno.
697 (process_i386_registers): Likewise.
698
e1d4d893
L		 6992008-01-05 H.J. Lu <hongjiu.lu@intel.com>
700
701 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
702 ATTSyntax.
703
704 * i386-opc.h (IntelMnemonic): Renamed to ..
705 (ATTSyntax): This
706 (Opcode_Modifier_Max): Updated.
707 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
708 and intelsyntax.
709
8944f3c2 710 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 711 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
712 * i386-tbl.h: Regenerated.
713
6f143e4d
L		 7142008-01-04 H.J. Lu <hongjiu.lu@intel.com>
715
716 * i386-gen.c: Update copyright to 2008.
717 * i386-opc.h: Likewise.
718 * i386-opc.tbl: Likewise.
719
720 * i386-init.h: Regenerated.
721 * i386-tbl.h: Likewise.
722
c6add537
L		 7232008-01-04 H.J. Lu <hongjiu.lu@intel.com>
724
725 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
726 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
727 * i386-tbl.h: Regenerated.
728
3629bb00
L		 7292008-01-03 H.J. Lu <hongjiu.lu@intel.com>
730
731 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
732 CpuSSE4_2_Or_ABM.
733 (cpu_flags): Likewise.
734
735 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
736 (CpuSSE4_2_Or_ABM): Likewise.
737 (CpuLM): Updated.
738 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
739
740 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
741 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
742 and CpuPadLock, respectively.
743 * i386-init.h: Regenerated.
744 * i386-tbl.h: Likewise.
745
24995bd6
L		 7462008-01-03 H.J. Lu <hongjiu.lu@intel.com>
747
748 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
749
750 * i386-opc.h (No_xSuf): Removed.
751 (CheckSize): Updated.
752
753 * i386-tbl.h: Regenerated.
754
e0329a22
L		 7552008-01-02 H.J. Lu <hongjiu.lu@intel.com>
756
757 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
758 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
759 CPU_SSE5_FLAGS.
760 (cpu_flags): Add CpuSSE4_2_Or_ABM.
761
762 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
763 (CpuLM): Updated.
764 (i386_cpu_flags): Add cpusse4_2_or_abm.
765
766 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
767 CpuABM|CpuSSE4_2 on popcnt.
768 * i386-init.h: Regenerated.
769 * i386-tbl.h: Likewise.
770
f2a9c676
L		 7712008-01-02 H.J. Lu <hongjiu.lu@intel.com>
772
773 * i386-opc.h: Update comments.
774
d978b5be
L		 7752008-01-02 H.J. Lu <hongjiu.lu@intel.com>
776
777 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
778 * i386-opc.h: Likewise.
779 * i386-opc.tbl: Likewise.
780
582d5edd
L		 7812008-01-02 H.J. Lu <hongjiu.lu@intel.com>
782
783 PR gas/5534
784 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
785 Byte, Word, Dword, QWord and Xmmword.
786
787 * i386-opc.h (No_xSuf): New.
788 (CheckSize): Likewise.
789 (Byte): Likewise.
790 (Word): Likewise.
791 (Dword): Likewise.
792 (QWord): Likewise.
793 (Xmmword): Likewise.
794 (FWait): Updated.
795 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
796 Dword, QWord and Xmmword.
797
798 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
799 used.
800 * i386-tbl.h: Regenerated.
801
3fe15143
MK		 8022008-01-02 Mark Kettenis <kettenis@gnu.org>
803
804 * m88k-dis.c (instructions): Fix fcvt.* instructions.
805 From Miod Vallat.
806
6c7ac64e 807For older changes see ChangeLog-2007
252b5132
RH		 808\f
809Local Variables:
2f6d2f85
NC		 810mode: change-log
811left-margin: 8
812fill-column: 74
252b5132
RH		 813version-control: never
814End:
GDB Binutils - Deliverables
This page took 0.508918 seconds and 4 git commands to generate.