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[AArch64][SVE 23/32] Add SVE pattern and prfop operands
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
245d2e3f
RS		 12016-09-21 Richard Sandiford <richard.sandiford@arm.com>
2
3 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
4 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
5 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
6 (FLD_SVE_prfop): Likewise.
7 * aarch64-opc.c: Include libiberty.h.
8 (aarch64_sve_pattern_array): New variable.
9 (aarch64_sve_prfop_array): Likewise.
10 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
11 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
12 AARCH64_OPND_SVE_PRFOP.
13 * aarch64-asm-2.c: Regenerate.
14 * aarch64-dis-2.c: Likewise.
15 * aarch64-opc-2.c: Likewise.
16
d50c751e
RS		 172016-09-21 Richard Sandiford <richard.sandiford@arm.com>
18
19 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
20 AARCH64_OPND_QLF_P_[ZM].
21 (aarch64_print_operand): Print /z and /m where appropriate.
22
f11ad6bc
RS		 232016-09-21 Richard Sandiford <richard.sandiford@arm.com>
24
25 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
26 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
27 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
28 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
29 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
30 * aarch64-opc.c (fields): Add corresponding entries here.
31 (operand_general_constraint_met_p): Check that SVE register lists
32 have the correct length. Check the ranges of SVE index registers.
33 Check for cases where p8-p15 are used in 3-bit predicate fields.
34 (aarch64_print_operand): Handle the new SVE operands.
35 * aarch64-opc-2.c: Regenerate.
36 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
37 * aarch64-asm.c (aarch64_ins_sve_index): New function.
38 (aarch64_ins_sve_reglist): Likewise.
39 * aarch64-asm-2.c: Regenerate.
40 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
41 * aarch64-dis.c (aarch64_ext_sve_index): New function.
42 (aarch64_ext_sve_reglist): Likewise.
43 * aarch64-dis-2.c: Regenerate.
44
0c608d6b
RS		 452016-09-21 Richard Sandiford <richard.sandiford@arm.com>
46
47 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
48 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
49 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
50 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
51 tied operands.
52
01dbfe4c
RS		 532016-09-21 Richard Sandiford <richard.sandiford@arm.com>
54
55 * aarch64-opc.c (get_offset_int_reg_name): New function.
56 (print_immediate_offset_address): Likewise.
57 (print_register_offset_address): Take the base and offset
58 registers as parameters.
59 (aarch64_print_operand): Update caller accordingly. Use
60 print_immediate_offset_address.
61
72e9f319
RS		 622016-09-21 Richard Sandiford <richard.sandiford@arm.com>
63
64 * aarch64-opc.c (BANK): New macro.
65 (R32, R64): Take a register number as argument
66 (int_reg): Use BANK.
67
8a7f0c1b
RS		 682016-09-21 Richard Sandiford <richard.sandiford@arm.com>
69
70 * aarch64-opc.c (print_register_list): Add a prefix parameter.
71 (aarch64_print_operand): Update accordingly.
72
aa2aa4c6
RS		 732016-09-21 Richard Sandiford <richard.sandiford@arm.com>
74
75 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
76 for FPIMM.
77 * aarch64-asm.h (ins_fpimm): New inserter.
78 * aarch64-asm.c (aarch64_ins_fpimm): New function.
79 * aarch64-asm-2.c: Regenerate.
80 * aarch64-dis.h (ext_fpimm): New extractor.
81 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
82 (aarch64_ext_fpimm): New function.
83 * aarch64-dis-2.c: Regenerate.
84
b5464a68
RS		 852016-09-21 Richard Sandiford <richard.sandiford@arm.com>
86
87 * aarch64-asm.c: Include libiberty.h.
88 (insert_fields): New function.
89 (aarch64_ins_imm): Use it.
90 * aarch64-dis.c (extract_fields): New function.
91 (aarch64_ext_imm): Use it.
92
42408347
RS		 932016-09-21 Richard Sandiford <richard.sandiford@arm.com>
94
95 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
96 with an esize parameter.
97 (operand_general_constraint_met_p): Update accordingly.
98 Fix misindented code.
99 * aarch64-asm.c (aarch64_ins_limm): Update call to
100 aarch64_logical_immediate_p.
101
4989adac
RS		 1022016-09-21 Richard Sandiford <richard.sandiford@arm.com>
103
104 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
105
bd11d5d8
RS		 1062016-09-21 Richard Sandiford <richard.sandiford@arm.com>
107
108 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
109
f807f43d
CZ		 1102016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
111
112 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
113
fd486b63
PB		 1142016-09-14 Peter Bergner <bergner@vnet.ibm.com>
115
116 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
117 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
118 xor3>: Delete mnemonics.
119 <cp_abort>: Rename mnemonic from ...
120 <cpabort>: ...to this.
121 <setb>: Change to a X form instruction.
122 <sync>: Change to 1 operand form.
123 <copy>: Delete mnemonic.
124 <copy_first>: Rename mnemonic from ...
125 <copy>: ...to this.
126 <paste, paste.>: Delete mnemonics.
127 <paste_last>: Rename mnemonic from ...
128 <paste.>: ...to this.
129
dce08442
AK		 1302016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
131
132 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
133
952c3f51
AK		 1342016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
135
136 * s390-mkopc.c (main): Support alternate arch strings.
137
8b71537b
PS		 1382016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
139
140 * s390-opc.txt: Fix kmctr instruction type.
141
5b64d091
L		 1422016-09-07 H.J. Lu <hongjiu.lu@intel.com>
143
144 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
145 * i386-init.h: Regenerated.
146
7763838e
CM		 1472016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
148
149 * opcodes/arc-dis.c (print_insn_arc): Changed.
150
1b8b6532
JM		 1512016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
152
153 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
154 camellia_fl.
155
1a336194
TP		 1562016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
157
158 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
159 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
160 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
161
6b40c462
L		 1622016-08-24 H.J. Lu <hongjiu.lu@intel.com>
163
164 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
165 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
166 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
167 PREFIX_MOD_3_0FAE_REG_4.
168 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
169 PREFIX_MOD_3_0FAE_REG_4.
170 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
171 (cpu_flags): Add CpuPTWRITE.
172 * i386-opc.h (CpuPTWRITE): New.
173 (i386_cpu_flags): Add cpuptwrite.
174 * i386-opc.tbl: Add ptwrite instruction.
175 * i386-init.h: Regenerated.
176 * i386-tbl.h: Likewise.
177
ab548d2d
AK		 1782016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
179
180 * arc-dis.h: Wrap around in extern "C".
181
344bde0a
RS		 1822016-08-23 Richard Sandiford <richard.sandiford@arm.com>
183
184 * aarch64-tbl.h (V8_2_INSN): New macro.
185 (aarch64_opcode_table): Use it.
186
5ce912d8
RS		 1872016-08-23 Richard Sandiford <richard.sandiford@arm.com>
188
189 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
190 CORE_INSN, __FP_INSN and SIMD_INSN.
191
9d30b0bd
RS		 1922016-08-23 Richard Sandiford <richard.sandiford@arm.com>
193
194 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
195 (aarch64_opcode_table): Update uses accordingly.
196
dfdaec14
AJ		 1972016-07-25 Andrew Jenner <andrew@codesourcery.com>
198 Kwok Cheung Yeung <kcy@codesourcery.com>
199
200 opcodes/
201 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
202 'e_cmplwi' to 'e_cmpli' instead.
203 (OPVUPRT, OPVUPRT_MASK): Define.
204 (powerpc_opcodes): Add E200Z4 insns.
205 (vle_opcodes): Add context save/restore insns.
206
7bd374a4
MR		 2072016-07-27 Maciej W. Rozycki <macro@imgtec.com>
208
209 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
210 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
211 "j".
212
db18dbab
GM		 2132016-07-27 Graham Markall <graham.markall@embecosm.com>
214
215 * arc-nps400-tbl.h: Change block comments to GNU format.
216 * arc-dis.c: Add new globals addrtypenames,
217 addrtypenames_max, and addtypeunknown.
218 (get_addrtype): New function.
219 (print_insn_arc): Print colons and address types when
220 required.
221 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
222 define insert and extract functions for all address types.
223 (arc_operands): Add operands for colon and all address
224 types.
225 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
226 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
227 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
228 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
229 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
230 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
231
fecd57f9
L		 2322016-07-21 H.J. Lu <hongjiu.lu@intel.com>
233
234 * configure: Regenerated.
235
37fd5ef3
CZ		 2362016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
237
238 * arc-dis.c (skipclass): New structure.
239 (decodelist): New variable.
240 (is_compatible_p): New function.
241 (new_element): Likewise.
242 (skip_class_p): Likewise.
243 (find_format_from_table): Use skip_class_p function.
244 (find_format): Decode first the extension instructions.
245 (print_insn_arc): Select either ARCEM or ARCHS based on elf
246 e_flags.
247 (parse_option): New function.
248 (parse_disassembler_options): Likewise.
249 (print_arc_disassembler_options): Likewise.
250 (print_insn_arc): Use parse_disassembler_options function. Proper
251 select ARCv2 cpu variant.
252 * disassemble.c (disassembler_usage): Add ARC disassembler
253 options.
254
92281a5b
MR		 2552016-07-13 Maciej W. Rozycki <macro@imgtec.com>
256
257 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
258 annotation from the "nal" entry and reorder it beyond "bltzal".
259
6e7ced37
JM		 2602016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
261
262 * sparc-opc.c (ldtxa): New macro.
263 (sparc_opcodes): Use the macro defined above to add entries for
264 the LDTXA instructions.
265 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
266 instruction.
267
2f831b9a 2682016-07-07 James Bowman <james.bowman@ftdichip.com>
269
270 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
271 and "jmpc".
272
c07315e0
JB		 2732016-07-01 Jan Beulich <jbeulich@suse.com>
274
275 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
276 (movzb): Adjust to cover all permitted suffixes.
277 (movzw): New.
278 * i386-tbl.h: Re-generate.
279
9243100a
JB		 2802016-07-01 Jan Beulich <jbeulich@suse.com>
281
282 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
283 (lgdt): Remove Tbyte from non-64-bit variant.
284 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
285 xsaves64, xsavec64): Remove Disp16.
286 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
287 Remove Disp32S from non-64-bit variants. Remove Disp16 from
288 64-bit variants.
289 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
290 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
291 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
292 64-bit variants.
293 * i386-tbl.h: Re-generate.
294
8325cc63
JB		 2952016-07-01 Jan Beulich <jbeulich@suse.com>
296
297 * i386-opc.tbl (xlat): Remove RepPrefixOk.
298 * i386-tbl.h: Re-generate.
299
838441e4
YQ		 3002016-06-30 Yao Qi <yao.qi@linaro.org>
301
302 * arm-dis.c (print_insn): Fix typo in comment.
303
dab26bf4
RS		 3042016-06-28 Richard Sandiford <richard.sandiford@arm.com>
305
306 * aarch64-opc.c (operand_general_constraint_met_p): Check the
307 range of ldst_elemlist operands.
308 (print_register_list): Use PRIi64 to print the index.
309 (aarch64_print_operand): Likewise.
310
5703197e
TS		 3112016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
312
313 * mcore-opc.h: Remove sentinal.
314 * mcore-dis.c (print_insn_mcore): Adjust.
315
ce440d63
GM		 3162016-06-23 Graham Markall <graham.markall@embecosm.com>
317
318 * arc-opc.c: Correct description of availability of NPS400
319 features.
320
6fd3a02d
PB		 3212016-06-22 Peter Bergner <bergner@vnet.ibm.com>
322
323 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
324 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
325 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
326 xor3>: New mnemonics.
327 <setb>: Change to a VX form instruction.
328 (insert_sh6): Add support for rldixor.
329 (extract_sh6): Likewise.
330
6b477896
TS		 3312016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
332
333 * arc-ext.h: Wrap in extern C.
334
bdd582db
GM		 3352016-06-21 Graham Markall <graham.markall@embecosm.com>
336
337 * arc-dis.c (arc_insn_length): Add comment on instruction length.
338 Use same method for determining instruction length on ARC700 and
339 NPS-400.
340 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
341 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
342 with the NPS400 subclass.
343 * arc-opc.c: Likewise.
344
96074adc
JM		 3452016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
346
347 * sparc-opc.c (rdasr): New macro.
348 (wrasr): Likewise.
349 (rdpr): Likewise.
350 (wrpr): Likewise.
351 (rdhpr): Likewise.
352 (wrhpr): Likewise.
353 (sparc_opcodes): Use the macros above to fix and expand the
354 definition of read/write instructions from/to
355 asr/privileged/hyperprivileged instructions.
356 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
357 %hva_mask_nz. Prefer softint_set and softint_clear over
358 set_softint and clear_softint.
359 (print_insn_sparc): Support %ver in Rd.
360
7a10c22f
JM		 3612016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
362
363 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
364 architecture according to the hardware capabilities they require.
365
4f26fb3a
JM		 3662016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
367
368 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
369 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
370 bfd_mach_sparc_v9{c,d,e,v,m}.
371 * sparc-opc.c (MASK_V9C): Define.
372 (MASK_V9D): Likewise.
373 (MASK_V9E): Likewise.
374 (MASK_V9V): Likewise.
375 (MASK_V9M): Likewise.
376 (v6): Add MASK_V9{C,D,E,V,M}.
377 (v6notlet): Likewise.
378 (v7): Likewise.
379 (v8): Likewise.
380 (v9): Likewise.
381 (v9andleon): Likewise.
382 (v9a): Likewise.
383 (v9b): Likewise.
384 (v9c): Define.
385 (v9d): Likewise.
386 (v9e): Likewise.
387 (v9v): Likewise.
388 (v9m): Likewise.
389 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
390
3ee6e4fb
NC		 3912016-06-15 Nick Clifton <nickc@redhat.com>
392
393 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
394 constants to match expected behaviour.
395 (nds32_parse_opcode): Likewise. Also for whitespace.
396
02f3be19
AB		 3972016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
398
399 * arc-opc.c (extract_rhv1): Extract value from insn.
400
6f9f37ed 4012016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 402
403 * arc-nps400-tbl.h: Add ldbit instruction.
404 * arc-opc.c: Add flag classes required for ldbit.
405
6f9f37ed 4062016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 407
408 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
409 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
410 support the above instructions.
411
6f9f37ed 4122016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 413
414 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
415 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
416 csma, cbba, zncv, and hofs.
417 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
418 support the above instructions.
419
4202016-06-06 Graham Markall <graham.markall@embecosm.com>
421
422 * arc-nps400-tbl.h: Add andab and orab instructions.
423
4242016-06-06 Graham Markall <graham.markall@embecosm.com>
425
426 * arc-nps400-tbl.h: Add addl-like instructions.
427
4282016-06-06 Graham Markall <graham.markall@embecosm.com>
429
430 * arc-nps400-tbl.h: Add mxb and imxb instructions.
431
4322016-06-06 Graham Markall <graham.markall@embecosm.com>
433
434 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
435 instructions.
436
b2cc3f6f
AK		 4372016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
438
439 * s390-dis.c (option_use_insn_len_bits_p): New file scope
440 variable.
441 (init_disasm): Handle new command line option "insnlength".
442 (print_s390_disassembler_options): Mention new option in help
443 output.
444 (print_insn_s390): Use the encoded insn length when dumping
445 unknown instructions.
446
1857fe72
DC		 4472016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
448
449 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
450 to the address and set as symbol address for LDS/ STS immediate operands.
451
14b57c7c
AM		 4522016-06-07 Alan Modra <amodra@gmail.com>
453
454 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
455 cpu for "vle" to e500.
456 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
457 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
458 (PPCNONE): Delete, substitute throughout.
459 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
460 except for major opcode 4 and 31.
461 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
462
4d1464f2
MW		 4632016-06-07 Matthew Wahab <matthew.wahab@arm.com>
464
465 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
466 ARM_EXT_RAS in relevant entries.
467
026122a6
PB		 4682016-06-03 Peter Bergner <bergner@vnet.ibm.com>
469
470 PR binutils/20196
471 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
472 opcodes for E6500.
473
07f5af7d
L		 4742016-06-03 H.J. Lu <hongjiu.lu@intel.com>
475
476 PR binutis/18386
477 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
478 (indir_v_mode): New.
479 Add comments for '&'.
480 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
481 (putop): Handle '&'.
482 (intel_operand_size): Handle indir_v_mode.
483 (OP_E_register): Likewise.
484 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
485 64-bit indirect call/jmp for AMD64.
486 * i386-tbl.h: Regenerated
487
4eb6f892
AB		 4882016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
489
490 * arc-dis.c (struct arc_operand_iterator): New structure.
491 (find_format_from_table): All the old content from find_format,
492 with some minor adjustments, and parameter renaming.
493 (find_format_long_instructions): New function.
494 (find_format): Rewritten.
495 (arc_insn_length): Add LSB parameter.
496 (extract_operand_value): New function.
497 (operand_iterator_next): New function.
498 (print_insn_arc): Use new functions to find opcode, and iterator
499 over operands.
500 * arc-opc.c (insert_nps_3bit_dst_short): New function.
501 (extract_nps_3bit_dst_short): New function.
502 (insert_nps_3bit_src2_short): New function.
503 (extract_nps_3bit_src2_short): New function.
504 (insert_nps_bitop1_size): New function.
505 (extract_nps_bitop1_size): New function.
506 (insert_nps_bitop2_size): New function.
507 (extract_nps_bitop2_size): New function.
508 (insert_nps_bitop_mod4_msb): New function.
509 (extract_nps_bitop_mod4_msb): New function.
510 (insert_nps_bitop_mod4_lsb): New function.
511 (extract_nps_bitop_mod4_lsb): New function.
512 (insert_nps_bitop_dst_pos3_pos4): New function.
513 (extract_nps_bitop_dst_pos3_pos4): New function.
514 (insert_nps_bitop_ins_ext): New function.
515 (extract_nps_bitop_ins_ext): New function.
516 (arc_operands): Add new operands.
517 (arc_long_opcodes): New global array.
518 (arc_num_long_opcodes): New global.
519 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
520
1fe0971e
TS		 5212016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
522
523 * nds32-asm.h: Add extern "C".
524 * sh-opc.h: Likewise.
525
315f180f
GM		 5262016-06-01 Graham Markall <graham.markall@embecosm.com>
527
528 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
529 0,b,limm to the rflt instruction.
530
a2b5fccc
TS		 5312016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
532
533 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
534 constant.
535
0cbd0046
L		 5362016-05-29 H.J. Lu <hongjiu.lu@intel.com>
537
538 PR gas/20145
539 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
540 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
541 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
542 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
543 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
544 * i386-init.h: Regenerated.
545
1848e567
L		 5462016-05-27 H.J. Lu <hongjiu.lu@intel.com>
547
548 PR gas/20145
549 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
550 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
551 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
552 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
553 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
554 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
555 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
556 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
557 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
558 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
559 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
560 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
561 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
562 CpuRegMask for AVX512.
563 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
564 and CpuRegMask.
565 (set_bitfield_from_cpu_flag_init): New function.
566 (set_bitfield): Remove const on f. Call
567 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
568 * i386-opc.h (CpuRegMMX): New.
569 (CpuRegXMM): Likewise.
570 (CpuRegYMM): Likewise.
571 (CpuRegZMM): Likewise.
572 (CpuRegMask): Likewise.
573 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
574 and cpuregmask.
575 * i386-init.h: Regenerated.
576 * i386-tbl.h: Likewise.
577
e92bae62
L		 5782016-05-27 H.J. Lu <hongjiu.lu@intel.com>
579
580 PR gas/20154
581 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
582 (opcode_modifiers): Add AMD64 and Intel64.
583 (main): Properly verify CpuMax.
584 * i386-opc.h (CpuAMD64): Removed.
585 (CpuIntel64): Likewise.
586 (CpuMax): Set to CpuNo64.
587 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
588 (AMD64): New.
589 (Intel64): Likewise.
590 (i386_opcode_modifier): Add amd64 and intel64.
591 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
592 on call and jmp.
593 * i386-init.h: Regenerated.
594 * i386-tbl.h: Likewise.
595
e89c5eaa
L		 5962016-05-27 H.J. Lu <hongjiu.lu@intel.com>
597
598 PR gas/20154
599 * i386-gen.c (main): Fail if CpuMax is incorrect.
600 * i386-opc.h (CpuMax): Set to CpuIntel64.
601 * i386-tbl.h: Regenerated.
602
77d66e7b
NC		 6032016-05-27 Nick Clifton <nickc@redhat.com>
604
605 PR target/20150
606 * msp430-dis.c (msp430dis_read_two_bytes): New function.
607 (msp430dis_opcode_unsigned): New function.
608 (msp430dis_opcode_signed): New function.
609 (msp430_singleoperand): Use the new opcode reading functions.
610 Only disassenmble bytes if they were successfully read.
611 (msp430_doubleoperand): Likewise.
612 (msp430_branchinstr): Likewise.
613 (msp430x_callx_instr): Likewise.
614 (print_insn_msp430): Check that it is safe to read bytes before
615 attempting disassembly. Use the new opcode reading functions.
616
19dfcc89
PB		 6172016-05-26 Peter Bergner <bergner@vnet.ibm.com>
618
619 * ppc-opc.c (CY): New define. Document it.
620 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
621
f3ad7637
L		 6222016-05-25 H.J. Lu <hongjiu.lu@intel.com>
623
624 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
625 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
626 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
627 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
628 CPU_ANY_AVX_FLAGS.
629 * i386-init.h: Regenerated.
630
f1360d58
L		 6312016-05-25 H.J. Lu <hongjiu.lu@intel.com>
632
633 PR gas/20141
634 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
635 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
636 * i386-init.h: Regenerated.
637
293f5f65
L		 6382016-05-25 H.J. Lu <hongjiu.lu@intel.com>
639
640 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
641 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
642 * i386-init.h: Regenerated.
643
d9eca1df
CZ		 6442016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
645
646 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
647 information.
648 (print_insn_arc): Set insn_type information.
649 * arc-opc.c (C_CC): Add F_CLASS_COND.
650 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
651 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
652 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
653 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
654 (brne, brne_s, jeq_s, jne_s): Likewise.
655
87789e08
CZ		 6562016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
657
658 * arc-tbl.h (neg): New instruction variant.
659
c810e0b8
CZ		 6602016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
661
662 * arc-dis.c (find_format, find_format, get_auxreg)
663 (print_insn_arc): Changed.
664 * arc-ext.h (INSERT_XOP): Likewise.
665
3d207518
TS		 6662016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
667
668 * tic54x-dis.c (sprint_mmr): Adjust.
669 * tic54x-opc.c: Likewise.
670
514e58b7
AM		 6712016-05-19 Alan Modra <amodra@gmail.com>
672
673 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
674
e43de63c
AM		 6752016-05-19 Alan Modra <amodra@gmail.com>
676
677 * ppc-opc.c: Formatting.
678 (NSISIGNOPT): Define.
679 (powerpc_opcodes <subis>): Use NSISIGNOPT.
680
1401d2fe
MR		 6812016-05-18 Maciej W. Rozycki <macro@imgtec.com>
682
683 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
684 replacing references to `micromips_ase' throughout.
685 (_print_insn_mips): Don't use file-level microMIPS annotation to
686 determine the disassembly mode with the symbol table.
687
1178da44
PB		 6882016-05-13 Peter Bergner <bergner@vnet.ibm.com>
689
690 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
691
8f4f9071
MF		 6922016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
693
694 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
695 mips64r6.
696 * mips-opc.c (D34): New macro.
697 (mips_builtin_opcodes): Define bposge32c for DSPr3.
698
8bc52696
AF		 6992016-05-10 Alexander Fomin <alexander.fomin@intel.com>
700
701 * i386-dis.c (prefix_table): Add RDPID instruction.
702 * i386-gen.c (cpu_flag_init): Add RDPID flag.
703 (cpu_flags): Add RDPID bitfield.
704 * i386-opc.h (enum): Add RDPID element.
705 (i386_cpu_flags): Add RDPID field.
706 * i386-opc.tbl: Add RDPID instruction.
707 * i386-init.h: Regenerate.
708 * i386-tbl.h: Regenerate.
709
39d911fc
TP		 7102016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
711
712 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
713 branch type of a symbol.
714 (print_insn): Likewise.
715
16a1fa25
TP		 7162016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
717
718 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
719 Mainline Security Extensions instructions.
720 (thumb_opcodes): Add entries for narrow ARMv8-M Security
721 Extensions instructions.
722 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
723 instructions.
724 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
725 special registers.
726
d751b79e
JM		 7272016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
728
729 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
730
945e0f82
CZ		 7312016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
732
733 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
734 (arcExtMap_genOpcode): Likewise.
735 * arc-opc.c (arg_32bit_rc): Define new variable.
736 (arg_32bit_u6): Likewise.
737 (arg_32bit_limm): Likewise.
738
20f55f38
SN		 7392016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
740
741 * aarch64-gen.c (VERIFIER): Define.
742 * aarch64-opc.c (VERIFIER): Define.
743 (verify_ldpsw): Use static linkage.
744 * aarch64-opc.h (verify_ldpsw): Remove.
745 * aarch64-tbl.h: Use VERIFIER for verifiers.
746
4bd13cde
NC		 7472016-04-28 Nick Clifton <nickc@redhat.com>
748
749 PR target/19722
750 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
751 * aarch64-opc.c (verify_ldpsw): New function.
752 * aarch64-opc.h (verify_ldpsw): New prototype.
753 * aarch64-tbl.h: Add initialiser for verifier field.
754 (LDPSW): Set verifier to verify_ldpsw.
755
c0f92bf9
L		 7562016-04-23 H.J. Lu <hongjiu.lu@intel.com>
757
758 PR binutils/19983
759 PR binutils/19984
760 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
761 smaller than address size.
762
e6c7cdec
TS		 7632016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
764
765 * alpha-dis.c: Regenerate.
766 * crx-dis.c: Likewise.
767 * disassemble.c: Likewise.
768 * epiphany-opc.c: Likewise.
769 * fr30-opc.c: Likewise.
770 * frv-opc.c: Likewise.
771 * ip2k-opc.c: Likewise.
772 * iq2000-opc.c: Likewise.
773 * lm32-opc.c: Likewise.
774 * lm32-opinst.c: Likewise.
775 * m32c-opc.c: Likewise.
776 * m32r-opc.c: Likewise.
777 * m32r-opinst.c: Likewise.
778 * mep-opc.c: Likewise.
779 * mt-opc.c: Likewise.
780 * or1k-opc.c: Likewise.
781 * or1k-opinst.c: Likewise.
782 * tic80-opc.c: Likewise.
783 * xc16x-opc.c: Likewise.
784 * xstormy16-opc.c: Likewise.
785
537aefaf
AB		 7862016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
787
788 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
789 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
790 calcsd, and calcxd instructions.
791 * arc-opc.c (insert_nps_bitop_size): Delete.
792 (extract_nps_bitop_size): Delete.
793 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
794 (extract_nps_qcmp_m3): Define.
795 (extract_nps_qcmp_m2): Define.
796 (extract_nps_qcmp_m1): Define.
797 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
798 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
799 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
800 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
801 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
802 NPS_QCMP_M3.
803
c8f785f2
AB		 8042016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
805
806 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
807
6fd8e7c2
L		 8082016-04-15 H.J. Lu <hongjiu.lu@intel.com>
809
810 * Makefile.in: Regenerated with automake 1.11.6.
811 * aclocal.m4: Likewise.
812
4b0c052e
AB		 8132016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
814
815 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
816 instructions.
817 * arc-opc.c (insert_nps_cmem_uimm16): New function.
818 (extract_nps_cmem_uimm16): New function.
819 (arc_operands): Add NPS_XLDST_UIMM16 operand.
820
cb040366
AB		 8212016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
822
823 * arc-dis.c (arc_insn_length): New function.
824 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
825 (find_format): Change insnLen parameter to unsigned.
826
accc0180
NC		 8272016-04-13 Nick Clifton <nickc@redhat.com>
828
829 PR target/19937
830 * v850-opc.c (v850_opcodes): Correct masks for long versions of
831 the LD.B and LD.BU instructions.
832
f36e33da
CZ		 8332016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
834
835 * arc-dis.c (find_format): Check for extension flags.
836 (print_flags): New function.
837 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
838 .extAuxRegister.
839 * arc-ext.c (arcExtMap_coreRegName): Use
840 LAST_EXTENSION_CORE_REGISTER.
841 (arcExtMap_coreReadWrite): Likewise.
842 (dump_ARC_extmap): Update printing.
843 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
844 (arc_aux_regs): Add cpu field.
845 * arc-regs.h: Add cpu field, lower case name aux registers.
846
1c2e355e
CZ		 8472016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
848
849 * arc-tbl.h: Add rtsc, sleep with no arguments.
850
b99747ae
CZ		 8512016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
852
853 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
854 Initialize.
855 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
856 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
857 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
858 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
859 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
860 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
861 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
862 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
863 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
864 (arc_opcode arc_opcodes): Null terminate the array.
865 (arc_num_opcodes): Remove.
866 * arc-ext.h (INSERT_XOP): Define.
867 (extInstruction_t): Likewise.
868 (arcExtMap_instName): Delete.
869 (arcExtMap_insn): New function.
870 (arcExtMap_genOpcode): Likewise.
871 * arc-ext.c (ExtInstruction): Remove.
872 (create_map): Zero initialize instruction fields.
873 (arcExtMap_instName): Remove.
874 (arcExtMap_insn): New function.
875 (dump_ARC_extmap): More info while debuging.
876 (arcExtMap_genOpcode): New function.
877 * arc-dis.c (find_format): New function.
878 (print_insn_arc): Use find_format.
879 (arc_get_disassembler): Enable dump_ARC_extmap only when
880 debugging.
881
92708cec
MR		 8822016-04-11 Maciej W. Rozycki <macro@imgtec.com>
883
884 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
885 instruction bits out.
886
a42a4f84
AB		 8872016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
888
889 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
890 * arc-opc.c (arc_flag_operands): Add new flags.
891 (arc_flag_classes): Add new classes.
892
1328504b
AB		 8932016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
894
895 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
896
820f03ff
AB		 8972016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
898
899 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
900 encode1, rflt, crc16, and crc32 instructions.
901 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
902 (arc_flag_classes): Add C_NPS_R.
903 (insert_nps_bitop_size_2b): New function.
904 (extract_nps_bitop_size_2b): Likewise.
905 (insert_nps_bitop_uimm8): Likewise.
906 (extract_nps_bitop_uimm8): Likewise.
907 (arc_operands): Add new operand entries.
908
8ddf6b2a
CZ		 9092016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
910
b99747ae
CZ		 911 * arc-regs.h: Add a new subclass field. Add double assist
912 accumulator register values.
913 * arc-tbl.h: Use DPA subclass to mark the double assist
914 instructions. Use DPX/SPX subclas to mark the FPX instructions.
915 * arc-opc.c (RSP): Define instead of SP.
916 (arc_aux_regs): Add the subclass field.
8ddf6b2a 917
589a7d88
JW		 9182016-04-05 Jiong Wang <jiong.wang@arm.com>
919
920 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
921
0a191de9 9222016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 923
924 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
925 NPS_R_SRC1.
926
0a106562
AB		 9272016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
928
929 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
930 issues. No functional changes.
931
bd05ac5f
CZ		 9322016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
933
b99747ae
CZ		 934 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
935 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
936 (RTT): Remove duplicate.
937 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
938 (PCT_CONFIG*): Remove.
939 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 940
9885948f
CZ		 9412016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
942
b99747ae 943 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 944
f2dd8838
CZ		 9452016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
946
b99747ae
CZ		 947 * arc-tbl.h (invld07): Remove.
948 * arc-ext-tbl.h: New file.
949 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
950 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 951
0d2f91fe
JK		 9522016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
953
954 Fix -Wstack-usage warnings.
955 * aarch64-dis.c (print_operands): Substitute size.
956 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
957
a6b71f42
JM		 9582016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
959
960 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
961 to get a proper diagnostic when an invalid ASR register is used.
962
9780e045
NC		 9632016-03-22 Nick Clifton <nickc@redhat.com>
964
965 * configure: Regenerate.
966
e23e8ebe
AB		 9672016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
968
969 * arc-nps400-tbl.h: New file.
970 * arc-opc.c: Add top level comment.
971 (insert_nps_3bit_dst): New function.
972 (extract_nps_3bit_dst): New function.
973 (insert_nps_3bit_src2): New function.
974 (extract_nps_3bit_src2): New function.
975 (insert_nps_bitop_size): New function.
976 (extract_nps_bitop_size): New function.
977 (arc_flag_operands): Add nps400 entries.
978 (arc_flag_classes): Add nps400 entries.
979 (arc_operands): Add nps400 entries.
980 (arc_opcodes): Add nps400 include.
981
1ae8ab47
AB		 9822016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
983
984 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
985 the new class enum values.
986
8699fc3e
AB		 9872016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
988
989 * arc-dis.c (print_insn_arc): Handle nps400.
990
24740d83
AB		 9912016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
992
993 * arc-opc.c (BASE): Delete.
994
8678914f
NC		 9952016-03-18 Nick Clifton <nickc@redhat.com>
996
997 PR target/19721
998 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
999 of MOV insn that aliases an ORR insn.
1000
cc933301
JW		 10012016-03-16 Jiong Wang <jiong.wang@arm.com>
1002
1003 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1004
f86f5863
TS		 10052016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1006
1007 * mcore-opc.h: Add const qualifiers.
1008 * microblaze-opc.h (struct op_code_struct): Likewise.
1009 * sh-opc.h: Likewise.
1010 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1011 (tic4x_print_op): Likewise.
1012
62de1c63
AM		 10132016-03-02 Alan Modra <amodra@gmail.com>
1014
d11698cd 1015 * or1k-desc.h: Regenerate.
62de1c63 1016 * fr30-ibld.c: Regenerate.
c697cf0b 1017 * rl78-decode.c: Regenerate.
62de1c63 1018
020efce5
NC		 10192016-03-01 Nick Clifton <nickc@redhat.com>
1020
1021 PR target/19747
1022 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1023
b0c11777
RL		 10242016-02-24 Renlin Li <renlin.li@arm.com>
1025
1026 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1027 (print_insn_coprocessor): Support fp16 instructions.
1028
3e309328
RL		 10292016-02-24 Renlin Li <renlin.li@arm.com>
1030
1031 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1032 vminnm, vrint(mpna).
1033
8afc7bea
RL		 10342016-02-24 Renlin Li <renlin.li@arm.com>
1035
1036 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1037 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1038
4fd7268a
L		 10392016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1040
1041 * i386-dis.c (print_insn): Parenthesize expression to prevent
1042 truncated addresses.
1043 (OP_J): Likewise.
1044
4670103e
CZ		 10452016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1046 Janek van Oirschot <jvanoirs@synopsys.com>
1047
b99747ae
CZ		 1048 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1049 variable.
4670103e 1050
c1d9289f
NC		 10512016-02-04 Nick Clifton <nickc@redhat.com>
1052
1053 PR target/19561
1054 * msp430-dis.c (print_insn_msp430): Add a special case for
1055 decoding an RRC instruction with the ZC bit set in the extension
1056 word.
1057
a143b004
AB		 10582016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1059
1060 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1061 * epiphany-ibld.c: Regenerate.
1062 * fr30-ibld.c: Regenerate.
1063 * frv-ibld.c: Regenerate.
1064 * ip2k-ibld.c: Regenerate.
1065 * iq2000-ibld.c: Regenerate.
1066 * lm32-ibld.c: Regenerate.
1067 * m32c-ibld.c: Regenerate.
1068 * m32r-ibld.c: Regenerate.
1069 * mep-ibld.c: Regenerate.
1070 * mt-ibld.c: Regenerate.
1071 * or1k-ibld.c: Regenerate.
1072 * xc16x-ibld.c: Regenerate.
1073 * xstormy16-ibld.c: Regenerate.
1074
b89807c6
AB		 10752016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1076
1077 * epiphany-dis.c: Regenerated from latest cpu files.
1078
d8c823c8
MM		 10792016-02-01 Michael McConville <mmcco@mykolab.com>
1080
1081 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1082 test bit.
1083
5bc5ae88
RL		 10842016-01-25 Renlin Li <renlin.li@arm.com>
1085
1086 * arm-dis.c (mapping_symbol_for_insn): New function.
1087 (find_ifthen_state): Call mapping_symbol_for_insn().
1088
0bff6e2d
MW		 10892016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1090
1091 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1092 of MSR UAO immediate operand.
1093
100b4f2e
MR		 10942016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1095
1096 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1097 instruction support.
1098
5c14705f
AM		 10992016-01-17 Alan Modra <amodra@gmail.com>
1100
1101 * configure: Regenerate.
1102
4d82fe66
NC		 11032016-01-14 Nick Clifton <nickc@redhat.com>
1104
1105 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1106 instructions that can support stack pointer operations.
1107 * rl78-decode.c: Regenerate.
1108 * rl78-dis.c: Fix display of stack pointer in MOVW based
1109 instructions.
1110
651657fa
MW		 11112016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1112
1113 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1114 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1115 erxtatus_el1 and erxaddr_el1.
1116
105bde57
MW		 11172016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1118
1119 * arm-dis.c (arm_opcodes): Add "esb".
1120 (thumb_opcodes): Likewise.
1121
afa8d405
PB		 11222016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1123
1124 * ppc-opc.c <xscmpnedp>: Delete.
1125 <xvcmpnedp>: Likewise.
1126 <xvcmpnedp.>: Likewise.
1127 <xvcmpnesp>: Likewise.
1128 <xvcmpnesp.>: Likewise.
1129
83c3256e
AS		 11302016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1131
1132 PR gas/13050
1133 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1134 addition to ISA_A.
1135
6f2750fe
AM		 11362016-01-01 Alan Modra <amodra@gmail.com>
1137
1138 Update year range in copyright notice of all files.
1139
3499769a
AM		 1140For older changes see ChangeLog-2015
1141\f
1142Copyright (C) 2016 Free Software Foundation, Inc.
1143
1144Copying and distribution of this file, with or without modification,
1145are permitted in any medium without royalty provided the copyright
1146notice and this notice are preserved.
1147
1148Local Variables:
1149mode: change-log
1150left-margin: 8
1151fill-column: 74
1152version-control: never
1153End:
GDB Binutils - Deliverables
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