[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* arm-dis.c (print_insn_coprocessor): Avoid negative shift.

2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c: Add comment accidentally removed by old commit.
	(MTMSRD_L): Delete.

2015-06-04  Nick Clifton  <nickc@redhat.com>

	PR 18474
	* msp430-dis.c (msp430_nooperands): Fix check for emulated insns.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (arm_opcodes): Add "setpan".
	(thumb_opcodes): Add "setpan".

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (select_arm_features): Rework to avoid used of redefined
	macros.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_rdma): New.
	(RDMA): New.
	(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_lor): New.
	(LOR): New.
	(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
	"stllrb", "stllrh".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (F_ARCHEXT): New.
	(aarch64_sys_regs): Add "pan".
	(aarch64_sys_reg_supported_p): New.
	(aarch64_pstatefields): Add "pan".
	(aarch64_pstatefield_supported_p): New.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-tbl.h: Regenerate.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (print_insn): Swap rounding mode specifier and
	general purpose register in Intel mode.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	* i386-tbl.h: Regenerate.

2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	* i386-init.h: Regenerated.

2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (IH) New define.
	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	<tlbie>: Add RS operand for POWER7.
	<slbia>: Add IH operand for POWER6.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
	direct branch.
	(jmp): Likewise.
	* i386-tbl.h: Regenerated.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.ac: Support bfd_iamcu_arch.
	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	CPU_IAMCU_COMPAT_FLAGS.
	(cpu_flags): Add CpuIAMCU.
	* i386-opc.h (CpuIAMCU): New.
	(i386_cpu_flags): Add cpuiamcu.
	* configure: Regenerated.
	* i386-init.h: Likewise.
	* i386-tbl.h: Likewise.

2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c (X86_64_E8): New.
	(X86_64_E9): Likewise.
	Update comments on 'T', 'U', 'V'.  Add comments for '^'.
	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	(mod_table): Replace {T|} with ^ on Jcall/Jmp.
	(putop): Handle '^'.
	(OP_J): Ignore the operand size prefix in 64-bit.  Don't check
	REX_W.

2015-04-30  DJ Delorie  <dj@redhat.com>

	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

2015-04-29  Nick Clifton  <nickc@redhat.com>

	* po/fr.po: Updated French translation.

2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (DCBT_EO): New define.
	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	<lharx>: Likewise.
	<stbcx.>: Likewise.
	<sthcx.>: Likewise.
	<waitrsv>: Do not enable for POWER7 and later.
	<waitimpl>: Likewise.
	<dcbt>: Default to the two operand form of the instruction for all
	"old" cpus.  For "new" cpus, use the operand ordering that matches
	whether the cpu is server or embedded.
	<dcbtst>: Likewise.

2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: New instruction type VV0UU2.
	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	and WFC.

2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	(vfpclasspd, vfpclassps): Add %XZ.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	(PREFIX_UD_REPZ): Likewise.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_requirement): Removed.
	(print_insn): Don't set prefix_requirement.  Check
	dp->prefix_requirement instead of prefix_requirement.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/17898
	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	(PREFIX_MOD_0_0FC7_REG_6): This.
	(PREFIX_MOD_3_0FC7_REG_6): New.
	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.
	(mod_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	(PREFIX_MANDATORY_REPNZ): Likewise.
	(PREFIX_MANDATORY_DATA): Likewise.
	(PREFIX_MANDATORY_ADDR): Likewise.
	(PREFIX_MANDATORY_LOCK): Likewise.
	(PREFIX_MANDATORY): Likewise.
	(PREFIX_UD_SHIFT): Set to 8
	(PREFIX_UD_REPZ): Updated.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.
	(PREFIX_IGNORED_SHIFT): New.
	(PREFIX_IGNORED_REPZ): Likewise.
	(PREFIX_IGNORED_REPNZ): Likewise.
	(PREFIX_IGNORED_DATA): Likewise.
	(PREFIX_IGNORED_ADDR): Likewise.
	(PREFIX_IGNORED_LOCK): Likewise.
	(PREFIX_OPCODE): Likewise.
	(PREFIX_IGNORED): Likewise.
	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	(three_byte_table): Likewise.
	(mod_table): Likewise.
	(mandatory_prefix): Renamed to ...
	(prefix_requirement): This.
	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	Update PREFIX_90 entry.
	(get_valid_dis386): Check prefix_requirement to see if a prefix
	should be ignored.
	(print_insn): Replace mandatory_prefix with prefix_requirement.

2015-04-15  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	use it for ssat and ssat16.
	(print_insn_thumb32): Add handle case for 'D' control code.

2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
	    H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	Fill prefix_requirement field.
	(struct dis386): Add prefix_requirement field.
	(dis386): Fill prefix_requirement field.
	(dis386_twobyte): Ditto.
	(twobyte_has_mandatory_prefix_: Remove.
	(reg_table): Fill prefix_requirement field.
	(prefix_table): Ditto.
	(x86_64_table): Ditto.
	(three_byte_table): Ditto.
	(xop_table): Ditto.
	(vex_table): Ditto.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(mod_table): Ditto.
	(bad_opcode): Ditto.
	(print_insn): Use prefix_requirement.
	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	(float_reg): Ditto.

2015-03-30  Mike Frysinger  <vapier@gentoo.org>

	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.

2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.in: Regenerated.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	powerpc_opcd_indices and vle_opcd_indices once.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-opc.c (powerpc_opcodes): Add slbfee.

2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	(opcode16): Likewise.
	(coprocessor_opcodes): Replace bit with feature struct.
	(neon_opcodes): Likewise.
	(arm_opcodes): Likewise.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
	(print_insn_coprocessor): Likewise.
	(print_insn_arm): Likewise.
	(select_arm_features): Follow new feature struct.

2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>

	* i386-dis.c (rm_table): Add clzero.
	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	Add CPU_CLZERO_FLAGS.
	(cpu_flags): Add CpuCLZERO.
	* i386-opc.h: Add CpuCLZERO.
	* i386-opc.tbl: Add clzero.
	* i386-init.h: Re-generated.
	* i386-tbl.h: Re-generated.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (decode_mips_operand): Fix constraint issues
	with u and y operands.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.

2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Add new IBM z13 instructions.
	* s390-opc.txt: Likewise.

2015-03-10  Renlin Li  <renlin.li@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	related alias.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2015-03-03  Jiong Wang  <jiong.wang@arm.com>

	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.

2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>

	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	arch_sh_up.
	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.

2015-02-23  Vinay  <Vinay.G@kpit.com>

	* rl78-decode.opc (MOV): Added space between two operands for
	'mov' instruction in index addressing mode.
	* rl78-decode.c: Regenerate.

2015-02-19  Pedro Alves  <palves@redhat.com>

	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".

2015-02-10  Pedro Alves  <palves@redhat.com>
	    Tom Tromey  <tromey@redhat.com>

	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	microblaze_and, microblaze_xor.
	* microblaze-opc.h (opcodes): Adjust.

2015-01-28  James Bowman  <james.bowman@ftdichip.com>

	* Makefile.am: Add FT32 files.
	* configure.ac: Handle FT32.
	* disassemble.c (disassembler): Call print_insn_ft32.
	* ft32-dis.c: New file.
	* ft32-opc.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.

2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>

	* nds32-asm.c (keyword_sr): Add new system registers.

2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-dis.c (s390_extract_operand): Support vector register
	operands.
	(s390_print_insn_with_opcode): Support new operands types and add
	new handling of optional operands.
	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	and include opcode/s390.h instead.
	(struct op_struct): New field `flags'.
	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	(dumpTable): Dump flags.
	(main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
	string.
	* s390-opc.c: Add new operands types, instruction formats, and
	instruction masks.
	(s390_opformats): Add new formats for .insn.
	* s390-opc.txt: Add new instructions.

2015-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2014
\f
Copyright (C) 2015 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
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Commit	Line	Data
24b4cf66 SN	1	2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
	2
	3	* arm-dis.c (print_insn_coprocessor): Avoid negative shift.
	4
99a2c561 PB	5	2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
	6
	7	* ppc-opc.c: Add comment accidentally removed by old commit.
	8	(MTMSRD_L): Delete.
	9
13be46a2 NC	10	2015-06-04 Nick Clifton <nickc@redhat.com>
	11
	12	PR 18474
	13	* msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
	14
ddfded2f MW	15	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	16
	17	* arm-dis.c (arm_opcodes): Add "setpan".
	18	(thumb_opcodes): Add "setpan".
	19
1af1dd51 MW	20	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	21
	22	* arm-dis.c (select_arm_features): Rework to avoid used of redefined
	23	macros.
	24
9e1f0fa7 MW	25	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	26
	27	* aarch64-tbl.h (aarch64_feature_rdma): New.
	28	(RDMA): New.
	29	(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
	30	* aarch64-asm-2.c: Regenerate.
	31	* aarch64-dis-2.c: Regenerate.
	32	* aarch64-opc-2.c: Regenerate.
	33
290806fd MW	34	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	35
	36	* aarch64-tbl.h (aarch64_feature_lor): New.
	37	(LOR): New.
	38	(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
	39	"stllrb", "stllrh".
	40	* aarch64-asm-2.c: Regenerate.
	41	* aarch64-dis-2.c: Regenerate.
	42	* aarch64-opc-2.c: Regenerate.
	43
f21cce2c MW	44	2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
	45
	46	* aarch64-opc.c (F_ARCHEXT): New.
	47	(aarch64_sys_regs): Add "pan".
	48	(aarch64_sys_reg_supported_p): New.
	49	(aarch64_pstatefields): Add "pan".
	50	(aarch64_pstatefield_supported_p): New.
	51
d194d186 JB	52	2015-06-01 Jan Beulich <jbeulich@suse.com>
	53
	54	* i386-tbl.h: Regenerate.
	55
3a8547d2 JB	56	2015-06-01 Jan Beulich <jbeulich@suse.com>
	57
	58	* i386-dis.c (print_insn): Swap rounding mode specifier and
	59	general purpose register in Intel mode.
	60
015c54d5 JB	61	2015-06-01 Jan Beulich <jbeulich@suse.com>
	62
	63	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	64	* i386-tbl.h: Regenerate.
	65
071f0063 L	66	2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
	67
	68	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	69	* i386-init.h: Regenerated.
	70
5db04b09 L	71	2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
	72
	73	PR binutis/18386
	74	* i386-dis.c: Add comments for '@'.
	75	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	76	(enum x86_64_isa): New.
	77	(isa64): Likewise.
	78	(print_i386_disassembler_options): Add amd64 and intel64.
	79	(print_insn): Handle amd64 and intel64.
	80	(putop): Handle '@'.
	81	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	82	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	83	* i386-opc.h (AMD64): New.
	84	(CpuIntel64): Likewise.
	85	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	86	* i386-opc.tbl: Add direct call/jmp with Disp16\|Disp32 for AMD64.
	87	Mark direct call/jmp without Disp16\|Disp32 as Intel64.
	88	* i386-init.h: Regenerated.
	89	* i386-tbl.h: Likewise.
	90
4bc0608a PB	91	2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
	92
	93	* ppc-opc.c (IH) New define.
	94	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	95	<tlbie>: Add RS operand for POWER7.
	96	<slbia>: Add IH operand for POWER6.
	97
70cead07 L	98	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	99
	100	* opcodes/i386-opc.tbl (call): Remove Disp16\|Disp32 from 64-bit
	101	direct branch.
	102	(jmp): Likewise.
	103	* i386-tbl.h: Regenerated.
	104
7b6d09fb L	105	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	106
	107	* configure.ac: Support bfd_iamcu_arch.
	108	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	109	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	110	CPU_IAMCU_COMPAT_FLAGS.
	111	(cpu_flags): Add CpuIAMCU.
	112	* i386-opc.h (CpuIAMCU): New.
	113	(i386_cpu_flags): Add cpuiamcu.
	114	* configure: Regenerated.
	115	* i386-init.h: Likewise.
	116	* i386-tbl.h: Likewise.
	117
31955f99 L	118	2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
	119
	120	PR binutis/18386
	121	* i386-dis.c (X86_64_E8): New.
	122	(X86_64_E9): Likewise.
	123	Update comments on 'T', 'U', 'V'. Add comments for '^'.
	124	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	125	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	126	(mod_table): Replace {T\|} with ^ on Jcall/Jmp.
	127	(putop): Handle '^'.
	128	(OP_J): Ignore the operand size prefix in 64-bit. Don't check
	129	REX_W.
	130
0952813b DD	131	2015-04-30 DJ Delorie <dj@redhat.com>
	132
	133	* disassemble.c (disassembler): Choose suitable disassembler based
	134	on E_ABI.
	135	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
	136	it to decode mul/div insns.
	137	* rl78-decode.c: Regenerate.
	138	* rl78-dis.c (print_insn_rl78): Rename to...
	139	(print_insn_rl78_common): ...this, take ISA parameter.
	140	(print_insn_rl78): New.
	141	(print_insn_rl78_g10): New.
	142	(print_insn_rl78_g13): New.
	143	(print_insn_rl78_g14): New.
	144	(rl78_get_disassembler): New.
	145
f9d3ecaa NC	146	2015-04-29 Nick Clifton <nickc@redhat.com>
	147
	148	* po/fr.po: Updated French translation.
	149
4fff86c5 PB	150	2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
	151
	152	* ppc-opc.c (DCBT_EO): New define.
	153	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	154	<lharx>: Likewise.
	155	<stbcx.>: Likewise.
	156	<sthcx.>: Likewise.
	157	<waitrsv>: Do not enable for POWER7 and later.
	158	<waitimpl>: Likewise.
	159	<dcbt>: Default to the two operand form of the instruction for all
	160	"old" cpus. For "new" cpus, use the operand ordering that matches
	161	whether the cpu is server or embedded.
	162	<dcbtst>: Likewise.
	163
3b78cfe1 AK	164	2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	165
	166	* s390-opc.c: New instruction type VV0UU2.
	167	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	168	and WFC.
	169
04d824a4 JB	170	2015-04-23 Jan Beulich <jbeulich@suse.com>
	171
	172	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	173	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	174	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	175	(vfpclasspd, vfpclassps): Add %XZ.
	176
09708981 L	177	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	178
	179	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	180	(PREFIX_UD_REPZ): Likewise.
	181	(PREFIX_UD_REPNZ): Likewise.
	182	(PREFIX_UD_DATA): Likewise.
	183	(PREFIX_UD_ADDR): Likewise.
	184	(PREFIX_UD_LOCK): Likewise.
	185
3888916d L	186	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	187
	188	* i386-dis.c (prefix_requirement): Removed.
	189	(print_insn): Don't set prefix_requirement. Check
	190	dp->prefix_requirement instead of prefix_requirement.
	191
f24bcbaa L	192	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	193
	194	PR binutils/17898
	195	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	196	(PREFIX_MOD_0_0FC7_REG_6): This.
	197	(PREFIX_MOD_3_0FC7_REG_6): New.
	198	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	199	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	200	PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
	201	PREFIX_MOD_3_0FC7_REG_7.
	202	(mod_table): Replace PREFIX_0FC7_REG_6 with
	203	PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
	204	PREFIX_MOD_3_0FC7_REG_7.
	205
507bd325 L	206	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	207
	208	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	209	(PREFIX_MANDATORY_REPNZ): Likewise.
	210	(PREFIX_MANDATORY_DATA): Likewise.
	211	(PREFIX_MANDATORY_ADDR): Likewise.
	212	(PREFIX_MANDATORY_LOCK): Likewise.
	213	(PREFIX_MANDATORY): Likewise.
	214	(PREFIX_UD_SHIFT): Set to 8
	215	(PREFIX_UD_REPZ): Updated.
	216	(PREFIX_UD_REPNZ): Likewise.
	217	(PREFIX_UD_DATA): Likewise.
	218	(PREFIX_UD_ADDR): Likewise.
	219	(PREFIX_UD_LOCK): Likewise.
	220	(PREFIX_IGNORED_SHIFT): New.
	221	(PREFIX_IGNORED_REPZ): Likewise.
	222	(PREFIX_IGNORED_REPNZ): Likewise.
	223	(PREFIX_IGNORED_DATA): Likewise.
	224	(PREFIX_IGNORED_ADDR): Likewise.
	225	(PREFIX_IGNORED_LOCK): Likewise.
	226	(PREFIX_OPCODE): Likewise.
	227	(PREFIX_IGNORED): Likewise.
	228	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	229	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	230	(three_byte_table): Likewise.
	231	(mod_table): Likewise.
	232	(mandatory_prefix): Renamed to ...
	233	(prefix_requirement): This.
	234	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	235	Update PREFIX_90 entry.
	236	(get_valid_dis386): Check prefix_requirement to see if a prefix
	237	should be ignored.
	238	(print_insn): Replace mandatory_prefix with prefix_requirement.
	239
f0fba320 RL	240	2015-04-15 Renlin Li <renlin.li@arm.com>
	241
	242	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	243	use it for ssat and ssat16.
	244	(print_insn_thumb32): Add handle case for 'D' control code.
	245
bf890a93 IT	246	2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
	247	H.J. Lu <hongjiu.lu@intel.com>
	248
	249	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	250	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	251	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	252	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	253	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	254	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	255	Fill prefix_requirement field.
	256	(struct dis386): Add prefix_requirement field.
	257	(dis386): Fill prefix_requirement field.
	258	(dis386_twobyte): Ditto.
	259	(twobyte_has_mandatory_prefix_: Remove.
	260	(reg_table): Fill prefix_requirement field.
	261	(prefix_table): Ditto.
	262	(x86_64_table): Ditto.
	263	(three_byte_table): Ditto.
	264	(xop_table): Ditto.
	265	(vex_table): Ditto.
	266	(vex_len_table): Ditto.
	267	(vex_w_table): Ditto.
	268	(mod_table): Ditto.
	269	(bad_opcode): Ditto.
	270	(print_insn): Use prefix_requirement.
	271	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	272	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	273	(float_reg): Ditto.
	274
2f783c1f MF	275	2015-03-30 Mike Frysinger <vapier@gentoo.org>
	276
	277	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
	278
b9d94d62 L	279	2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
	280
	281	* Makefile.in: Regenerated.
	282
27c49e9a AB	283	2015-03-25 Anton Blanchard <anton@samba.org>
	284
	285	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	286	powerpc_opcd_indices and vle_opcd_indices once.
	287
c4e676f1 AB	288	2015-03-25 Anton Blanchard <anton@samba.org>
	289
	290	* ppc-opc.c (powerpc_opcodes): Add slbfee.
	291
823d2571 TG	292	2015-03-24 Terry Guo <terry.guo@arm.com>
	293
	294	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	295	(opcode16): Likewise.
	296	(coprocessor_opcodes): Replace bit with feature struct.
	297	(neon_opcodes): Likewise.
	298	(arm_opcodes): Likewise.
	299	(thumb_opcodes): Likewise.
	300	(thumb32_opcodes): Likewise.
	301	(print_insn_coprocessor): Likewise.
	302	(print_insn_arm): Likewise.
	303	(select_arm_features): Follow new feature struct.
	304
029f3522 GG	305	2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
	306
	307	* i386-dis.c (rm_table): Add clzero.
	308	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	309	Add CPU_CLZERO_FLAGS.
	310	(cpu_flags): Add CpuCLZERO.
	311	* i386-opc.h: Add CpuCLZERO.
	312	* i386-opc.tbl: Add clzero.
	313	* i386-init.h: Re-generated.
	314	* i386-tbl.h: Re-generated.
	315
6914869a AB	316	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	317
	318	* mips-opc.c (decode_mips_operand): Fix constraint issues
	319	with u and y operands.
	320
21e20815 AB	321	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	322
	323	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
	324
6b1d7593 AK	325	2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	326
	327	* s390-opc.c: Add new IBM z13 instructions.
	328	* s390-opc.txt: Likewise.
	329
c8f89a34 JW	330	2015-03-10 Renlin Li <renlin.li@arm.com>
	331
	332	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	333	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	334	related alias.
	335	* aarch64-asm-2.c: Regenerate.
	336	* aarch64-dis-2.c: Likewise.
	337	* aarch64-opc-2.c: Likewise.
	338
d8282f0e JW	339	2015-03-03 Jiong Wang <jiong.wang@arm.com>
	340
	341	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
	342
ac994365 OE	343	2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
	344
	345	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	346	arch_sh_up.
	347	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	348	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
	349
fd63f640 V	350	2015-02-23 Vinay <Vinay.G@kpit.com>
	351
	352	* rl78-decode.opc (MOV): Added space between two operands for
	353	'mov' instruction in index addressing mode.
	354	* rl78-decode.c: Regenerate.
	355
f63c1776 PA	356	2015-02-19 Pedro Alves <palves@redhat.com>
	357
	358	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
	359
07774fcc PA	360	2015-02-10 Pedro Alves <palves@redhat.com>
	361	Tom Tromey <tromey@redhat.com>
	362
	363	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	364	microblaze_and, microblaze_xor.
	365	* microblaze-opc.h (opcodes): Adjust.
	366
3f8107ab AM	367	2015-01-28 James Bowman <james.bowman@ftdichip.com>
	368
	369	* Makefile.am: Add FT32 files.
	370	* configure.ac: Handle FT32.
	371	* disassemble.c (disassembler): Call print_insn_ft32.
	372	* ft32-dis.c: New file.
	373	* ft32-opc.c: New file.
	374	* Makefile.in: Regenerate.
	375	* configure: Regenerate.
	376	* po/POTFILES.in: Regenerate.
	377
e5fe4957 KLC	378	2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
	379
	380	* nds32-asm.c (keyword_sr): Add new system registers.
	381
1e2e8c52 AK	382	2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	383
	384	* s390-dis.c (s390_extract_operand): Support vector register
	385	operands.
	386	(s390_print_insn_with_opcode): Support new operands types and add
	387	new handling of optional operands.
	388	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	389	and include opcode/s390.h instead.
	390	(struct op_struct): New field `flags'.
	391	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	392	(dumpTable): Dump flags.
	393	(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
	394	string.
	395	* s390-opc.c: Add new operands types, instruction formats, and
	396	instruction masks.
	397	(s390_opformats): Add new formats for .insn.
	398	* s390-opc.txt: Add new instructions.
	399
b90efa5b	400	2015-01-01 Alan Modra <amodra@gmail.com>
bffb6004	401
b90efa5b	402	Update year range in copyright notice of all files.
bffb6004	403
b90efa5b	404	For older changes see ChangeLog-2014
252b5132	405	\f
b90efa5b	406	Copyright (C) 2015 Free Software Foundation, Inc.
752937aa NC	407
	408	Copying and distribution of this file, with or without modification,
	409	are permitted in any medium without royalty provided the copyright
	410	notice and this notice are preserved.
	411
252b5132	412	Local Variables:
2f6d2f85 NC	413	mode: change-log
	414	left-margin: 8
	415	fill-column: 74
252b5132 RH	416	version-control: never
252b5132 RH	417	End: