[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2008-04-16  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
	    Michael Meissner  <michael.meissner@amd.com>

	* i386-opc.tbl: Fix protX to allow memory in the middle operand.
	* i386-tbl.h: Regenerate from i386-opc.tbl.
	
2008-04-14  Edmar Wienskoski  <edmar@freescale.com>

	* ppc-dis.c (powerpc_dialect): Handle "e500mc".  Extend "e500" to
	accept Power E500MC instructions.
	(print_ppc_disassembler_options): Document -Me500mc.
	* ppc-opc.c (DUIS, DUI, T): New.
	(XRT, XRTRA): Likewise.
	(E500MC): Likewise.
	(powerpc_opcodes): Add new Power E500MC instructions.

2008-04-10  Andreas Krebbel  <krebbel1@de.ibm.com>

	* s390-dis.c (init_disasm): Evaluate disassembler_options.
	(print_s390_disassembler_options): New function.
	* disassemble.c (disassembler_usage): Invoke
	print_s390_disassembler_options.

2008-04-10  Andreas Krebbel  <krebbel1@de.ibm.com>

	* s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
	of local variables used for mnemonic parsing: prefix, suffix and
	number.

2008-04-10  Andreas Krebbel  <krebbel1@de.ibm.com>

	* s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
	extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
	(s390_crb_extensions): New extensions table.
	(insertExpandedMnemonic): Handle '$' tag.
	* s390-opc.txt: Remove conditional jump variants which can now
	be expanded automatically.
	Replace '*' tag with '$' in the compare and branch instructions.

2008-04-07  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_VEX_38XX): Add a tab.
	(PREFIX_VEX_3AXX): Likewis.

2008-04-07  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove 4 extra blank lines.

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	* i386-opc.tbl: Likewise.

	* i386-opc.h (CpuCLMUL): Renamed to ...
	(CpuPCLMUL): This.
	(CpuFMA): Updated.
	(i386_cpu_flags): Replace cpuclmul with cpupclmul.

	* i386-init.h: Regenerated.

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_register): New.
	(OP_E_memory): Likewise.
	(OP_VEX): Likewise.
	(OP_EX_Vex): Likewise.
	(OP_EX_VexW): Likewise.
	(OP_XMM_Vex): Likewise.
	(OP_XMM_VexW): Likewise.
	(OP_REG_VexI4): Likewise.
	(PCLMUL_Fixup): Likewise.
	(VEXI4_Fixup): Likewise.
	(VZERO_Fixup): Likewise.
	(VCMP_Fixup): Likewise.
	(VPERMIL2_Fixup): Likewise.
	(rex_original): Likewise.
	(rex_ignored): Likewise.
	(Mxmm): Likewise.
	(XMM): Likewise.
	(EXxmm): Likewise.
	(EXxmmq): Likewise.
	(EXymmq): Likewise.
	(Vex): Likewise.
	(Vex128): Likewise.
	(Vex256): Likewise.
	(VexI4): Likewise.
	(EXdVex): Likewise.
	(EXqVex): Likewise.
	(EXVexW): Likewise.
	(EXdVexW): Likewise.
	(EXqVexW): Likewise.
	(XMVex): Likewise.
	(XMVexW): Likewise.
	(XMVexI4): Likewise.
	(PCLMUL): Likewise.
	(VZERO): Likewise.
	(VCMP): Likewise.
	(VPERMIL2): Likewise.
	(xmm_mode): Likewise.
	(xmmq_mode): Likewise.
	(ymmq_mode): Likewise.
	(vex_mode): Likewise.
	(vex128_mode): Likewise.
	(vex256_mode): Likewise.
	(USE_VEX_C4_TABLE): Likewise.
	(USE_VEX_C5_TABLE): Likewise.
	(USE_VEX_LEN_TABLE): Likewise.
	(VEX_C4_TABLE): Likewise.
	(VEX_C5_TABLE): Likewise.
	(VEX_LEN_TABLE): Likewise.
	(REG_VEX_XX): Likewise.
	(MOD_VEX_XXX): Likewise.
	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	(PREFIX_0F3A44): Likewise.
	(PREFIX_0F3ADF): Likewise.
	(PREFIX_VEX_XXX): Likewise.
	(VEX_OF): Likewise.
	(VEX_OF38): Likewise.
	(VEX_OF3A): Likewise.
	(VEX_LEN_XXX): Likewise.
	(vex): Likewise.
	(need_vex): Likewise.
	(need_vex_reg): Likewise.
	(vex_i4_done): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(OP_REG_VexI4): Likewise.
	(vex_cmp_op): Likewise.
	(pclmul_op): Likewise.
	(vpermil2_op): Likewise.
	(m_mode): Updated.
	(es_reg): Likewise.
	(PREFIX_0F38F0): Likewise.
	(PREFIX_0F3A60): Likewise.
	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
	and PREFIX_VEX_XXX entries.
	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
	PREFIX_0F3ADF.
	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
	Add MOD_VEX_XXX entries.
	(ckprefix): Initialize rex_original and rex_ignored.  Store the
	REX byte in rex_original.
	(get_valid_dis386): Handle the implicit prefix in VEX prefix
	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
	calling get_valid_dis386.  Use rex_original and rex_ignored when
	printing out REX.
	(putop): Handle "XY".
	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
	ymmq_mode.
	(OP_E_extended): Updated to use OP_E_register and
	OP_E_memory.
	(OP_XMM): Handle VEX.
	(OP_EX): Likewise.
	(XMM_Fixup): Likewise.
	(CMP_Fixup): Use ARRAY_SIZE.

	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
	(operand_type_init): Add OPERAND_TYPE_REGYMM and
	OPERAND_TYPE_VEX_IMM4.
	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
	VexImmExt and SSE2AVX.
	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.

	* i386-opc.h (CpuAVX): New.
	(CpuAES): Likewise.
	(CpuCLMUL): Likewise.
	(CpuFMA): Likewise.
	(Vex): Likewise.
	(Vex256): Likewise.
	(VexNDS): Likewise.
	(VexNDD): Likewise.
	(VexW0): Likewise.
	(VexW1): Likewise.
	(Vex0F): Likewise.
	(Vex0F38): Likewise.
	(Vex0F3A): Likewise.
	(Vex3Sources): Likewise.
	(VexImmExt): Likewise.
	(SSE2AVX): Likewise.
	(RegYMM): Likewise.
	(Ymmword): Likewise.
	(Vex_Imm4): Likewise.
	(Implicit1stXmm0): Likewise.
	(CpuXsave): Updated.
	(CpuLM): Likewise.
	(ByteOkIntel): Likewise.
	(OldGcc): Likewise.
	(Control): Likewise.
	(Unspecified): Likewise.
	(OTMax): Likewise.
	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
	vex3sources, veximmext and sse2avx.
	(i386_operand_type): Add regymm, ymmword and vex_imm4.

	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.

	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-03-26  Bernd Schmidt  <bernd.schmidt@analog.com>

	From  Robin Getz  <robin.getz@analog.com>
	* bfin-dis.c (bu32): Typedef.
	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	(constant_formats[]): Add uimm32 and huimm16.
	(fmtconst_val): New.
	(uimm32): Define.
	(huimm32): Define.
	(imm16_val): Define.
	(luimm16_val): Define.
	(struct saved_state): Define.
	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	(get_allreg): New.
	(decode_LDIMMhalf_0): Print out the whole register value.

	From Jie Zhang  <jie.zhang@analog.com>
	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	multiply and multiply-accumulate to data register instruction.

	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	c_imm32, c_huimm32e): Define.
	(constant_formats): Add flags for printing decimal, leading spaces, and
	exact symbols.
	(comment, parallel): Add global flags in all disassembly.
	(fmtconst): Take advantage of new flags, and print default in hex.
	(fmtconst_val): Likewise.
	(decode_macfunc): Be consistant with spaces, tabs, comments,
	capitalization in disassembly, fix minor coding style issues.
	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	_print_insn_bfin, print_insn_bfin): Likewise.

2008-03-17  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

	* aclocal.m4: Regenerate.
	* configure: Likewise.
	* Makefile.in: Likewise.

2008-03-13  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2008-03-07  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c (powerpc_opcodes): Order and format.

2008-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	* i386-tbl.h: Regenerated.

2008-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	x86-64.
	* i386-tbl.h: Regenerated.

2008-02-21  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	and Fword for far indirect jmp. Allow Reg16 and Word for near
	indirect jmp on x86-64. Disallow Fword for lcall.
	* i386-tbl.h: Re-generate.

2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>

	* cr16-opc.c  (cr16_num_optab): Defined

2008-02-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c  (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	* i386-init.h: Regenerated.

2008-02-14  Nick Clifton  <nickc@redhat.com>

	PR binutils/5524
	* configure.in (SHARED_LIBADD): Select the correct host specific
	file extension for shared libraries.
	* configure: Regenerate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.h (RegFlat): New.
	* i386-reg.tbl (flat): Add.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (a_mode): New.
	(cond_jump_mode): Adjust.
	(Ma): Change to a_mode.
	(intel_operand_size): Handle a_mode.
	* i386-opc.tbl: Allow Dword and Qword for bound.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-gen.c (process_i386_registers): Process new fields.
	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	unsigned char. Add dw2_regnum and Dw2Inval.
	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	register names.
	* i386-tbl.h: Re-generate.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
	* i386-init.h: Updated.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flags): Add CpuXsave.

	* i386-opc.h (CpuXsave): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpuxsave.

	* i386-dis.c (MOD_0FAE_REG_4): New.
	(RM_0F01_REG_2): Likewise.
	(MOD_0FAE_REG_5): Updated.
	(RM_0F01_REG_3): Likewise.
	(reg_table): Use MOD_0FAE_REG_4.
	(mod_table): Use RM_0F01_REG_2.  Add MOD_0FAE_REG_4.  Updated
	for xrstor.
	(rm_table): Add RM_0F01_REG_2.

	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-02-11  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	* i386-tbl.h: Re-generate.

2008-02-04  H.J. Lu  <hongjiu.lu@intel.com>

	PR 5715
	* configure: Regenerated.

2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>

	* mips-dis.c: Update copyright.
	(mips_arch_choices): Add Octeon.
	* mips-opc.c: Update copyright.
	(IOCT): New macro.
	(mips_builtin_opcodes): Add Octeon instruction synciobdma.

2008-01-29  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c: Support optional L form mtmsr.

2008-01-24  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_extended): Handle r12 like rsp.

2008-01-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	* i386-init.h: Regenerated.

2008-01-23  Tristan Gingold  <gingold@adacore.com>

	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuMMX2): Removed.
	(CpuSSE): Updated.

	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	CPU_SMX_FLAGS.
	* i386-init.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Use Qword on movddup.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (Mx): New.
	(PREFIX_0FC3): Likewise.
	(PREFIX_0FC7_REG_6): Updated.
	(dis386_twobyte): Use PREFIX_0FC3.
	(prefix_table): Add PREFIX_0FC3.  Use Mq on movntq and movntsd.
	Use Mx on movntps, movntpd, movntdq and movntdqa.  Use Md on
	movntss.

2008-01-14  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	(operand_types): Add Mem.

	* i386-opc.h (IntelSyntax): New.
	* i386-opc.h (Mem): New.
	(Byte): Updated.
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Add intelsyntax.
	(i386_operand_type): Add mem.

	* i386-opc.tbl: Remove Reg16 from movnti.  Add sizes to more
	instructions.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-13  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (Byte): Fix a typo.

2008-01-12  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (operand_type_init): Add Dword to
	OPERAND_TYPE_ACC32.  Add Qword to OPERAND_TYPE_ACC64.
	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	Qword and Xmmword.
	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	Xmmword, Unspecified and Anysize.
	(set_bitfield): Make Mmword an alias of Qword.  Make Oword
	an alias of Xmmword.

	* i386-opc.h (CheckSize): Removed.
	(Byte): Updated.
	(Word): Likewise.
	(Dword): Likewise.
	(Qword): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(OTMax): Likewise.
	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	qword and xmmword.
	(Fword): New.
	(TBYTE): Likewise.
	(Unspecified): Likewise.
	(Anysize): Likewise.
	(i386_operand_type): Add byte, word, dword, fword, qword,
	tbyte xmmword, unspecified and anysize.

	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	Tbyte, Xmmword, Unspecified and Anysize.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-10  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	(REG_0F18): Updated.
	(reg_table): Updated.
	(dis386_twobyte): Updated.  Use "nopQ" on 0x19 to 0x1e.
	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (set_bitfield): Use fail () on error.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (lineno): New.
	(filename): Likewise.
	(set_bitfield): Report filename and line numer on error.
	(process_i386_opcodes): Set filename and update lineno.
	(process_i386_registers): Likewise.

2008-01-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	ATTSyntax.

	* i386-opc.h (IntelMnemonic): Renamed to ..
	(ATTSyntax): This
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	and intelsyntax.

	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax 
	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	* i386-tbl.h: Regenerated.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c: Update copyright to 2008.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	* i386-tbl.h: Regenerated.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	CpuSSE4_2_Or_ABM.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	(CpuSSE4_2_Or_ABM): Likewise.
	(CpuLM): Updated.
	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.

	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
	and CpuPadLock, respectively.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove No_xSuf.

	* i386-opc.h (No_xSuf): Removed.
	(CheckSize): Updated.

	* i386-tbl.h: Regenerated.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	CPU_SSE5_FLAGS.
	(cpu_flags): Add CpuSSE4_2_Or_ABM.

	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpusse4_2_or_abm.

	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	CpuABM|CpuSSE4_2 on popcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h: Update comments.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	Byte, Word, Dword, QWord and Xmmword.

	* i386-opc.h (No_xSuf): New.
	(CheckSize): Likewise.
	(Byte): Likewise.
	(Word): Likewise.
	(Dword): Likewise.
	(QWord): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	Dword, QWord and Xmmword.

	* i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
	used.
	* i386-tbl.h: Regenerated.

2008-01-02  Mark Kettenis  <kettenis@gnu.org>

	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	From Miod Vallat.

For older changes see ChangeLog-2007
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
ce886ab1 DR	1	2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
	2	Michael Meissner <michael.meissner@amd.com>
	3
	4	* i386-opc.tbl: Fix protX to allow memory in the middle operand.
	5	* i386-tbl.h: Regenerate from i386-opc.tbl.
	6
19a6653c AM	7	2008-04-14 Edmar Wienskoski <edmar@freescale.com>
	8
	9	* ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
	10	accept Power E500MC instructions.
	11	(print_ppc_disassembler_options): Document -Me500mc.
	12	* ppc-opc.c (DUIS, DUI, T): New.
	13	(XRT, XRTRA): Likewise.
	14	(E500MC): Likewise.
	15	(powerpc_opcodes): Add new Power E500MC instructions.
	16
112b7c50 AK	17	2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
	18
	19	* s390-dis.c (init_disasm): Evaluate disassembler_options.
	20	(print_s390_disassembler_options): New function.
	21	* disassemble.c (disassembler_usage): Invoke
	22	print_s390_disassembler_options.
	23
7ff42648 AK	24	2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
	25
	26	* s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
	27	of local variables used for mnemonic parsing: prefix, suffix and
	28	number.
	29
45a5551e AK	30	2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
	31
	32	* s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
	33	extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
	34	(s390_crb_extensions): New extensions table.
	35	(insertExpandedMnemonic): Handle '$' tag.
	36	* s390-opc.txt: Remove conditional jump variants which can now
	37	be expanded automatically.
	38	Replace '*' tag with '$' in the compare and branch instructions.
	39
06c8514a L	40	2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
	41
	42	* i386-dis.c (PREFIX_VEX_38XX): Add a tab.
	43	(PREFIX_VEX_3AXX): Likewis.
	44
b122c285 L	45	2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
	46
	47	* i386-opc.tbl: Remove 4 extra blank lines.
	48
594ab6a3 L	49	2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
	50
	51	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	52	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	53	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	54	* i386-opc.tbl: Likewise.
	55
	56	* i386-opc.h (CpuCLMUL): Renamed to ...
	57	(CpuPCLMUL): This.
	58	(CpuFMA): Updated.
	59	(i386_cpu_flags): Replace cpuclmul with cpupclmul.
	60
	61	* i386-init.h: Regenerated.
	62
c0f3af97 L	63	2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
	64
	65	* i386-dis.c (OP_E_register): New.
	66	(OP_E_memory): Likewise.
	67	(OP_VEX): Likewise.
	68	(OP_EX_Vex): Likewise.
	69	(OP_EX_VexW): Likewise.
	70	(OP_XMM_Vex): Likewise.
	71	(OP_XMM_VexW): Likewise.
	72	(OP_REG_VexI4): Likewise.
	73	(PCLMUL_Fixup): Likewise.
	74	(VEXI4_Fixup): Likewise.
	75	(VZERO_Fixup): Likewise.
	76	(VCMP_Fixup): Likewise.
	77	(VPERMIL2_Fixup): Likewise.
	78	(rex_original): Likewise.
	79	(rex_ignored): Likewise.
	80	(Mxmm): Likewise.
	81	(XMM): Likewise.
	82	(EXxmm): Likewise.
	83	(EXxmmq): Likewise.
	84	(EXymmq): Likewise.
	85	(Vex): Likewise.
	86	(Vex128): Likewise.
	87	(Vex256): Likewise.
	88	(VexI4): Likewise.
	89	(EXdVex): Likewise.
	90	(EXqVex): Likewise.
	91	(EXVexW): Likewise.
	92	(EXdVexW): Likewise.
	93	(EXqVexW): Likewise.
	94	(XMVex): Likewise.
	95	(XMVexW): Likewise.
	96	(XMVexI4): Likewise.
	97	(PCLMUL): Likewise.
	98	(VZERO): Likewise.
	99	(VCMP): Likewise.
	100	(VPERMIL2): Likewise.
	101	(xmm_mode): Likewise.
	102	(xmmq_mode): Likewise.
	103	(ymmq_mode): Likewise.
	104	(vex_mode): Likewise.
	105	(vex128_mode): Likewise.
	106	(vex256_mode): Likewise.
	107	(USE_VEX_C4_TABLE): Likewise.
	108	(USE_VEX_C5_TABLE): Likewise.
	109	(USE_VEX_LEN_TABLE): Likewise.
	110	(VEX_C4_TABLE): Likewise.
	111	(VEX_C5_TABLE): Likewise.
	112	(VEX_LEN_TABLE): Likewise.
	113	(REG_VEX_XX): Likewise.
	114	(MOD_VEX_XXX): Likewise.
	115	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	116	(PREFIX_0F3A44): Likewise.
	117	(PREFIX_0F3ADF): Likewise.
	118	(PREFIX_VEX_XXX): Likewise.
	119	(VEX_OF): Likewise.
	120	(VEX_OF38): Likewise.
	121	(VEX_OF3A): Likewise.
	122	(VEX_LEN_XXX): Likewise.
	123	(vex): Likewise.
	124	(need_vex): Likewise.
	125	(need_vex_reg): Likewise.
	126	(vex_i4_done): Likewise.
127	(vex_table): Likewise.
128	(vex_len_table): Likewise.
129	(OP_REG_VexI4): Likewise.
130	(vex_cmp_op): Likewise.
131	(pclmul_op): Likewise.
132	(vpermil2_op): Likewise.
133	(m_mode): Updated.
134	(es_reg): Likewise.
135	(PREFIX_0F38F0): Likewise.
136	(PREFIX_0F3A60): Likewise.
137	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
138	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
139	and PREFIX_VEX_XXX entries.
140	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
141	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
142	PREFIX_0F3ADF.
143	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
144	Add MOD_VEX_XXX entries.
145	(ckprefix): Initialize rex_original and rex_ignored. Store the
146	REX byte in rex_original.
147	(get_valid_dis386): Handle the implicit prefix in VEX prefix
148	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
149	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
150	calling get_valid_dis386. Use rex_original and rex_ignored when
151	printing out REX.
152	(putop): Handle "XY".
153	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
154	ymmq_mode.
155	(OP_E_extended): Updated to use OP_E_register and
156	OP_E_memory.
157	(OP_XMM): Handle VEX.
158	(OP_EX): Likewise.
159	(XMM_Fixup): Likewise.
160	(CMP_Fixup): Use ARRAY_SIZE.
161
162	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
163	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
164	(operand_type_init): Add OPERAND_TYPE_REGYMM and
165	OPERAND_TYPE_VEX_IMM4.
166	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
167	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
168	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
169	VexImmExt and SSE2AVX.
170	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
171
172	* i386-opc.h (CpuAVX): New.
173	(CpuAES): Likewise.
174	(CpuCLMUL): Likewise.
175	(CpuFMA): Likewise.
176	(Vex): Likewise.
177	(Vex256): Likewise.
178	(VexNDS): Likewise.
179	(VexNDD): Likewise.
180	(VexW0): Likewise.
181	(VexW1): Likewise.
182	(Vex0F): Likewise.
183	(Vex0F38): Likewise.
184	(Vex0F3A): Likewise.
185	(Vex3Sources): Likewise.
186	(VexImmExt): Likewise.
187	(SSE2AVX): Likewise.
188	(RegYMM): Likewise.
189	(Ymmword): Likewise.
190	(Vex_Imm4): Likewise.
191	(Implicit1stXmm0): Likewise.
192	(CpuXsave): Updated.
193	(CpuLM): Likewise.
194	(ByteOkIntel): Likewise.
195	(OldGcc): Likewise.
196	(Control): Likewise.
197	(Unspecified): Likewise.
198	(OTMax): Likewise.
199	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
200	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
201	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
202	vex3sources, veximmext and sse2avx.
203	(i386_operand_type): Add regymm, ymmword and vex_imm4.
204
205	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
206
207	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
208
209	* i386-init.h: Regenerated.
210	* i386-tbl.h: Likewise.
211
b21c9cb4 BS	212	2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
	213
	214	From Robin Getz <robin.getz@analog.com>
	215	* bfin-dis.c (bu32): Typedef.
	216	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	217	(constant_formats[]): Add uimm32 and huimm16.
	218	(fmtconst_val): New.
	219	(uimm32): Define.
	220	(huimm32): Define.
	221	(imm16_val): Define.
	222	(luimm16_val): Define.
	223	(struct saved_state): Define.
	224	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	225	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	226	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	227	(get_allreg): New.
	228	(decode_LDIMMhalf_0): Print out the whole register value.
	229
ee171c8f BS	230	From Jie Zhang <jie.zhang@analog.com>
	231	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	232	multiply and multiply-accumulate to data register instruction.
	233
086134ec BS	234	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	235	c_imm32, c_huimm32e): Define.
	236	(constant_formats): Add flags for printing decimal, leading spaces, and
	237	exact symbols.
	238	(comment, parallel): Add global flags in all disassembly.
	239	(fmtconst): Take advantage of new flags, and print default in hex.
	240	(fmtconst_val): Likewise.
	241	(decode_macfunc): Be consistant with spaces, tabs, comments,
	242	capitalization in disassembly, fix minor coding style issues.
	243	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	244	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	245	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	246	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	247	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	248	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	249	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	250	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	251	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	252	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	253	_print_insn_bfin, print_insn_bfin): Likewise.
	254
58c85be7 RW	255	2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
	256
	257	* aclocal.m4: Regenerate.
	258	* configure: Likewise.
	259	* Makefile.in: Likewise.
	260
50e7d84b AM	261	2008-03-13 Alan Modra <amodra@bigpond.net.au>
	262
	263	* Makefile.am: Run "make dep-am".
	264	* Makefile.in: Regenerate.
	265	* configure: Regenerate.
	266
de866fcc AM	267	2008-03-07 Alan Modra <amodra@bigpond.net.au>
	268
	269	* ppc-opc.c (powerpc_opcodes): Order and format.
	270
28dbc079 L	271	2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
	272
	273	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	274	* i386-tbl.h: Regenerated.
	275
849830bd L	276	2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
	277
	278	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	279	x86-64.
	280	* i386-tbl.h: Regenerated.
	281
743ddb6b JB	282	2008-02-21 Jan Beulich <jbeulich@novell.com>
	283
	284	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	285	and Fword for far indirect jmp. Allow Reg16 and Word for near
	286	indirect jmp on x86-64. Disallow Fword for lcall.
	287	* i386-tbl.h: Re-generate.
	288
796d5313 NC	289	2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
	290
	291	* cr16-opc.c (cr16_num_optab): Defined
	292
65da13b5 L	293	2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
	294
	295	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	296	* i386-init.h: Regenerated.
	297
0e336180 NC	298	2008-02-14 Nick Clifton <nickc@redhat.com>
	299
	300	PR binutils/5524
	301	* configure.in (SHARED_LIBADD): Select the correct host specific
	302	file extension for shared libraries.
	303	* configure: Regenerate.
	304
b7240065 JB	305	2008-02-13 Jan Beulich <jbeulich@novell.com>
	306
	307	* i386-opc.h (RegFlat): New.
	308	* i386-reg.tbl (flat): Add.
	309	* i386-tbl.h: Re-generate.
	310
34b772a6 JB	311	2008-02-13 Jan Beulich <jbeulich@novell.com>
	312
	313	* i386-dis.c (a_mode): New.
	314	(cond_jump_mode): Adjust.
	315	(Ma): Change to a_mode.
	316	(intel_operand_size): Handle a_mode.
	317	* i386-opc.tbl: Allow Dword and Qword for bound.
	318	* i386-tbl.h: Re-generate.
	319
a60de03c JB	320	2008-02-13 Jan Beulich <jbeulich@novell.com>
	321
	322	* i386-gen.c (process_i386_registers): Process new fields.
	323	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	324	unsigned char. Add dw2_regnum and Dw2Inval.
	325	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	326	register names.
	327	* i386-tbl.h: Re-generate.
	328
f03fe4c1 L	329	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
f03fe4c1 L	330
4b6bc8eb	331	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1 L	332	* i386-init.h: Updated.
f03fe4c1 L	333
475a2301 L	334	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
	335
	336	* i386-gen.c (cpu_flags): Add CpuXsave.
	337
	338	* i386-opc.h (CpuXsave): New.
4b6bc8eb	339	(CpuLM): Updated.
475a2301 L	340	(i386_cpu_flags): Add cpuxsave.
	341
	342	* i386-dis.c (MOD_0FAE_REG_4): New.
	343	(RM_0F01_REG_2): Likewise.
	344	(MOD_0FAE_REG_5): Updated.
	345	(RM_0F01_REG_3): Likewise.
	346	(reg_table): Use MOD_0FAE_REG_4.
	347	(mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
	348	for xrstor.
	349	(rm_table): Add RM_0F01_REG_2.
	350
	351	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	352	* i386-init.h: Regenerated.
	353	* i386-tbl.h: Likewise.
	354
595785c6	355	2008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc	356
595785c6 JB	357	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	358	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	359	* i386-tbl.h: Re-generate.
	360
bb8541b9 L	361	2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
	362
	363	PR 5715
	364	* configure: Regenerated.
	365
57b592a3 AN	366	2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
	367
	368	* mips-dis.c: Update copyright.
	369	(mips_arch_choices): Add Octeon.
	370	* mips-opc.c: Update copyright.
	371	(IOCT): New macro.
	372	(mips_builtin_opcodes): Add Octeon instruction synciobdma.
	373
930bb4cf AM	374	2008-01-29 Alan Modra <amodra@bigpond.net.au>
	375
	376	* ppc-opc.c: Support optional L form mtmsr.
	377
82c18208 L	378	2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
	379
	380	* i386-dis.c (OP_E_extended): Handle r12 like rsp.
	381
599121aa L	382	2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
	383
	384	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	385	* i386-init.h: Regenerated.
	386
80098f51 TG	387	2008-01-23 Tristan Gingold <gingold@adacore.com>
	388
	389	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	390	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
	391
115c7c25 L	392	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	393
	394	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	395	(cpu_flags): Likewise.
	396
	397	* i386-opc.h (CpuMMX2): Removed.
	398	(CpuSSE): Updated.
	399
	400	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE\|Cpu3dnowA.
	401	* i386-init.h: Regenerated.
	402	* i386-tbl.h: Likewise.
	403
6305a203 L	404	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	405
	406	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	407	CPU_SMX_FLAGS.
	408	* i386-init.h: Regenerated.
	409
fd07a1c8 L	410	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	411
	412	* i386-opc.tbl: Use Qword on movddup.
	413	* i386-tbl.h: Regenerated.
	414
321fd21e L	415	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	416
	417	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	418	* i386-tbl.h: Regenerated.
	419
4ee52178 L	420	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	421
	422	* i386-dis.c (Mx): New.
	423	(PREFIX_0FC3): Likewise.
	424	(PREFIX_0FC7_REG_6): Updated.
	425	(dis386_twobyte): Use PREFIX_0FC3.
	426	(prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
	427	Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
	428	movntss.
	429
5c07affc L	430	2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
	431
	432	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	433	(operand_types): Add Mem.
	434
	435	* i386-opc.h (IntelSyntax): New.
	436	* i386-opc.h (Mem): New.
	437	(Byte): Updated.
	438	(Opcode_Modifier_Max): Updated.
	439	(i386_opcode_modifier): Add intelsyntax.
	440	(i386_operand_type): Add mem.
	441
	442	* i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
	443	instructions.
	444
	445	* i386-reg.tbl: Add size for accumulator.
	446
	447	* i386-init.h: Regenerated.
	448	* i386-tbl.h: Likewise.
	449
0d6a2f58 L	450	2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
	451
	452	* i386-opc.h (Byte): Fix a typo.
	453
7d5e4556 L	454	2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
	455
	456	PR gas/5534
	457	* i386-gen.c (operand_type_init): Add Dword to
	458	OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
	459	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	460	Qword and Xmmword.
	461	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	462	Xmmword, Unspecified and Anysize.
	463	(set_bitfield): Make Mmword an alias of Qword. Make Oword
	464	an alias of Xmmword.
	465
	466	* i386-opc.h (CheckSize): Removed.
	467	(Byte): Updated.
	468	(Word): Likewise.
	469	(Dword): Likewise.
	470	(Qword): Likewise.
	471	(Xmmword): Likewise.
	472	(FWait): Updated.
	473	(OTMax): Likewise.
	474	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	475	qword and xmmword.
	476	(Fword): New.
	477	(TBYTE): Likewise.
	478	(Unspecified): Likewise.
	479	(Anysize): Likewise.
	480	(i386_operand_type): Add byte, word, dword, fword, qword,
	481	tbyte xmmword, unspecified and anysize.
	482
	483	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	484	Tbyte, Xmmword, Unspecified and Anysize.
	485
	486	* i386-reg.tbl: Add size for accumulator.
	487
	488	* i386-init.h: Regenerated.
	489	* i386-tbl.h: Likewise.
	490
b5b1fc4f L	491	2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
	492
	493	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	494	(REG_0F18): Updated.
	495	(reg_table): Updated.
	496	(dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
	497	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
	498
50e8458f L	499	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	500
	501	* i386-gen.c (set_bitfield): Use fail () on error.
	502
3d4d5afa L	503	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	504
	505	* i386-gen.c (lineno): New.
	506	(filename): Likewise.
	507	(set_bitfield): Report filename and line numer on error.
	508	(process_i386_opcodes): Set filename and update lineno.
	509	(process_i386_registers): Likewise.
	510
e1d4d893 L	511	2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
	512
	513	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	514	ATTSyntax.
	515
	516	* i386-opc.h (IntelMnemonic): Renamed to ..
	517	(ATTSyntax): This
	518	(Opcode_Modifier_Max): Updated.
	519	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	520	and intelsyntax.
	521
	522	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
	523	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	524	* i386-tbl.h: Regenerated.
	525
6f143e4d L	526	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	527
	528	* i386-gen.c: Update copyright to 2008.
	529	* i386-opc.h: Likewise.
	530	* i386-opc.tbl: Likewise.
	531
	532	* i386-init.h: Regenerated.
	533	* i386-tbl.h: Likewise.
	534
c6add537 L	535	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	536
	537	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	538	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	539	* i386-tbl.h: Regenerated.
	540
3629bb00 L	541	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	542
	543	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	544	CpuSSE4_2_Or_ABM.
	545	(cpu_flags): Likewise.
	546
	547	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	548	(CpuSSE4_2_Or_ABM): Likewise.
	549	(CpuLM): Updated.
	550	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
	551
	552	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	553	Cpu686\|CpuPadLock with CpuSSE4_1\|CpuSSE5, CpuABM\|CpuSSE4_2
	554	and CpuPadLock, respectively.
	555	* i386-init.h: Regenerated.
	556	* i386-tbl.h: Likewise.
	557
24995bd6 L	558	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	559
	560	* i386-gen.c (opcode_modifiers): Remove No_xSuf.
	561
	562	* i386-opc.h (No_xSuf): Removed.
	563	(CheckSize): Updated.
	564
	565	* i386-tbl.h: Regenerated.
	566
e0329a22 L	567	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	568
	569	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	570	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	571	CPU_SSE5_FLAGS.
	572	(cpu_flags): Add CpuSSE4_2_Or_ABM.
	573
	574	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	575	(CpuLM): Updated.
	576	(i386_cpu_flags): Add cpusse4_2_or_abm.
	577
	578	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	579	CpuABM\|CpuSSE4_2 on popcnt.
	580	* i386-init.h: Regenerated.
	581	* i386-tbl.h: Likewise.
	582
f2a9c676 L	583	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	584
	585	* i386-opc.h: Update comments.
	586
d978b5be L	587	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	588
	589	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	590	* i386-opc.h: Likewise.
	591	* i386-opc.tbl: Likewise.
	592
582d5edd L	593	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	594
	595	PR gas/5534
	596	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	597	Byte, Word, Dword, QWord and Xmmword.
	598
	599	* i386-opc.h (No_xSuf): New.
	600	(CheckSize): Likewise.
	601	(Byte): Likewise.
	602	(Word): Likewise.
	603	(Dword): Likewise.
	604	(QWord): Likewise.
	605	(Xmmword): Likewise.
	606	(FWait): Updated.
	607	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	608	Dword, QWord and Xmmword.
	609
	610	* i386-opc.tbl: Add CheckSize\|QWord to movq if IgnoreSize is
	611	used.
	612	* i386-tbl.h: Regenerated.
	613
3fe15143 MK	614	2008-01-02 Mark Kettenis <kettenis@gnu.org>
	615
	616	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	617	From Miod Vallat.
	618
6c7ac64e	619	For older changes see ChangeLog-2007
252b5132 RH	620	\f
252b5132 RH	621	Local Variables:
2f6d2f85 NC	622	mode: change-log
	623	left-margin: 8
	624	fill-column: 74
252b5132 RH	625	version-control: never
252b5132 RH	626	End: