[AArch64] Add ARMv8.3 weaker release consistency load instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
28617675
SN
12016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
2
3 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
4 * aarch64-asm-2.c: Regenerate.
5 * aarch64-dis-2.c: Regenerate.
6 * aarch64-opc-2.c: Regenerate.
7
ccfc90a3
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82016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
9
10 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
11 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
12 * aarch64-asm-2.c: Regenerate.
13 * aarch64-dis-2.c: Regenerate.
14 * aarch64-opc-2.c: Regenerate.
15
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162016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
17
18 * aarch64-tbl.h (QL_X1NIL): New.
19 (arch64_opcode_table): Add ldraa, ldrab.
20 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
21 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
22 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
23 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
24 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
25 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
26 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
27 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
28 (aarch64_print_operand): Likewise.
29 * aarch64-asm-2.c: Regenerate.
30 * aarch64-dis-2.c: Regenerate.
31 * aarch64-opc-2.c: Regenerate.
32
74f5402d
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332016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
34
35 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
36 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
37 * aarch64-asm-2.c: Regenerate.
38 * aarch64-dis-2.c: Regenerate.
39 * aarch64-opc-2.c: Regenerate.
40
c84364ec
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412016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
42
43 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
44 (AARCH64_OPERANDS): Add Rm_SP.
45 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
46 * aarch64-asm-2.c: Regenerate.
47 * aarch64-dis-2.c: Regenerate.
48 * aarch64-opc-2.c: Regenerate.
49
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502016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
51
52 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
53 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
54 autdzb, xpaci, xpacd.
55 * aarch64-asm-2.c: Regenerate.
56 * aarch64-dis-2.c: Regenerate.
57 * aarch64-opc-2.c: Regenerate.
58
b0bfa7b5
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592016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
60
61 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
62 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
63 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
64 (aarch64_sys_reg_supported_p): Add feature test for new registers.
65
8787d804
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662016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
67
68 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
69 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
70 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
71 autibsp.
72 * aarch64-asm-2.c: Regenerate.
73 * aarch64-dis-2.c: Regenerate.
74
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752016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
76
77 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
78
60227d64
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792016-11-09 H.J. Lu <hongjiu.lu@intel.com>
80
81 PR binutils/20799
82 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
83 * i386-dis.c (EdqwS): Removed.
84 (dqw_swap_mode): Likewise.
85 (intel_operand_size): Don't check dqw_swap_mode.
86 (OP_E_register): Likewise.
87 (OP_E_memory): Likewise.
88 (OP_G): Likewise.
89 (OP_EX): Likewise.
90 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
91 * i386-tbl.h: Regerated.
92
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932016-11-09 H.J. Lu <hongjiu.lu@intel.com>
94
95 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 96 * i386-tbl.h: Regerated.
7efeed17 97
1f334aeb
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982016-11-08 H.J. Lu <hongjiu.lu@intel.com>
99
100 PR binutils/20701
101 * i386-dis.c (THREE_BYTE_0F7A): Removed.
102 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
103 (three_byte_table): Remove THREE_BYTE_0F7A.
104
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1052016-11-07 H.J. Lu <hongjiu.lu@intel.com>
106
107 PR binutils/20775
108 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
109 (FGRPd9_4): Replace 1 with 2.
110 (FGRPd9_5): Replace 2 with 3.
111 (FGRPd9_6): Replace 3 with 4.
112 (FGRPd9_7): Replace 4 with 5.
113 (FGRPda_5): Replace 5 with 6.
114 (FGRPdb_4): Replace 6 with 7.
115 (FGRPde_3): Replace 7 with 8.
116 (FGRPdf_4): Replace 8 with 9.
117 (fgrps): Add an entry for Bad_Opcode.
118
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1192016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
120
121 * arc-opc.c (arc_flag_operands): Add F_DI14.
122 (arc_flag_classes): Add C_DI14.
123 * arc-nps400-tbl.h: Add new exc instructions.
124
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1252016-11-03 Graham Markall <graham.markall@embecosm.com>
126
127 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
128 major opcode 0xa.
129 * arc-nps-400-tbl.h: Add dcmac instruction.
130 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
131 (insert_nps_rbdouble_64): Added.
132 (extract_nps_rbdouble_64): Added.
133 (insert_nps_proto_size): Added.
134 (extract_nps_proto_size): Added.
135
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1362016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
137
138 * arc-dis.c (struct arc_operand_iterator): Remove all fields
139 relating to long instruction processing, add new limm field.
140 (OPCODE): Rename to...
141 (OPCODE_32BIT_INSN): ...this.
142 (OPCODE_AC): Delete.
143 (skip_this_opcode): Handle different instruction lengths, update
144 macro name.
145 (special_flag_p): Update parameter type.
146 (find_format_from_table): Update for more instruction lengths.
147 (find_format_long_instructions): Delete.
148 (find_format): Update for more instruction lengths.
149 (arc_insn_length): Likewise.
150 (extract_operand_value): Update for more instruction lengths.
151 (operand_iterator_next): Remove code relating to long
152 instructions.
153 (arc_opcode_to_insn_type): New function.
154 (print_insn_arc):Update for more instructions lengths.
155 * arc-ext.c (extInstruction_t): Change argument type.
156 * arc-ext.h (extInstruction_t): Change argument type.
157 * arc-fxi.h: Change type unsigned to unsigned long long
158 extensively throughout.
159 * arc-nps400-tbl.h: Add long instructions taken from
160 arc_long_opcodes table in arc-opc.c.
161 * arc-opc.c: Update parameter types on insert/extract handlers.
162 (arc_long_opcodes): Delete.
163 (arc_num_long_opcodes): Delete.
164 (arc_opcode_len): Update for more instruction lengths.
165
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1662016-11-03 Graham Markall <graham.markall@embecosm.com>
167
168 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
169
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1702016-11-03 Graham Markall <graham.markall@embecosm.com>
171
172 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
173 with arc_opcode_len.
174 (find_format_long_instructions): Likewise.
175 * arc-opc.c (arc_opcode_len): New function.
176
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1772016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
178
179 * arc-nps400-tbl.h: Fix some instruction masks.
180
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1812016-11-03 H.J. Lu <hongjiu.lu@intel.com>
182
183 * i386-dis.c (REG_82): Removed.
184 (X86_64_82_REG_0): Likewise.
185 (X86_64_82_REG_1): Likewise.
186 (X86_64_82_REG_2): Likewise.
187 (X86_64_82_REG_3): Likewise.
188 (X86_64_82_REG_4): Likewise.
189 (X86_64_82_REG_5): Likewise.
190 (X86_64_82_REG_6): Likewise.
191 (X86_64_82_REG_7): Likewise.
192 (X86_64_82): New.
193 (dis386): Use X86_64_82 instead of REG_82.
194 (reg_table): Remove REG_82.
195 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
196 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
197 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
198 X86_64_82_REG_7.
199
8b89fe14
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2002016-11-03 H.J. Lu <hongjiu.lu@intel.com>
201
202 PR binutils/20754
203 * i386-dis.c (REG_82): New.
204 (X86_64_82_REG_0): Likewise.
205 (X86_64_82_REG_1): Likewise.
206 (X86_64_82_REG_2): Likewise.
207 (X86_64_82_REG_3): Likewise.
208 (X86_64_82_REG_4): Likewise.
209 (X86_64_82_REG_5): Likewise.
210 (X86_64_82_REG_6): Likewise.
211 (X86_64_82_REG_7): Likewise.
212 (dis386): Use REG_82.
213 (reg_table): Add REG_82.
214 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
215 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
216 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
217
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2182016-11-03 H.J. Lu <hongjiu.lu@intel.com>
219
220 * i386-dis.c (REG_82): Renamed to ...
221 (REG_83): This.
222 (dis386): Updated.
223 (reg_table): Likewise.
224
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2252016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
226
227 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
228 * i386-dis-evex.h (evex_table): Updated.
229 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
230 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
231 (cpu_flags): Add CpuAVX512_4VNNIW.
232 * i386-opc.h (enum): (AVX512_4VNNIW): New.
233 (i386_cpu_flags): Add cpuavx512_4vnniw.
234 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
235 * i386-init.h: Regenerate.
236 * i386-tbl.h: Ditto.
237
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2382016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
239
240 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
241 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
242 * i386-dis-evex.h (evex_table): Updated.
243 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
244 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
245 (cpu_flags): Add CpuAVX512_4FMAPS.
246 (opcode_modifiers): Add ImplicitQuadGroup modifier.
247 * i386-opc.h (AVX512_4FMAP): New.
248 (i386_cpu_flags): Add cpuavx512_4fmaps.
249 (ImplicitQuadGroup): New.
250 (i386_opcode_modifier): Add implicitquadgroup.
251 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
252 * i386-init.h: Regenerate.
253 * i386-tbl.h: Ditto.
254
e23eba97
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2552016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
256 Andrew Waterman <andrew@sifive.com>
257
258 Add support for RISC-V architecture.
259 * configure.ac: Add entry for bfd_riscv_arch.
260 * configure: Regenerate.
261 * disassemble.c (disassembler): Add support for riscv.
262 (disassembler_usage): Likewise.
263 * riscv-dis.c: New file.
264 * riscv-opc.c: New file.
265
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2662016-10-21 H.J. Lu <hongjiu.lu@intel.com>
267
268 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
269 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
270 (rm_table): Update the RM_0FAE_REG_7 entry.
271 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
272 (cpu_flags): Remove CpuPCOMMIT.
273 * i386-opc.h (CpuPCOMMIT): Removed.
274 (i386_cpu_flags): Remove cpupcommit.
275 * i386-opc.tbl: Remove pcommit.
276 * i386-init.h: Regenerated.
277 * i386-tbl.h: Likewise.
278
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2792016-10-20 H.J. Lu <hongjiu.lu@intel.com>
280
281 PR binutis/20705
282 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
283 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
284 32-bit mode. Don't check vex.register_specifier in 32-bit
285 mode.
286 (OP_VEX): Check for invalid mask registers.
287
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2882016-10-18 H.J. Lu <hongjiu.lu@intel.com>
289
290 PR binutis/20699
291 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
292 sizeflag.
293
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2942016-10-18 H.J. Lu <hongjiu.lu@intel.com>
295
296 PR binutis/20704
297 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
298
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MR
2992016-10-18 Maciej W. Rozycki <macro@imgtec.com>
300
301 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
302 local variable to `index_regno'.
303
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3042016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
305
306 * arc-tbl.h: Removed any "inv.+" instructions from the table.
307
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CZ
3082016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
309
310 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
311 usage on ISA basis.
312
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JW
3132016-10-11 Jiong Wang <jiong.wang@arm.com>
314
315 PR target/20666
316 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
317
362c0c4d
JW
3182016-10-07 Jiong Wang <jiong.wang@arm.com>
319
320 PR target/20667
321 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
322 available.
323
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3242016-10-07 Alan Modra <amodra@gmail.com>
325
326 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
327
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3282016-10-06 Alan Modra <amodra@gmail.com>
329
330 * aarch64-opc.c: Spell fall through comments consistently.
331 * i386-dis.c: Likewise.
332 * aarch64-dis.c: Add missing fall through comments.
333 * aarch64-opc.c: Likewise.
334 * arc-dis.c: Likewise.
335 * arm-dis.c: Likewise.
336 * i386-dis.c: Likewise.
337 * m68k-dis.c: Likewise.
338 * mep-asm.c: Likewise.
339 * ns32k-dis.c: Likewise.
340 * sh-dis.c: Likewise.
341 * tic4x-dis.c: Likewise.
342 * tic6x-dis.c: Likewise.
343 * vax-dis.c: Likewise.
344
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AM
3452016-10-06 Alan Modra <amodra@gmail.com>
346
347 * arc-ext.c (create_map): Add missing break.
348 * msp430-decode.opc (encode_as): Likewise.
349 * msp430-decode.c: Regenerate.
350
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AM
3512016-10-06 Alan Modra <amodra@gmail.com>
352
353 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
354 * crx-dis.c (print_insn_crx): Likewise.
355
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3562016-09-30 H.J. Lu <hongjiu.lu@intel.com>
357
358 PR binutils/20657
359 * i386-dis.c (putop): Don't assign alt twice.
360
744ce302
JW
3612016-09-29 Jiong Wang <jiong.wang@arm.com>
362
363 PR target/20553
364 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
365
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3662016-09-29 Alan Modra <amodra@gmail.com>
367
368 * ppc-opc.c (L): Make compulsory.
369 (LOPT): New, optional form of L.
370 (HTM_R): Define as LOPT.
371 (L0, L1): Delete.
372 (L32OPT): New, optional for 32-bit L.
373 (L2OPT): New, 2-bit L for dcbf.
374 (SVC_LEC): Update.
375 (L2): Define.
376 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
377 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
378 <dcbf>: Use L2OPT.
379 <tlbiel, tlbie>: Use LOPT.
380 <wclr, wclrall>: Use L2.
381
c5da1932
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3822016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
383
384 * Makefile.in: Regenerate.
385 * configure: Likewise.
386
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3872016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
388
389 * arc-ext-tbl.h (EXTINSN2OPF): Define.
390 (EXTINSN2OP): Use EXTINSN2OPF.
391 (bspeekm, bspop, modapp): New extension instructions.
392 * arc-opc.c (F_DNZ_ND): Define.
393 (F_DNZ_D): Likewise.
394 (F_SIZEB1): Changed.
395 (C_DNZ_D): Define.
396 (C_HARD): Changed.
397 * arc-tbl.h (dbnz): New instruction.
398 (prealloc): Allow it for ARC EM.
399 (xbfu): Likewise.
400
ad43e107
RS
4012016-09-21 Richard Sandiford <richard.sandiford@arm.com>
402
403 * aarch64-opc.c (print_immediate_offset_address): Print spaces
404 after commas in addresses.
405 (aarch64_print_operand): Likewise.
406
ab3b8fcf
RS
4072016-09-21 Richard Sandiford <richard.sandiford@arm.com>
408
409 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
410 rather than "should be" or "expected to be" in error messages.
411
bb7eff52
RS
4122016-09-21 Richard Sandiford <richard.sandiford@arm.com>
413
414 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
415 (print_mnemonic_name): ...here.
416 (print_comment): New function.
417 (print_aarch64_insn): Call it.
418 * aarch64-opc.c (aarch64_conds): Add SVE names.
419 (aarch64_print_operand): Print alternative condition names in
420 a comment.
421
c0890d26
RS
4222016-09-21 Richard Sandiford <richard.sandiford@arm.com>
423
424 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
425 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
426 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
427 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
428 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
429 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
430 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
431 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
432 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
433 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
434 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
435 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
436 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
437 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
438 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
439 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
440 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
441 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
442 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
443 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
444 (OP_SVE_XWU, OP_SVE_XXU): New macros.
445 (aarch64_feature_sve): New variable.
446 (SVE): New macro.
447 (_SVE_INSN): Likewise.
448 (aarch64_opcode_table): Add SVE instructions.
449 * aarch64-opc.h (extract_fields): Declare.
450 * aarch64-opc-2.c: Regenerate.
451 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
452 * aarch64-asm-2.c: Regenerate.
453 * aarch64-dis.c (extract_fields): Make global.
454 (do_misc_decoding): Handle the new SVE aarch64_ops.
455 * aarch64-dis-2.c: Regenerate.
456
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4572016-09-21 Richard Sandiford <richard.sandiford@arm.com>
458
459 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
460 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
461 aarch64_field_kinds.
462 * aarch64-opc.c (fields): Add corresponding entries.
463 * aarch64-asm.c (aarch64_get_variant): New function.
464 (aarch64_encode_variant_using_iclass): Likewise.
465 (aarch64_opcode_encode): Call it.
466 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
467 (aarch64_opcode_decode): Call it.
468
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4692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
470
471 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
472 and FP register operands.
473 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
474 (FLD_SVE_Vn): New aarch64_field_kinds.
475 * aarch64-opc.c (fields): Add corresponding entries.
476 (aarch64_print_operand): Handle the new SVE core and FP register
477 operands.
478 * aarch64-opc-2.c: Regenerate.
479 * aarch64-asm-2.c: Likewise.
480 * aarch64-dis-2.c: Likewise.
481
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4822016-09-21 Richard Sandiford <richard.sandiford@arm.com>
483
484 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
485 immediate operands.
486 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
487 * aarch64-opc.c (fields): Add corresponding entry.
488 (operand_general_constraint_met_p): Handle the new SVE FP immediate
489 operands.
490 (aarch64_print_operand): Likewise.
491 * aarch64-opc-2.c: Regenerate.
492 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
493 (ins_sve_float_zero_one): New inserters.
494 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
495 (aarch64_ins_sve_float_half_two): Likewise.
496 (aarch64_ins_sve_float_zero_one): Likewise.
497 * aarch64-asm-2.c: Regenerate.
498 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
499 (ext_sve_float_zero_one): New extractors.
500 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
501 (aarch64_ext_sve_float_half_two): Likewise.
502 (aarch64_ext_sve_float_zero_one): Likewise.
503 * aarch64-dis-2.c: Regenerate.
504
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5052016-09-21 Richard Sandiford <richard.sandiford@arm.com>
506
507 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
508 integer immediate operands.
509 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
510 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
511 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
512 * aarch64-opc.c (fields): Add corresponding entries.
513 (operand_general_constraint_met_p): Handle the new SVE integer
514 immediate operands.
515 (aarch64_print_operand): Likewise.
516 (aarch64_sve_dupm_mov_immediate_p): New function.
517 * aarch64-opc-2.c: Regenerate.
518 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
519 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
520 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
521 (aarch64_ins_limm): ...here.
522 (aarch64_ins_inv_limm): New function.
523 (aarch64_ins_sve_aimm): Likewise.
524 (aarch64_ins_sve_asimm): Likewise.
525 (aarch64_ins_sve_limm_mov): Likewise.
526 (aarch64_ins_sve_shlimm): Likewise.
527 (aarch64_ins_sve_shrimm): Likewise.
528 * aarch64-asm-2.c: Regenerate.
529 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
530 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
531 * aarch64-dis.c (decode_limm): New function, split out from...
532 (aarch64_ext_limm): ...here.
533 (aarch64_ext_inv_limm): New function.
534 (decode_sve_aimm): Likewise.
535 (aarch64_ext_sve_aimm): Likewise.
536 (aarch64_ext_sve_asimm): Likewise.
537 (aarch64_ext_sve_limm_mov): Likewise.
538 (aarch64_top_bit): Likewise.
539 (aarch64_ext_sve_shlimm): Likewise.
540 (aarch64_ext_sve_shrimm): Likewise.
541 * aarch64-dis-2.c: Regenerate.
542
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5432016-09-21 Richard Sandiford <richard.sandiford@arm.com>
544
545 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
546 operands.
547 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
548 the AARCH64_MOD_MUL_VL entry.
549 (value_aligned_p): Cope with non-power-of-two alignments.
550 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
551 (print_immediate_offset_address): Likewise.
552 (aarch64_print_operand): Likewise.
553 * aarch64-opc-2.c: Regenerate.
554 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
555 (ins_sve_addr_ri_s9xvl): New inserters.
556 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
557 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
558 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
559 * aarch64-asm-2.c: Regenerate.
560 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
561 (ext_sve_addr_ri_s9xvl): New extractors.
562 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
563 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
564 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
565 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
566 * aarch64-dis-2.c: Regenerate.
567
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5682016-09-21 Richard Sandiford <richard.sandiford@arm.com>
569
570 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
571 address operands.
572 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
573 (FLD_SVE_xs_22): New aarch64_field_kinds.
574 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
575 (get_operand_specific_data): New function.
576 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
577 FLD_SVE_xs_14 and FLD_SVE_xs_22.
578 (operand_general_constraint_met_p): Handle the new SVE address
579 operands.
580 (sve_reg): New array.
581 (get_addr_sve_reg_name): New function.
582 (aarch64_print_operand): Handle the new SVE address operands.
583 * aarch64-opc-2.c: Regenerate.
584 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
585 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
586 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
587 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
588 (aarch64_ins_sve_addr_rr_lsl): Likewise.
589 (aarch64_ins_sve_addr_rz_xtw): Likewise.
590 (aarch64_ins_sve_addr_zi_u5): Likewise.
591 (aarch64_ins_sve_addr_zz): Likewise.
592 (aarch64_ins_sve_addr_zz_lsl): Likewise.
593 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
594 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
595 * aarch64-asm-2.c: Regenerate.
596 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
597 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
598 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
599 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
600 (aarch64_ext_sve_addr_ri_u6): Likewise.
601 (aarch64_ext_sve_addr_rr_lsl): Likewise.
602 (aarch64_ext_sve_addr_rz_xtw): Likewise.
603 (aarch64_ext_sve_addr_zi_u5): Likewise.
604 (aarch64_ext_sve_addr_zz): Likewise.
605 (aarch64_ext_sve_addr_zz_lsl): Likewise.
606 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
607 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
608 * aarch64-dis-2.c: Regenerate.
609
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6102016-09-21 Richard Sandiford <richard.sandiford@arm.com>
611
612 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
613 AARCH64_OPND_SVE_PATTERN_SCALED.
614 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
615 * aarch64-opc.c (fields): Add a corresponding entry.
616 (set_multiplier_out_of_range_error): New function.
617 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
618 (operand_general_constraint_met_p): Handle
619 AARCH64_OPND_SVE_PATTERN_SCALED.
620 (print_register_offset_address): Use PRIi64 to print the
621 shift amount.
622 (aarch64_print_operand): Likewise. Handle
623 AARCH64_OPND_SVE_PATTERN_SCALED.
624 * aarch64-opc-2.c: Regenerate.
625 * aarch64-asm.h (ins_sve_scale): New inserter.
626 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
627 * aarch64-asm-2.c: Regenerate.
628 * aarch64-dis.h (ext_sve_scale): New inserter.
629 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
630 * aarch64-dis-2.c: Regenerate.
631
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6322016-09-21 Richard Sandiford <richard.sandiford@arm.com>
633
634 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
635 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
636 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
637 (FLD_SVE_prfop): Likewise.
638 * aarch64-opc.c: Include libiberty.h.
639 (aarch64_sve_pattern_array): New variable.
640 (aarch64_sve_prfop_array): Likewise.
641 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
642 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
643 AARCH64_OPND_SVE_PRFOP.
644 * aarch64-asm-2.c: Regenerate.
645 * aarch64-dis-2.c: Likewise.
646 * aarch64-opc-2.c: Likewise.
647
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6482016-09-21 Richard Sandiford <richard.sandiford@arm.com>
649
650 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
651 AARCH64_OPND_QLF_P_[ZM].
652 (aarch64_print_operand): Print /z and /m where appropriate.
653
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6542016-09-21 Richard Sandiford <richard.sandiford@arm.com>
655
656 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
657 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
658 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
659 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
660 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
661 * aarch64-opc.c (fields): Add corresponding entries here.
662 (operand_general_constraint_met_p): Check that SVE register lists
663 have the correct length. Check the ranges of SVE index registers.
664 Check for cases where p8-p15 are used in 3-bit predicate fields.
665 (aarch64_print_operand): Handle the new SVE operands.
666 * aarch64-opc-2.c: Regenerate.
667 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
668 * aarch64-asm.c (aarch64_ins_sve_index): New function.
669 (aarch64_ins_sve_reglist): Likewise.
670 * aarch64-asm-2.c: Regenerate.
671 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
672 * aarch64-dis.c (aarch64_ext_sve_index): New function.
673 (aarch64_ext_sve_reglist): Likewise.
674 * aarch64-dis-2.c: Regenerate.
675
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6762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
677
678 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
679 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
680 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
681 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
682 tied operands.
683
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6842016-09-21 Richard Sandiford <richard.sandiford@arm.com>
685
686 * aarch64-opc.c (get_offset_int_reg_name): New function.
687 (print_immediate_offset_address): Likewise.
688 (print_register_offset_address): Take the base and offset
689 registers as parameters.
690 (aarch64_print_operand): Update caller accordingly. Use
691 print_immediate_offset_address.
692
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6932016-09-21 Richard Sandiford <richard.sandiford@arm.com>
694
695 * aarch64-opc.c (BANK): New macro.
696 (R32, R64): Take a register number as argument
697 (int_reg): Use BANK.
698
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6992016-09-21 Richard Sandiford <richard.sandiford@arm.com>
700
701 * aarch64-opc.c (print_register_list): Add a prefix parameter.
702 (aarch64_print_operand): Update accordingly.
703
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7042016-09-21 Richard Sandiford <richard.sandiford@arm.com>
705
706 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
707 for FPIMM.
708 * aarch64-asm.h (ins_fpimm): New inserter.
709 * aarch64-asm.c (aarch64_ins_fpimm): New function.
710 * aarch64-asm-2.c: Regenerate.
711 * aarch64-dis.h (ext_fpimm): New extractor.
712 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
713 (aarch64_ext_fpimm): New function.
714 * aarch64-dis-2.c: Regenerate.
715
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7162016-09-21 Richard Sandiford <richard.sandiford@arm.com>
717
718 * aarch64-asm.c: Include libiberty.h.
719 (insert_fields): New function.
720 (aarch64_ins_imm): Use it.
721 * aarch64-dis.c (extract_fields): New function.
722 (aarch64_ext_imm): Use it.
723
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7242016-09-21 Richard Sandiford <richard.sandiford@arm.com>
725
726 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
727 with an esize parameter.
728 (operand_general_constraint_met_p): Update accordingly.
729 Fix misindented code.
730 * aarch64-asm.c (aarch64_ins_limm): Update call to
731 aarch64_logical_immediate_p.
732
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7332016-09-21 Richard Sandiford <richard.sandiford@arm.com>
734
735 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
736
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7372016-09-21 Richard Sandiford <richard.sandiford@arm.com>
738
739 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
740
f807f43d
CZ
7412016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
742
743 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
744
fd486b63
PB
7452016-09-14 Peter Bergner <bergner@vnet.ibm.com>
746
747 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
748 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
749 xor3>: Delete mnemonics.
750 <cp_abort>: Rename mnemonic from ...
751 <cpabort>: ...to this.
752 <setb>: Change to a X form instruction.
753 <sync>: Change to 1 operand form.
754 <copy>: Delete mnemonic.
755 <copy_first>: Rename mnemonic from ...
756 <copy>: ...to this.
757 <paste, paste.>: Delete mnemonics.
758 <paste_last>: Rename mnemonic from ...
759 <paste.>: ...to this.
760
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7612016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
762
763 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
764
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7652016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
766
767 * s390-mkopc.c (main): Support alternate arch strings.
768
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7692016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
770
771 * s390-opc.txt: Fix kmctr instruction type.
772
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L
7732016-09-07 H.J. Lu <hongjiu.lu@intel.com>
774
775 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
776 * i386-init.h: Regenerated.
777
7763838e
CM
7782016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
779
780 * opcodes/arc-dis.c (print_insn_arc): Changed.
781
1b8b6532
JM
7822016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
783
784 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
785 camellia_fl.
786
1a336194
TP
7872016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
788
789 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
790 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
791 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
792
6b40c462
L
7932016-08-24 H.J. Lu <hongjiu.lu@intel.com>
794
795 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
796 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
797 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
798 PREFIX_MOD_3_0FAE_REG_4.
799 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
800 PREFIX_MOD_3_0FAE_REG_4.
801 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
802 (cpu_flags): Add CpuPTWRITE.
803 * i386-opc.h (CpuPTWRITE): New.
804 (i386_cpu_flags): Add cpuptwrite.
805 * i386-opc.tbl: Add ptwrite instruction.
806 * i386-init.h: Regenerated.
807 * i386-tbl.h: Likewise.
808
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8092016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
810
811 * arc-dis.h: Wrap around in extern "C".
812
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8132016-08-23 Richard Sandiford <richard.sandiford@arm.com>
814
815 * aarch64-tbl.h (V8_2_INSN): New macro.
816 (aarch64_opcode_table): Use it.
817
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8182016-08-23 Richard Sandiford <richard.sandiford@arm.com>
819
820 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
821 CORE_INSN, __FP_INSN and SIMD_INSN.
822
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8232016-08-23 Richard Sandiford <richard.sandiford@arm.com>
824
825 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
826 (aarch64_opcode_table): Update uses accordingly.
827
dfdaec14
AJ
8282016-07-25 Andrew Jenner <andrew@codesourcery.com>
829 Kwok Cheung Yeung <kcy@codesourcery.com>
830
831 opcodes/
832 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
833 'e_cmplwi' to 'e_cmpli' instead.
834 (OPVUPRT, OPVUPRT_MASK): Define.
835 (powerpc_opcodes): Add E200Z4 insns.
836 (vle_opcodes): Add context save/restore insns.
837
7bd374a4
MR
8382016-07-27 Maciej W. Rozycki <macro@imgtec.com>
839
840 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
841 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
842 "j".
843
db18dbab
GM
8442016-07-27 Graham Markall <graham.markall@embecosm.com>
845
846 * arc-nps400-tbl.h: Change block comments to GNU format.
847 * arc-dis.c: Add new globals addrtypenames,
848 addrtypenames_max, and addtypeunknown.
849 (get_addrtype): New function.
850 (print_insn_arc): Print colons and address types when
851 required.
852 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
853 define insert and extract functions for all address types.
854 (arc_operands): Add operands for colon and all address
855 types.
856 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
857 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
858 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
859 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
860 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
861 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
862
fecd57f9
L
8632016-07-21 H.J. Lu <hongjiu.lu@intel.com>
864
865 * configure: Regenerated.
866
37fd5ef3
CZ
8672016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
868
869 * arc-dis.c (skipclass): New structure.
870 (decodelist): New variable.
871 (is_compatible_p): New function.
872 (new_element): Likewise.
873 (skip_class_p): Likewise.
874 (find_format_from_table): Use skip_class_p function.
875 (find_format): Decode first the extension instructions.
876 (print_insn_arc): Select either ARCEM or ARCHS based on elf
877 e_flags.
878 (parse_option): New function.
879 (parse_disassembler_options): Likewise.
880 (print_arc_disassembler_options): Likewise.
881 (print_insn_arc): Use parse_disassembler_options function. Proper
882 select ARCv2 cpu variant.
883 * disassemble.c (disassembler_usage): Add ARC disassembler
884 options.
885
92281a5b
MR
8862016-07-13 Maciej W. Rozycki <macro@imgtec.com>
887
888 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
889 annotation from the "nal" entry and reorder it beyond "bltzal".
890
6e7ced37
JM
8912016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
892
893 * sparc-opc.c (ldtxa): New macro.
894 (sparc_opcodes): Use the macro defined above to add entries for
895 the LDTXA instructions.
896 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
897 instruction.
898
2f831b9a 8992016-07-07 James Bowman <james.bowman@ftdichip.com>
900
901 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
902 and "jmpc".
903
c07315e0
JB
9042016-07-01 Jan Beulich <jbeulich@suse.com>
905
906 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
907 (movzb): Adjust to cover all permitted suffixes.
908 (movzw): New.
909 * i386-tbl.h: Re-generate.
910
9243100a
JB
9112016-07-01 Jan Beulich <jbeulich@suse.com>
912
913 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
914 (lgdt): Remove Tbyte from non-64-bit variant.
915 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
916 xsaves64, xsavec64): Remove Disp16.
917 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
918 Remove Disp32S from non-64-bit variants. Remove Disp16 from
919 64-bit variants.
920 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
921 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
922 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
923 64-bit variants.
924 * i386-tbl.h: Re-generate.
925
8325cc63
JB
9262016-07-01 Jan Beulich <jbeulich@suse.com>
927
928 * i386-opc.tbl (xlat): Remove RepPrefixOk.
929 * i386-tbl.h: Re-generate.
930
838441e4
YQ
9312016-06-30 Yao Qi <yao.qi@linaro.org>
932
933 * arm-dis.c (print_insn): Fix typo in comment.
934
dab26bf4
RS
9352016-06-28 Richard Sandiford <richard.sandiford@arm.com>
936
937 * aarch64-opc.c (operand_general_constraint_met_p): Check the
938 range of ldst_elemlist operands.
939 (print_register_list): Use PRIi64 to print the index.
940 (aarch64_print_operand): Likewise.
941
5703197e
TS
9422016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
943
944 * mcore-opc.h: Remove sentinal.
945 * mcore-dis.c (print_insn_mcore): Adjust.
946
ce440d63
GM
9472016-06-23 Graham Markall <graham.markall@embecosm.com>
948
949 * arc-opc.c: Correct description of availability of NPS400
950 features.
951
6fd3a02d
PB
9522016-06-22 Peter Bergner <bergner@vnet.ibm.com>
953
954 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
955 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
956 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
957 xor3>: New mnemonics.
958 <setb>: Change to a VX form instruction.
959 (insert_sh6): Add support for rldixor.
960 (extract_sh6): Likewise.
961
6b477896
TS
9622016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
963
964 * arc-ext.h: Wrap in extern C.
965
bdd582db
GM
9662016-06-21 Graham Markall <graham.markall@embecosm.com>
967
968 * arc-dis.c (arc_insn_length): Add comment on instruction length.
969 Use same method for determining instruction length on ARC700 and
970 NPS-400.
971 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
972 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
973 with the NPS400 subclass.
974 * arc-opc.c: Likewise.
975
96074adc
JM
9762016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
977
978 * sparc-opc.c (rdasr): New macro.
979 (wrasr): Likewise.
980 (rdpr): Likewise.
981 (wrpr): Likewise.
982 (rdhpr): Likewise.
983 (wrhpr): Likewise.
984 (sparc_opcodes): Use the macros above to fix and expand the
985 definition of read/write instructions from/to
986 asr/privileged/hyperprivileged instructions.
987 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
988 %hva_mask_nz. Prefer softint_set and softint_clear over
989 set_softint and clear_softint.
990 (print_insn_sparc): Support %ver in Rd.
991
7a10c22f
JM
9922016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
993
994 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
995 architecture according to the hardware capabilities they require.
996
4f26fb3a
JM
9972016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
998
999 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1000 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1001 bfd_mach_sparc_v9{c,d,e,v,m}.
1002 * sparc-opc.c (MASK_V9C): Define.
1003 (MASK_V9D): Likewise.
1004 (MASK_V9E): Likewise.
1005 (MASK_V9V): Likewise.
1006 (MASK_V9M): Likewise.
1007 (v6): Add MASK_V9{C,D,E,V,M}.
1008 (v6notlet): Likewise.
1009 (v7): Likewise.
1010 (v8): Likewise.
1011 (v9): Likewise.
1012 (v9andleon): Likewise.
1013 (v9a): Likewise.
1014 (v9b): Likewise.
1015 (v9c): Define.
1016 (v9d): Likewise.
1017 (v9e): Likewise.
1018 (v9v): Likewise.
1019 (v9m): Likewise.
1020 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1021
3ee6e4fb
NC
10222016-06-15 Nick Clifton <nickc@redhat.com>
1023
1024 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1025 constants to match expected behaviour.
1026 (nds32_parse_opcode): Likewise. Also for whitespace.
1027
02f3be19
AB
10282016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1029
1030 * arc-opc.c (extract_rhv1): Extract value from insn.
1031
6f9f37ed 10322016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM
1033
1034 * arc-nps400-tbl.h: Add ldbit instruction.
1035 * arc-opc.c: Add flag classes required for ldbit.
1036
6f9f37ed 10372016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM
1038
1039 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1040 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1041 support the above instructions.
1042
6f9f37ed 10432016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM
1044
1045 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1046 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1047 csma, cbba, zncv, and hofs.
1048 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1049 support the above instructions.
1050
10512016-06-06 Graham Markall <graham.markall@embecosm.com>
1052
1053 * arc-nps400-tbl.h: Add andab and orab instructions.
1054
10552016-06-06 Graham Markall <graham.markall@embecosm.com>
1056
1057 * arc-nps400-tbl.h: Add addl-like instructions.
1058
10592016-06-06 Graham Markall <graham.markall@embecosm.com>
1060
1061 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1062
10632016-06-06 Graham Markall <graham.markall@embecosm.com>
1064
1065 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1066 instructions.
1067
b2cc3f6f
AK
10682016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1069
1070 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1071 variable.
1072 (init_disasm): Handle new command line option "insnlength".
1073 (print_s390_disassembler_options): Mention new option in help
1074 output.
1075 (print_insn_s390): Use the encoded insn length when dumping
1076 unknown instructions.
1077
1857fe72
DC
10782016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1079
1080 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1081 to the address and set as symbol address for LDS/ STS immediate operands.
1082
14b57c7c
AM
10832016-06-07 Alan Modra <amodra@gmail.com>
1084
1085 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1086 cpu for "vle" to e500.
1087 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1088 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1089 (PPCNONE): Delete, substitute throughout.
1090 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1091 except for major opcode 4 and 31.
1092 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1093
4d1464f2
MW
10942016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1095
1096 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1097 ARM_EXT_RAS in relevant entries.
1098
026122a6
PB
10992016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1100
1101 PR binutils/20196
1102 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1103 opcodes for E6500.
1104
07f5af7d
L
11052016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1106
1107 PR binutis/18386
1108 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1109 (indir_v_mode): New.
1110 Add comments for '&'.
1111 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1112 (putop): Handle '&'.
1113 (intel_operand_size): Handle indir_v_mode.
1114 (OP_E_register): Likewise.
1115 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1116 64-bit indirect call/jmp for AMD64.
1117 * i386-tbl.h: Regenerated
1118
4eb6f892
AB
11192016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1120
1121 * arc-dis.c (struct arc_operand_iterator): New structure.
1122 (find_format_from_table): All the old content from find_format,
1123 with some minor adjustments, and parameter renaming.
1124 (find_format_long_instructions): New function.
1125 (find_format): Rewritten.
1126 (arc_insn_length): Add LSB parameter.
1127 (extract_operand_value): New function.
1128 (operand_iterator_next): New function.
1129 (print_insn_arc): Use new functions to find opcode, and iterator
1130 over operands.
1131 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1132 (extract_nps_3bit_dst_short): New function.
1133 (insert_nps_3bit_src2_short): New function.
1134 (extract_nps_3bit_src2_short): New function.
1135 (insert_nps_bitop1_size): New function.
1136 (extract_nps_bitop1_size): New function.
1137 (insert_nps_bitop2_size): New function.
1138 (extract_nps_bitop2_size): New function.
1139 (insert_nps_bitop_mod4_msb): New function.
1140 (extract_nps_bitop_mod4_msb): New function.
1141 (insert_nps_bitop_mod4_lsb): New function.
1142 (extract_nps_bitop_mod4_lsb): New function.
1143 (insert_nps_bitop_dst_pos3_pos4): New function.
1144 (extract_nps_bitop_dst_pos3_pos4): New function.
1145 (insert_nps_bitop_ins_ext): New function.
1146 (extract_nps_bitop_ins_ext): New function.
1147 (arc_operands): Add new operands.
1148 (arc_long_opcodes): New global array.
1149 (arc_num_long_opcodes): New global.
1150 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1151
1fe0971e
TS
11522016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1153
1154 * nds32-asm.h: Add extern "C".
1155 * sh-opc.h: Likewise.
1156
315f180f
GM
11572016-06-01 Graham Markall <graham.markall@embecosm.com>
1158
1159 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1160 0,b,limm to the rflt instruction.
1161
a2b5fccc
TS
11622016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1163
1164 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1165 constant.
1166
0cbd0046
L
11672016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1168
1169 PR gas/20145
1170 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1171 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1172 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1173 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1174 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1175 * i386-init.h: Regenerated.
1176
1848e567
L
11772016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1178
1179 PR gas/20145
1180 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1181 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1182 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1183 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1184 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1185 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1186 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1187 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1188 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1189 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1190 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1191 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1192 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1193 CpuRegMask for AVX512.
1194 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1195 and CpuRegMask.
1196 (set_bitfield_from_cpu_flag_init): New function.
1197 (set_bitfield): Remove const on f. Call
1198 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1199 * i386-opc.h (CpuRegMMX): New.
1200 (CpuRegXMM): Likewise.
1201 (CpuRegYMM): Likewise.
1202 (CpuRegZMM): Likewise.
1203 (CpuRegMask): Likewise.
1204 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1205 and cpuregmask.
1206 * i386-init.h: Regenerated.
1207 * i386-tbl.h: Likewise.
1208
e92bae62
L
12092016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1210
1211 PR gas/20154
1212 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1213 (opcode_modifiers): Add AMD64 and Intel64.
1214 (main): Properly verify CpuMax.
1215 * i386-opc.h (CpuAMD64): Removed.
1216 (CpuIntel64): Likewise.
1217 (CpuMax): Set to CpuNo64.
1218 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1219 (AMD64): New.
1220 (Intel64): Likewise.
1221 (i386_opcode_modifier): Add amd64 and intel64.
1222 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1223 on call and jmp.
1224 * i386-init.h: Regenerated.
1225 * i386-tbl.h: Likewise.
1226
e89c5eaa
L
12272016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1228
1229 PR gas/20154
1230 * i386-gen.c (main): Fail if CpuMax is incorrect.
1231 * i386-opc.h (CpuMax): Set to CpuIntel64.
1232 * i386-tbl.h: Regenerated.
1233
77d66e7b
NC
12342016-05-27 Nick Clifton <nickc@redhat.com>
1235
1236 PR target/20150
1237 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1238 (msp430dis_opcode_unsigned): New function.
1239 (msp430dis_opcode_signed): New function.
1240 (msp430_singleoperand): Use the new opcode reading functions.
1241 Only disassenmble bytes if they were successfully read.
1242 (msp430_doubleoperand): Likewise.
1243 (msp430_branchinstr): Likewise.
1244 (msp430x_callx_instr): Likewise.
1245 (print_insn_msp430): Check that it is safe to read bytes before
1246 attempting disassembly. Use the new opcode reading functions.
1247
19dfcc89
PB
12482016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1249
1250 * ppc-opc.c (CY): New define. Document it.
1251 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1252
f3ad7637
L
12532016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1254
1255 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1256 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1257 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1258 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1259 CPU_ANY_AVX_FLAGS.
1260 * i386-init.h: Regenerated.
1261
f1360d58
L
12622016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1263
1264 PR gas/20141
1265 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1266 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1267 * i386-init.h: Regenerated.
1268
293f5f65
L
12692016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1270
1271 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1272 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1273 * i386-init.h: Regenerated.
1274
d9eca1df
CZ
12752016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1276
1277 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1278 information.
1279 (print_insn_arc): Set insn_type information.
1280 * arc-opc.c (C_CC): Add F_CLASS_COND.
1281 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1282 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1283 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1284 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1285 (brne, brne_s, jeq_s, jne_s): Likewise.
1286
87789e08
CZ
12872016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1288
1289 * arc-tbl.h (neg): New instruction variant.
1290
c810e0b8
CZ
12912016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1292
1293 * arc-dis.c (find_format, find_format, get_auxreg)
1294 (print_insn_arc): Changed.
1295 * arc-ext.h (INSERT_XOP): Likewise.
1296
3d207518
TS
12972016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1298
1299 * tic54x-dis.c (sprint_mmr): Adjust.
1300 * tic54x-opc.c: Likewise.
1301
514e58b7
AM
13022016-05-19 Alan Modra <amodra@gmail.com>
1303
1304 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1305
e43de63c
AM
13062016-05-19 Alan Modra <amodra@gmail.com>
1307
1308 * ppc-opc.c: Formatting.
1309 (NSISIGNOPT): Define.
1310 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1311
1401d2fe
MR
13122016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1313
1314 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1315 replacing references to `micromips_ase' throughout.
1316 (_print_insn_mips): Don't use file-level microMIPS annotation to
1317 determine the disassembly mode with the symbol table.
1318
1178da44
PB
13192016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1320
1321 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1322
8f4f9071
MF
13232016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1324
1325 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1326 mips64r6.
1327 * mips-opc.c (D34): New macro.
1328 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1329
8bc52696
AF
13302016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1331
1332 * i386-dis.c (prefix_table): Add RDPID instruction.
1333 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1334 (cpu_flags): Add RDPID bitfield.
1335 * i386-opc.h (enum): Add RDPID element.
1336 (i386_cpu_flags): Add RDPID field.
1337 * i386-opc.tbl: Add RDPID instruction.
1338 * i386-init.h: Regenerate.
1339 * i386-tbl.h: Regenerate.
1340
39d911fc
TP
13412016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1342
1343 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1344 branch type of a symbol.
1345 (print_insn): Likewise.
1346
16a1fa25
TP
13472016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1348
1349 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1350 Mainline Security Extensions instructions.
1351 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1352 Extensions instructions.
1353 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1354 instructions.
1355 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1356 special registers.
1357
d751b79e
JM
13582016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1359
1360 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1361
945e0f82
CZ
13622016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1363
1364 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1365 (arcExtMap_genOpcode): Likewise.
1366 * arc-opc.c (arg_32bit_rc): Define new variable.
1367 (arg_32bit_u6): Likewise.
1368 (arg_32bit_limm): Likewise.
1369
20f55f38
SN
13702016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1371
1372 * aarch64-gen.c (VERIFIER): Define.
1373 * aarch64-opc.c (VERIFIER): Define.
1374 (verify_ldpsw): Use static linkage.
1375 * aarch64-opc.h (verify_ldpsw): Remove.
1376 * aarch64-tbl.h: Use VERIFIER for verifiers.
1377
4bd13cde
NC
13782016-04-28 Nick Clifton <nickc@redhat.com>
1379
1380 PR target/19722
1381 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1382 * aarch64-opc.c (verify_ldpsw): New function.
1383 * aarch64-opc.h (verify_ldpsw): New prototype.
1384 * aarch64-tbl.h: Add initialiser for verifier field.
1385 (LDPSW): Set verifier to verify_ldpsw.
1386
c0f92bf9
L
13872016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1388
1389 PR binutils/19983
1390 PR binutils/19984
1391 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1392 smaller than address size.
1393
e6c7cdec
TS
13942016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1395
1396 * alpha-dis.c: Regenerate.
1397 * crx-dis.c: Likewise.
1398 * disassemble.c: Likewise.
1399 * epiphany-opc.c: Likewise.
1400 * fr30-opc.c: Likewise.
1401 * frv-opc.c: Likewise.
1402 * ip2k-opc.c: Likewise.
1403 * iq2000-opc.c: Likewise.
1404 * lm32-opc.c: Likewise.
1405 * lm32-opinst.c: Likewise.
1406 * m32c-opc.c: Likewise.
1407 * m32r-opc.c: Likewise.
1408 * m32r-opinst.c: Likewise.
1409 * mep-opc.c: Likewise.
1410 * mt-opc.c: Likewise.
1411 * or1k-opc.c: Likewise.
1412 * or1k-opinst.c: Likewise.
1413 * tic80-opc.c: Likewise.
1414 * xc16x-opc.c: Likewise.
1415 * xstormy16-opc.c: Likewise.
1416
537aefaf
AB
14172016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1418
1419 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1420 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1421 calcsd, and calcxd instructions.
1422 * arc-opc.c (insert_nps_bitop_size): Delete.
1423 (extract_nps_bitop_size): Delete.
1424 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1425 (extract_nps_qcmp_m3): Define.
1426 (extract_nps_qcmp_m2): Define.
1427 (extract_nps_qcmp_m1): Define.
1428 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1429 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1430 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1431 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1432 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1433 NPS_QCMP_M3.
1434
c8f785f2
AB
14352016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1436
1437 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1438
6fd8e7c2
L
14392016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1440
1441 * Makefile.in: Regenerated with automake 1.11.6.
1442 * aclocal.m4: Likewise.
1443
4b0c052e
AB
14442016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1445
1446 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1447 instructions.
1448 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1449 (extract_nps_cmem_uimm16): New function.
1450 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1451
cb040366
AB
14522016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1453
1454 * arc-dis.c (arc_insn_length): New function.
1455 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1456 (find_format): Change insnLen parameter to unsigned.
1457
accc0180
NC
14582016-04-13 Nick Clifton <nickc@redhat.com>
1459
1460 PR target/19937
1461 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1462 the LD.B and LD.BU instructions.
1463
f36e33da
CZ
14642016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1465
1466 * arc-dis.c (find_format): Check for extension flags.
1467 (print_flags): New function.
1468 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1469 .extAuxRegister.
1470 * arc-ext.c (arcExtMap_coreRegName): Use
1471 LAST_EXTENSION_CORE_REGISTER.
1472 (arcExtMap_coreReadWrite): Likewise.
1473 (dump_ARC_extmap): Update printing.
1474 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1475 (arc_aux_regs): Add cpu field.
1476 * arc-regs.h: Add cpu field, lower case name aux registers.
1477
1c2e355e
CZ
14782016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1479
1480 * arc-tbl.h: Add rtsc, sleep with no arguments.
1481
b99747ae
CZ
14822016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1483
1484 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1485 Initialize.
1486 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1487 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1488 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1489 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1490 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1491 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1492 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1493 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1494 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1495 (arc_opcode arc_opcodes): Null terminate the array.
1496 (arc_num_opcodes): Remove.
1497 * arc-ext.h (INSERT_XOP): Define.
1498 (extInstruction_t): Likewise.
1499 (arcExtMap_instName): Delete.
1500 (arcExtMap_insn): New function.
1501 (arcExtMap_genOpcode): Likewise.
1502 * arc-ext.c (ExtInstruction): Remove.
1503 (create_map): Zero initialize instruction fields.
1504 (arcExtMap_instName): Remove.
1505 (arcExtMap_insn): New function.
1506 (dump_ARC_extmap): More info while debuging.
1507 (arcExtMap_genOpcode): New function.
1508 * arc-dis.c (find_format): New function.
1509 (print_insn_arc): Use find_format.
1510 (arc_get_disassembler): Enable dump_ARC_extmap only when
1511 debugging.
1512
92708cec
MR
15132016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1514
1515 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1516 instruction bits out.
1517
a42a4f84
AB
15182016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1519
1520 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1521 * arc-opc.c (arc_flag_operands): Add new flags.
1522 (arc_flag_classes): Add new classes.
1523
1328504b
AB
15242016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1525
1526 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1527
820f03ff
AB
15282016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1529
1530 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1531 encode1, rflt, crc16, and crc32 instructions.
1532 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1533 (arc_flag_classes): Add C_NPS_R.
1534 (insert_nps_bitop_size_2b): New function.
1535 (extract_nps_bitop_size_2b): Likewise.
1536 (insert_nps_bitop_uimm8): Likewise.
1537 (extract_nps_bitop_uimm8): Likewise.
1538 (arc_operands): Add new operand entries.
1539
8ddf6b2a
CZ
15402016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1541
b99747ae
CZ
1542 * arc-regs.h: Add a new subclass field. Add double assist
1543 accumulator register values.
1544 * arc-tbl.h: Use DPA subclass to mark the double assist
1545 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1546 * arc-opc.c (RSP): Define instead of SP.
1547 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1548
589a7d88
JW
15492016-04-05 Jiong Wang <jiong.wang@arm.com>
1550
1551 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1552
0a191de9 15532016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB
1554
1555 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1556 NPS_R_SRC1.
1557
0a106562
AB
15582016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1559
1560 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1561 issues. No functional changes.
1562
bd05ac5f
CZ
15632016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1564
b99747ae
CZ
1565 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1566 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1567 (RTT): Remove duplicate.
1568 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1569 (PCT_CONFIG*): Remove.
1570 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1571
9885948f
CZ
15722016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1573
b99747ae 1574 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1575
f2dd8838
CZ
15762016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1577
b99747ae
CZ
1578 * arc-tbl.h (invld07): Remove.
1579 * arc-ext-tbl.h: New file.
1580 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1581 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1582
0d2f91fe
JK
15832016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1584
1585 Fix -Wstack-usage warnings.
1586 * aarch64-dis.c (print_operands): Substitute size.
1587 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1588
a6b71f42
JM
15892016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1590
1591 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1592 to get a proper diagnostic when an invalid ASR register is used.
1593
9780e045
NC
15942016-03-22 Nick Clifton <nickc@redhat.com>
1595
1596 * configure: Regenerate.
1597
e23e8ebe
AB
15982016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1599
1600 * arc-nps400-tbl.h: New file.
1601 * arc-opc.c: Add top level comment.
1602 (insert_nps_3bit_dst): New function.
1603 (extract_nps_3bit_dst): New function.
1604 (insert_nps_3bit_src2): New function.
1605 (extract_nps_3bit_src2): New function.
1606 (insert_nps_bitop_size): New function.
1607 (extract_nps_bitop_size): New function.
1608 (arc_flag_operands): Add nps400 entries.
1609 (arc_flag_classes): Add nps400 entries.
1610 (arc_operands): Add nps400 entries.
1611 (arc_opcodes): Add nps400 include.
1612
1ae8ab47
AB
16132016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1614
1615 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1616 the new class enum values.
1617
8699fc3e
AB
16182016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1619
1620 * arc-dis.c (print_insn_arc): Handle nps400.
1621
24740d83
AB
16222016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1623
1624 * arc-opc.c (BASE): Delete.
1625
8678914f
NC
16262016-03-18 Nick Clifton <nickc@redhat.com>
1627
1628 PR target/19721
1629 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1630 of MOV insn that aliases an ORR insn.
1631
cc933301
JW
16322016-03-16 Jiong Wang <jiong.wang@arm.com>
1633
1634 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1635
f86f5863
TS
16362016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1637
1638 * mcore-opc.h: Add const qualifiers.
1639 * microblaze-opc.h (struct op_code_struct): Likewise.
1640 * sh-opc.h: Likewise.
1641 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1642 (tic4x_print_op): Likewise.
1643
62de1c63
AM
16442016-03-02 Alan Modra <amodra@gmail.com>
1645
d11698cd 1646 * or1k-desc.h: Regenerate.
62de1c63 1647 * fr30-ibld.c: Regenerate.
c697cf0b 1648 * rl78-decode.c: Regenerate.
62de1c63 1649
020efce5
NC
16502016-03-01 Nick Clifton <nickc@redhat.com>
1651
1652 PR target/19747
1653 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1654
b0c11777
RL
16552016-02-24 Renlin Li <renlin.li@arm.com>
1656
1657 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1658 (print_insn_coprocessor): Support fp16 instructions.
1659
3e309328
RL
16602016-02-24 Renlin Li <renlin.li@arm.com>
1661
1662 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1663 vminnm, vrint(mpna).
1664
8afc7bea
RL
16652016-02-24 Renlin Li <renlin.li@arm.com>
1666
1667 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1668 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1669
4fd7268a
L
16702016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1671
1672 * i386-dis.c (print_insn): Parenthesize expression to prevent
1673 truncated addresses.
1674 (OP_J): Likewise.
1675
4670103e
CZ
16762016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1677 Janek van Oirschot <jvanoirs@synopsys.com>
1678
b99747ae
CZ
1679 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1680 variable.
4670103e 1681
c1d9289f
NC
16822016-02-04 Nick Clifton <nickc@redhat.com>
1683
1684 PR target/19561
1685 * msp430-dis.c (print_insn_msp430): Add a special case for
1686 decoding an RRC instruction with the ZC bit set in the extension
1687 word.
1688
a143b004
AB
16892016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1690
1691 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1692 * epiphany-ibld.c: Regenerate.
1693 * fr30-ibld.c: Regenerate.
1694 * frv-ibld.c: Regenerate.
1695 * ip2k-ibld.c: Regenerate.
1696 * iq2000-ibld.c: Regenerate.
1697 * lm32-ibld.c: Regenerate.
1698 * m32c-ibld.c: Regenerate.
1699 * m32r-ibld.c: Regenerate.
1700 * mep-ibld.c: Regenerate.
1701 * mt-ibld.c: Regenerate.
1702 * or1k-ibld.c: Regenerate.
1703 * xc16x-ibld.c: Regenerate.
1704 * xstormy16-ibld.c: Regenerate.
1705
b89807c6
AB
17062016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1707
1708 * epiphany-dis.c: Regenerated from latest cpu files.
1709
d8c823c8
MM
17102016-02-01 Michael McConville <mmcco@mykolab.com>
1711
1712 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1713 test bit.
1714
5bc5ae88
RL
17152016-01-25 Renlin Li <renlin.li@arm.com>
1716
1717 * arm-dis.c (mapping_symbol_for_insn): New function.
1718 (find_ifthen_state): Call mapping_symbol_for_insn().
1719
0bff6e2d
MW
17202016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1721
1722 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1723 of MSR UAO immediate operand.
1724
100b4f2e
MR
17252016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1726
1727 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1728 instruction support.
1729
5c14705f
AM
17302016-01-17 Alan Modra <amodra@gmail.com>
1731
1732 * configure: Regenerate.
1733
4d82fe66
NC
17342016-01-14 Nick Clifton <nickc@redhat.com>
1735
1736 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1737 instructions that can support stack pointer operations.
1738 * rl78-decode.c: Regenerate.
1739 * rl78-dis.c: Fix display of stack pointer in MOVW based
1740 instructions.
1741
651657fa
MW
17422016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1743
1744 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1745 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1746 erxtatus_el1 and erxaddr_el1.
1747
105bde57
MW
17482016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1749
1750 * arm-dis.c (arm_opcodes): Add "esb".
1751 (thumb_opcodes): Likewise.
1752
afa8d405
PB
17532016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1754
1755 * ppc-opc.c <xscmpnedp>: Delete.
1756 <xvcmpnedp>: Likewise.
1757 <xvcmpnedp.>: Likewise.
1758 <xvcmpnesp>: Likewise.
1759 <xvcmpnesp.>: Likewise.
1760
83c3256e
AS
17612016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1762
1763 PR gas/13050
1764 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1765 addition to ISA_A.
1766
6f2750fe
AM
17672016-01-01 Alan Modra <amodra@gmail.com>
1768
1769 Update year range in copyright notice of all files.
1770
3499769a
AM
1771For older changes see ChangeLog-2015
1772\f
1773Copyright (C) 2016 Free Software Foundation, Inc.
1774
1775Copying and distribution of this file, with or without modification,
1776are permitted in any medium without royalty provided the copyright
1777notice and this notice are preserved.
1778
1779Local Variables:
1780mode: change-log
1781left-margin: 8
1782fill-column: 74
1783version-control: never
1784End:
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