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Move common symbol check after bed->common_definition
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e347efc3
MR		 12017-08-07 Maciej W. Rozycki <macro@imgtec.com>
2
3 * disassemble.c (disassembler): Remove arch/mach/endian
4 assertions.
5
7cbc739c
NC		 62017-07-25 Nick Clifton <nickc@redhat.com>
7
8 PR 21739
9 * arc-opc.c (insert_rhv2): Use lower case first letter in error
10 message.
11 (insert_r0): Likewise.
12 (insert_r1): Likewise.
13 (insert_r2): Likewise.
14 (insert_r3): Likewise.
15 (insert_sp): Likewise.
16 (insert_gp): Likewise.
17 (insert_pcl): Likewise.
18 (insert_blink): Likewise.
19 (insert_ilink1): Likewise.
20 (insert_ilink2): Likewise.
21 (insert_ras): Likewise.
22 (insert_rbs): Likewise.
23 (insert_rcs): Likewise.
24 (insert_simm3s): Likewise.
25 (insert_rrange): Likewise.
26 (insert_r13el): Likewise.
27 (insert_fpel): Likewise.
28 (insert_blinkel): Likewise.
29 (insert_pclel): Likewise.
30 (insert_nps_bitop_size_2b): Likewise.
31 (insert_nps_imm_offset): Likewise.
32 (insert_nps_imm_entry): Likewise.
33 (insert_nps_size_16bit): Likewise.
34 (insert_nps_##NAME##_pos): Likewise.
35 (insert_nps_##NAME): Likewise.
36 (insert_nps_bitop_ins_ext): Likewise.
37 (insert_nps_##NAME): Likewise.
38 (insert_nps_min_hofs): Likewise.
39 (insert_nps_##NAME): Likewise.
40 (insert_nps_rbdouble_64): Likewise.
41 (insert_nps_misc_imm_offset): Likewise.
42 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
43 option description.
44
7684e580
JW		 452017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
46 Jiong Wang <jiong.wang@arm.com>
47
48 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
49 correct the print.
50 * aarch64-dis-2.c: Regenerated.
51
47826cdb
AK		 522017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
53
54 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
55 table.
56
2d2dbad0
NC		 572017-07-20 Nick Clifton <nickc@redhat.com>
58
59 * po/de.po: Updated German translation.
60
70b448ba 612017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
62
63 * arc-regs.h (sec_stat): New aux register.
64 (aux_kernel_sp): Likewise.
65 (aux_sec_u_sp): Likewise.
66 (aux_sec_k_sp): Likewise.
67 (sec_vecbase_build): Likewise.
68 (nsc_table_top): Likewise.
69 (nsc_table_base): Likewise.
70 (ersec_stat): Likewise.
71 (aux_sec_except): Likewise.
72
7179e0e6
CZ		 732017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
74
75 * arc-opc.c (extract_uimm12_20): New function.
76 (UIMM12_20): New operand.
77 (SIMM3_5_S): Adjust.
78 * arc-tbl.h (sjli): Add new instruction.
79
684d5a10
JEM		 802017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
81 John Eric Martin <John.Martin@emmicro-us.com>
82
83 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
84 (UIMM3_23): Adjust accordingly.
85 * arc-regs.h: Add/correct jli_base register.
86 * arc-tbl.h (jli_s): Likewise.
87
de194d85
YC		 882017-07-18 Nick Clifton <nickc@redhat.com>
89
90 PR 21775
91 * aarch64-opc.c: Fix spelling typos.
92 * i386-dis.c: Likewise.
93
0f6329bd
RB		 942017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
95
96 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
97 max_addr_offset and octets variables to size_t.
98
429d795d
AM		 992017-07-12 Alan Modra <amodra@gmail.com>
100
101 * po/da.po: Update from translationproject.org/latest/opcodes/.
102 * po/de.po: Likewise.
103 * po/es.po: Likewise.
104 * po/fi.po: Likewise.
105 * po/fr.po: Likewise.
106 * po/id.po: Likewise.
107 * po/it.po: Likewise.
108 * po/nl.po: Likewise.
109 * po/pt_BR.po: Likewise.
110 * po/ro.po: Likewise.
111 * po/sv.po: Likewise.
112 * po/tr.po: Likewise.
113 * po/uk.po: Likewise.
114 * po/vi.po: Likewise.
115 * po/zh_CN.po: Likewise.
116
4162bb66
AM		 1172017-07-11 Yao Qi <yao.qi@linaro.org>
118 Alan Modra <amodra@gmail.com>
119
120 * cgen.sh: Mark generated files read-only.
121 * epiphany-asm.c: Regenerate.
122 * epiphany-desc.c: Regenerate.
123 * epiphany-desc.h: Regenerate.
124 * epiphany-dis.c: Regenerate.
125 * epiphany-ibld.c: Regenerate.
126 * epiphany-opc.c: Regenerate.
127 * epiphany-opc.h: Regenerate.
128 * fr30-asm.c: Regenerate.
129 * fr30-desc.c: Regenerate.
130 * fr30-desc.h: Regenerate.
131 * fr30-dis.c: Regenerate.
132 * fr30-ibld.c: Regenerate.
133 * fr30-opc.c: Regenerate.
134 * fr30-opc.h: Regenerate.
135 * frv-asm.c: Regenerate.
136 * frv-desc.c: Regenerate.
137 * frv-desc.h: Regenerate.
138 * frv-dis.c: Regenerate.
139 * frv-ibld.c: Regenerate.
140 * frv-opc.c: Regenerate.
141 * frv-opc.h: Regenerate.
142 * ip2k-asm.c: Regenerate.
143 * ip2k-desc.c: Regenerate.
144 * ip2k-desc.h: Regenerate.
145 * ip2k-dis.c: Regenerate.
146 * ip2k-ibld.c: Regenerate.
147 * ip2k-opc.c: Regenerate.
148 * ip2k-opc.h: Regenerate.
149 * iq2000-asm.c: Regenerate.
150 * iq2000-desc.c: Regenerate.
151 * iq2000-desc.h: Regenerate.
152 * iq2000-dis.c: Regenerate.
153 * iq2000-ibld.c: Regenerate.
154 * iq2000-opc.c: Regenerate.
155 * iq2000-opc.h: Regenerate.
156 * lm32-asm.c: Regenerate.
157 * lm32-desc.c: Regenerate.
158 * lm32-desc.h: Regenerate.
159 * lm32-dis.c: Regenerate.
160 * lm32-ibld.c: Regenerate.
161 * lm32-opc.c: Regenerate.
162 * lm32-opc.h: Regenerate.
163 * lm32-opinst.c: Regenerate.
164 * m32c-asm.c: Regenerate.
165 * m32c-desc.c: Regenerate.
166 * m32c-desc.h: Regenerate.
167 * m32c-dis.c: Regenerate.
168 * m32c-ibld.c: Regenerate.
169 * m32c-opc.c: Regenerate.
170 * m32c-opc.h: Regenerate.
171 * m32r-asm.c: Regenerate.
172 * m32r-desc.c: Regenerate.
173 * m32r-desc.h: Regenerate.
174 * m32r-dis.c: Regenerate.
175 * m32r-ibld.c: Regenerate.
176 * m32r-opc.c: Regenerate.
177 * m32r-opc.h: Regenerate.
178 * m32r-opinst.c: Regenerate.
179 * mep-asm.c: Regenerate.
180 * mep-desc.c: Regenerate.
181 * mep-desc.h: Regenerate.
182 * mep-dis.c: Regenerate.
183 * mep-ibld.c: Regenerate.
184 * mep-opc.c: Regenerate.
185 * mep-opc.h: Regenerate.
186 * mt-asm.c: Regenerate.
187 * mt-desc.c: Regenerate.
188 * mt-desc.h: Regenerate.
189 * mt-dis.c: Regenerate.
190 * mt-ibld.c: Regenerate.
191 * mt-opc.c: Regenerate.
192 * mt-opc.h: Regenerate.
193 * or1k-asm.c: Regenerate.
194 * or1k-desc.c: Regenerate.
195 * or1k-desc.h: Regenerate.
196 * or1k-dis.c: Regenerate.
197 * or1k-ibld.c: Regenerate.
198 * or1k-opc.c: Regenerate.
199 * or1k-opc.h: Regenerate.
200 * or1k-opinst.c: Regenerate.
201 * xc16x-asm.c: Regenerate.
202 * xc16x-desc.c: Regenerate.
203 * xc16x-desc.h: Regenerate.
204 * xc16x-dis.c: Regenerate.
205 * xc16x-ibld.c: Regenerate.
206 * xc16x-opc.c: Regenerate.
207 * xc16x-opc.h: Regenerate.
208 * xstormy16-asm.c: Regenerate.
209 * xstormy16-desc.c: Regenerate.
210 * xstormy16-desc.h: Regenerate.
211 * xstormy16-dis.c: Regenerate.
212 * xstormy16-ibld.c: Regenerate.
213 * xstormy16-opc.c: Regenerate.
214 * xstormy16-opc.h: Regenerate.
215
7639175c
AM		 2162017-07-07 Alan Modra <amodra@gmail.com>
217
218 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
219 * m32c-dis.c: Regenerate.
220 * mep-dis.c: Regenerate.
221
e4bdd679
BP		 2222017-07-05 Borislav Petkov <bp@suse.de>
223
224 * i386-dis.c: Enable ModRM.reg /6 aliases.
225
60c96dbf
RR		 2262017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
227
228 * opcodes/arm-dis.c: Support MVFR2 in disassembly
229 with vmrs and vmsr.
230
0d702cfe
TG		 2312017-07-04 Tristan Gingold <gingold@adacore.com>
232
233 * configure: Regenerate.
234
15e6ed8c
TG		 2352017-07-03 Tristan Gingold <gingold@adacore.com>
236
237 * po/opcodes.pot: Regenerate.
238
b1d3c886
MR		 2392017-06-30 Maciej W. Rozycki <macro@imgtec.com>
240
241 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
242 entries to the MSA ASE instruction block.
243
909b4e3d
MR		 2442017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
245 Maciej W. Rozycki <macro@imgtec.com>
246
247 * micromips-opc.c (XPA, XPAVZ): New macros.
248 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
249 "mthgc0".
250
f5b2fd52
MR		 2512017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
252 Maciej W. Rozycki <macro@imgtec.com>
253
254 * micromips-opc.c (I36): New macro.
255 (micromips_opcodes): Add "eretnc".
256
9785fc2a
MR		 2572017-06-30 Maciej W. Rozycki <macro@imgtec.com>
258 Andrew Bennett <andrew.bennett@imgtec.com>
259
260 * mips-dis.c (mips_calculate_combination_ases): Handle the
261 ASE_XPA_VIRT flag.
262 (parse_mips_ase_option): New function.
263 (parse_mips_dis_option): Factor out ASE option handling to the
264 new function. Call `mips_calculate_combination_ases'.
265 * mips-opc.c (XPAVZ): New macro.
266 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
267 "mfhgc0", "mthc0" and "mthgc0".
268
60804c53
MR		 2692017-06-29 Maciej W. Rozycki <macro@imgtec.com>
270
271 * mips-dis.c (mips_calculate_combination_ases): New function.
272 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
273 calculation to the new function.
274 (set_default_mips_dis_options): Call the new function.
275
2e74f9dd
AK		 2762017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
277
278 * arc-dis.c (parse_disassembler_options): Use
279 FOR_EACH_DISASSEMBLER_OPTION.
280
e1e94c49
AK		 2812017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
282
283 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
284 disassembler option strings.
285 (parse_cpu_option): Likewise.
286
65a55fbb
TC		 2872017-06-28 Tamar Christina <tamar.christina@arm.com>
288
289 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
290 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
291 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
292 (aarch64_feature_dotprod, DOT_INSN): New.
293 (udot, sdot): New.
294 * aarch64-dis-2.c: Regenerated.
295
c604a79a
JW		 2962017-06-28 Jiong Wang <jiong.wang@arm.com>
297
298 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
299
38bf472a
MR		 3002017-06-28 Maciej W. Rozycki <macro@imgtec.com>
301 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 302 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 303
304 * mips-formats.h (INT_BIAS): New macro.
305 (INT_ADJ): Redefine in INT_BIAS terms.
306 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
307 (mips_print_save_restore): New function.
308 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
309 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
310 call.
311 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
312 (print_mips16_insn_arg): Call `mips_print_save_restore' for
313 OP_SAVE_RESTORE_LIST handling, factored out from here.
314 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
315 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
316 (mips_builtin_opcodes): Add "restore" and "save" entries.
317 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
318 (IAMR2): New macro.
319 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
320
9bdfdbf9
AW		 3212017-06-23 Andrew Waterman <andrew@sifive.com>
322
323 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
324 alias; do not mark SLTI instruction as an alias.
325
2234eee6
L		 3262017-06-21 H.J. Lu <hongjiu.lu@intel.com>
327
328 * i386-dis.c (RM_0FAE_REG_5): Removed.
329 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
330 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
331 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
332 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
333 PREFIX_MOD_3_0F01_REG_5_RM_0.
334 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
335 PREFIX_MOD_3_0FAE_REG_5.
336 (mod_table): Update MOD_0FAE_REG_5.
337 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
338 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
339 * i386-tbl.h: Regenerated.
340
c2f76402
L		 3412017-06-21 H.J. Lu <hongjiu.lu@intel.com>
342
343 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
344 * i386-opc.tbl: Likewise.
345 * i386-tbl.h: Regenerated.
346
9fef80d6
L		 3472017-06-21 H.J. Lu <hongjiu.lu@intel.com>
348
349 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
350 and "jmp{&|}".
351 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
352 prefix.
353
0f6d864d
NC		 3542017-06-19 Nick Clifton <nickc@redhat.com>
355
356 PR binutils/21614
357 * score-dis.c (score_opcodes): Add sentinel.
358
e197589b
AM		 3592017-06-16 Alan Modra <amodra@gmail.com>
360
361 * rx-decode.c: Regenerate.
362
0d96e4df
L		 3632017-06-15 H.J. Lu <hongjiu.lu@intel.com>
364
365 PR binutils/21594
366 * i386-dis.c (OP_E_register): Check valid bnd register.
367 (OP_G): Likewise.
368
cd3ea7c6
NC		 3692017-06-15 Nick Clifton <nickc@redhat.com>
370
371 PR binutils/21595
372 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
373 range value.
374
63323b5b
NC		 3752017-06-15 Nick Clifton <nickc@redhat.com>
376
377 PR binutils/21588
378 * rl78-decode.opc (OP_BUF_LEN): Define.
379 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
380 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
381 array.
382 * rl78-decode.c: Regenerate.
383
08c7881b
NC		 3842017-06-15 Nick Clifton <nickc@redhat.com>
385
386 PR binutils/21586
387 * bfin-dis.c (gregs): Clip index to prevent overflow.
388 (regs): Likewise.
389 (regs_lo): Likewise.
390 (regs_hi): Likewise.
391
e64519d1
NC		 3922017-06-14 Nick Clifton <nickc@redhat.com>
393
394 PR binutils/21576
395 * score7-dis.c (score_opcodes): Add sentinel.
396
6394c606
YQ		 3972017-06-14 Yao Qi <yao.qi@linaro.org>
398
399 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
400 * arm-dis.c: Likewise.
401 * ia64-dis.c: Likewise.
402 * mips-dis.c: Likewise.
403 * spu-dis.c: Likewise.
404 * disassemble.h (print_insn_aarch64): New declaration, moved from
405 include/dis-asm.h.
406 (print_insn_big_arm, print_insn_big_mips): Likewise.
407 (print_insn_i386, print_insn_ia64): Likewise.
408 (print_insn_little_arm, print_insn_little_mips): Likewise.
409
db5fa770
NC		 4102017-06-14 Nick Clifton <nickc@redhat.com>
411
412 PR binutils/21587
413 * rx-decode.opc: Include libiberty.h
414 (GET_SCALE): New macro - validates access to SCALE array.
415 (GET_PSCALE): New macro - validates access to PSCALE array.
416 (DIs, SIs, S2Is, rx_disp): Use new macros.
417 * rx-decode.c: Regenerate.
418
05c966f3
AV		 4192017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
420
421 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
422
10045478
AK		 4232017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
424
425 * arc-dis.c (enforced_isa_mask): Declare.
426 (cpu_types): Likewise.
427 (parse_cpu_option): New function.
428 (parse_disassembler_options): Use it.
429 (print_insn_arc): Use enforced_isa_mask.
430 (print_arc_disassembler_options): Document new options.
431
88c1242d
YQ		 4322017-05-24 Yao Qi <yao.qi@linaro.org>
433
434 * alpha-dis.c: Include disassemble.h, don't include
435 dis-asm.h.
436 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
437 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
438 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
439 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
440 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
441 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
442 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
443 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
444 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
445 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
446 * moxie-dis.c, msp430-dis.c, mt-dis.c:
447 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
448 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
449 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
450 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
451 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
452 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
453 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
454 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
455 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
456 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
457 * z80-dis.c, z8k-dis.c: Likewise.
458 * disassemble.h: New file.
459
ab20fa4a
YQ		 4602017-05-24 Yao Qi <yao.qi@linaro.org>
461
462 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
463 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
464
003ca0fd
YQ		 4652017-05-24 Yao Qi <yao.qi@linaro.org>
466
467 * disassemble.c (disassembler): Add arguments a, big and mach.
468 Use them.
469
04ef582a
L		 4702017-05-22 H.J. Lu <hongjiu.lu@intel.com>
471
472 * i386-dis.c (NOTRACK_Fixup): New.
473 (NOTRACK): Likewise.
474 (NOTRACK_PREFIX): Likewise.
475 (last_active_prefix): Likewise.
476 (reg_table): Use NOTRACK on indirect call and jmp.
477 (ckprefix): Set last_active_prefix.
478 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
479 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
480 * i386-opc.h (NoTrackPrefixOk): New.
481 (i386_opcode_modifier): Add notrackprefixok.
482 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
483 Add notrack.
484 * i386-tbl.h: Regenerated.
485
64517994
JM		 4862017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
487
488 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
489 (X_IMM2): Define.
490 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
491 bfd_mach_sparc_v9m8.
492 (print_insn_sparc): Handle new operand types.
493 * sparc-opc.c (MASK_M8): Define.
494 (v6): Add MASK_M8.
495 (v6notlet): Likewise.
496 (v7): Likewise.
497 (v8): Likewise.
498 (v9): Likewise.
499 (v9a): Likewise.
500 (v9b): Likewise.
501 (v9c): Likewise.
502 (v9d): Likewise.
503 (v9e): Likewise.
504 (v9v): Likewise.
505 (v9m): Likewise.
506 (v9andleon): Likewise.
507 (m8): Define.
508 (HWS_VM8): Define.
509 (HWS2_VM8): Likewise.
510 (sparc_opcode_archs): Add entry for "m8".
511 (sparc_opcodes): Add OSA2017 and M8 instructions
512 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
513 fpx{ll,ra,rl}64x,
514 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
515 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
516 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
517 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
518 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
519 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
520 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
521 ASI_CORE_SELECT_COMMIT_NHT.
522
535b785f
AM		 5232017-05-18 Alan Modra <amodra@gmail.com>
524
525 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
526 * aarch64-dis.c: Likewise.
527 * aarch64-gen.c: Likewise.
528 * aarch64-opc.c: Likewise.
529
25499ac7
MR		 5302017-05-15 Maciej W. Rozycki <macro@imgtec.com>
531 Matthew Fortune <matthew.fortune@imgtec.com>
532
533 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
534 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
535 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
536 (print_insn_arg) <OP_REG28>: Add handler.
537 (validate_insn_args) <OP_REG28>: Handle.
538 (print_mips16_insn_arg): Handle MIPS16 instructions that require
539 32-bit encoding and 9-bit immediates.
540 (print_insn_mips16): Handle MIPS16 instructions that require
541 32-bit encoding and MFC0/MTC0 operand decoding.
542 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
543 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
544 (RD_C0, WR_C0, E2, E2MT): New macros.
545 (mips16_opcodes): Add entries for MIPS16e2 instructions:
546 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
547 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
548 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
549 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
550 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
551 instructions, "swl", "swr", "sync" and its "sync_acquire",
552 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
553 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
554 regular/extended entries for original MIPS16 ISA revision
555 instructions whose extended forms are subdecoded in the MIPS16e2
556 ISA revision: "li", "sll" and "srl".
557
fdfb4752
MR		 5582017-05-15 Maciej W. Rozycki <macro@imgtec.com>
559
560 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
561 reference in CP0 move operand decoding.
562
a4f89915
MR		 5632017-05-12 Maciej W. Rozycki <macro@imgtec.com>
564
565 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
566 type to hexadecimal.
567 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
568
99e2d67a
MR		 5692017-05-11 Maciej W. Rozycki <macro@imgtec.com>
570
571 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
572 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
573 "sync_rmb" and "sync_wmb" as aliases.
574 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
575 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
576
53a346d8
CZ		 5772017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
578
579 * arc-dis.c (parse_option): Update quarkse_em option..
580 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
581 QUARKSE1.
582 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
583
f91d48de
KC		 5842017-05-03 Kito Cheng <kito.cheng@gmail.com>
585
586 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
587
43e379d7
MC		 5882017-05-01 Michael Clark <michaeljclark@mac.com>
589
590 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
591 register.
592
a4ddc54e
MR		 5932017-05-02 Maciej W. Rozycki <macro@imgtec.com>
594
595 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
596 and branches and not synthetic data instructions.
597
fe50e98c
BE		 5982017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
599
600 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
601
126124cc
CZ		 6022017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
603
604 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
605 * arc-opc.c (insert_r13el): New function.
606 (R13_EL): Define.
607 * arc-tbl.h: Add new enter/leave variants.
608
be6a24d8
CZ		 6092017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
610
611 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
612
0348fd79
MR		 6132017-04-25 Maciej W. Rozycki <macro@imgtec.com>
614
615 * mips-dis.c (print_mips_disassembler_options): Add
616 `no-aliases'.
617
6e3d1f07
MR		 6182017-04-25 Maciej W. Rozycki <macro@imgtec.com>
619
620 * mips16-opc.c (AL): New macro.
621 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
622 of "ld" and "lw" as aliases.
623
957f6b39
TC		 6242017-04-24 Tamar Christina <tamar.christina@arm.com>
625
626 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
627 arguments.
628
a8cc8a54
AM		 6292017-04-22 Alexander Fedotov <alfedotov@gmail.com>
630 Alan Modra <amodra@gmail.com>
631
632 * ppc-opc.c (ELEV): Define.
633 (vle_opcodes): Add se_rfgi and e_sc.
634 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
635 for E200Z4.
636
3ab87b68
JM		 6372017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
638
639 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
640
792f174f
NC		 6412017-04-21 Nick Clifton <nickc@redhat.com>
642
643 PR binutils/21380
644 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
645 LD3R and LD4R.
646
42742084
AM		 6472017-04-13 Alan Modra <amodra@gmail.com>
648
649 * epiphany-desc.c: Regenerate.
650 * fr30-desc.c: Regenerate.
651 * frv-desc.c: Regenerate.
652 * ip2k-desc.c: Regenerate.
653 * iq2000-desc.c: Regenerate.
654 * lm32-desc.c: Regenerate.
655 * m32c-desc.c: Regenerate.
656 * m32r-desc.c: Regenerate.
657 * mep-desc.c: Regenerate.
658 * mt-desc.c: Regenerate.
659 * or1k-desc.c: Regenerate.
660 * xc16x-desc.c: Regenerate.
661 * xstormy16-desc.c: Regenerate.
662
9a85b496
AM		 6632017-04-11 Alan Modra <amodra@gmail.com>
664
ef85eab0 665 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 666 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
667 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 668 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
669 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 670 (PPCVSX2): Define as PPC_OPCODE_POWER8.
671 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 672 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 673 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 674
62adc510
AM		 6752017-04-10 Alan Modra <amodra@gmail.com>
676
677 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
678 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
679 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
680 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
681
aa808707
PC		 6822017-04-09 Pip Cet <pipcet@gmail.com>
683
684 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
685 appropriate floating-point precision directly.
686
ac8f0f72
AM		 6872017-04-07 Alan Modra <amodra@gmail.com>
688
689 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
690 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
691 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
692 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
693 vector instructions with E6500 not PPCVEC2.
694
62ecb94c
PC		 6952017-04-06 Pip Cet <pipcet@gmail.com>
696
697 * Makefile.am: Add wasm32-dis.c.
698 * configure.ac: Add wasm32-dis.c to wasm32 target.
699 * disassemble.c: Add wasm32 disassembler code.
700 * wasm32-dis.c: New file.
701 * Makefile.in: Regenerate.
702 * configure: Regenerate.
703 * po/POTFILES.in: Regenerate.
704 * po/opcodes.pot: Regenerate.
705
f995bbe8
PA		 7062017-04-05 Pedro Alves <palves@redhat.com>
707
708 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
709 * arm-dis.c (parse_arm_disassembler_options): Constify.
710 * ppc-dis.c (powerpc_init_dialect): Constify local.
711 * vax-dis.c (parse_disassembler_options): Constify.
712
b5292032
PD		 7132017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
714
715 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
716 RISCV_GP_SYMBOL.
717
f96bd6c2
PC		 7182017-03-30 Pip Cet <pipcet@gmail.com>
719
720 * configure.ac: Add (empty) bfd_wasm32_arch target.
721 * configure: Regenerate
722 * po/opcodes.pot: Regenerate.
723
f7c514a3
JM		 7242017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
725
726 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
727 OSA2015.
728 * opcodes/sparc-opc.c (asi_table): New ASIs.
729
52be03fd
AM		 7302017-03-29 Alan Modra <amodra@gmail.com>
731
732 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
733 "raw" option.
734 (lookup_powerpc): Don't special case -1 dialect. Handle
735 PPC_OPCODE_RAW.
736 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
737 lookup_powerpc call, pass it on second.
738
9b753937
AM		 7392017-03-27 Alan Modra <amodra@gmail.com>
740
741 PR 21303
742 * ppc-dis.c (struct ppc_mopt): Comment.
743 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
744
c0c31e91
RZ		 7452017-03-27 Rinat Zelig <rinat@mellanox.com>
746
747 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
748 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
749 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
750 (insert_nps_misc_imm_offset): New function.
751 (extract_nps_misc imm_offset): New function.
752 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
753 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
754
2253c8f0
AK		 7552017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
756
757 * s390-mkopc.c (main): Remove vx2 check.
758 * s390-opc.txt: Remove vx2 instruction flags.
759
645d3342
RZ		 7602017-03-21 Rinat Zelig <rinat@mellanox.com>
761
762 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
763 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
764 (insert_nps_imm_offset): New function.
765 (extract_nps_imm_offset): New function.
766 (insert_nps_imm_entry): New function.
767 (extract_nps_imm_entry): New function.
768
4b94dd2d
AM		 7692017-03-17 Alan Modra <amodra@gmail.com>
770
771 PR 21248
772 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
773 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
774 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
775
b416fe87
KC		 7762017-03-14 Kito Cheng <kito.cheng@gmail.com>
777
778 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
779 <c.andi>: Likewise.
780 <c.addiw> Likewise.
781
03b039a5
KC		 7822017-03-14 Kito Cheng <kito.cheng@gmail.com>
783
784 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
785
2c232b83
AW		 7862017-03-13 Andrew Waterman <andrew@sifive.com>
787
788 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
789 <srl> Likewise.
790 <srai> Likewise.
791 <sra> Likewise.
792
86fa6981
L		 7932017-03-09 H.J. Lu <hongjiu.lu@intel.com>
794
795 * i386-gen.c (opcode_modifiers): Replace S with Load.
796 * i386-opc.h (S): Removed.
797 (Load): New.
798 (i386_opcode_modifier): Replace s with load.
799 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
800 and {evex}. Replace S with Load.
801 * i386-tbl.h: Regenerated.
802
c1fe188b
L		 8032017-03-09 H.J. Lu <hongjiu.lu@intel.com>
804
805 * i386-opc.tbl: Use CpuCET on rdsspq.
806 * i386-tbl.h: Regenerated.
807
4b8b687e
PB		 8082017-03-08 Peter Bergner <bergner@vnet.ibm.com>
809
810 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
811 <vsx>: Do not use PPC_OPCODE_VSX3;
812
1437d063
PB		 8132017-03-08 Peter Bergner <bergner@vnet.ibm.com>
814
815 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
816
603555e5
L		 8172017-03-06 H.J. Lu <hongjiu.lu@intel.com>
818
819 * i386-dis.c (REG_0F1E_MOD_3): New enum.
820 (MOD_0F1E_PREFIX_1): Likewise.
821 (MOD_0F38F5_PREFIX_2): Likewise.
822 (MOD_0F38F6_PREFIX_0): Likewise.
823 (RM_0F1E_MOD_3_REG_7): Likewise.
824 (PREFIX_MOD_0_0F01_REG_5): Likewise.
825 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
826 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
827 (PREFIX_0F1E): Likewise.
828 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
829 (PREFIX_0F38F5): Likewise.
830 (dis386_twobyte): Use PREFIX_0F1E.
831 (reg_table): Add REG_0F1E_MOD_3.
832 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
833 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
834 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
835 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
836 (three_byte_table): Use PREFIX_0F38F5.
837 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
838 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
839 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
840 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
841 PREFIX_MOD_3_0F01_REG_5_RM_2.
842 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
843 (cpu_flags): Add CpuCET.
844 * i386-opc.h (CpuCET): New enum.
845 (CpuUnused): Commented out.
846 (i386_cpu_flags): Add cpucet.
847 * i386-opc.tbl: Add Intel CET instructions.
848 * i386-init.h: Regenerated.
849 * i386-tbl.h: Likewise.
850
73f07bff
AM		 8512017-03-06 Alan Modra <amodra@gmail.com>
852
853 PR 21124
854 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
855 (extract_raq, extract_ras, extract_rbx): New functions.
856 (powerpc_operands): Use opposite corresponding insert function.
857 (Q_MASK): Define.
858 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
859 register restriction.
860
65b48a81
PB		 8612017-02-28 Peter Bergner <bergner@vnet.ibm.com>
862
863 * disassemble.c Include "safe-ctype.h".
864 (disassemble_init_for_target): Handle s390 init.
865 (remove_whitespace_and_extra_commas): New function.
866 (disassembler_options_cmp): Likewise.
867 * arm-dis.c: Include "libiberty.h".
868 (NUM_ELEM): Delete.
869 (regnames): Use long disassembler style names.
870 Add force-thumb and no-force-thumb options.
871 (NUM_ARM_REGNAMES): Rename from this...
872 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
873 (get_arm_regname_num_options): Delete.
874 (set_arm_regname_option): Likewise.
875 (get_arm_regnames): Likewise.
876 (parse_disassembler_options): Likewise.
877 (parse_arm_disassembler_option): Rename from this...
878 (parse_arm_disassembler_options): ...to this. Make static.
879 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
880 (print_insn): Use parse_arm_disassembler_options.
881 (disassembler_options_arm): New function.
882 (print_arm_disassembler_options): Handle updated regnames.
883 * ppc-dis.c: Include "libiberty.h".
884 (ppc_opts): Add "32" and "64" entries.
885 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
886 (powerpc_init_dialect): Add break to switch statement.
887 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
888 (disassembler_options_powerpc): New function.
889 (print_ppc_disassembler_options): Use ARRAY_SIZE.
890 Remove printing of "32" and "64".
891 * s390-dis.c: Include "libiberty.h".
892 (init_flag): Remove unneeded variable.
893 (struct s390_options_t): New structure type.
894 (options): New structure.
895 (init_disasm): Rename from this...
896 (disassemble_init_s390): ...to this. Add initializations for
897 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
898 (print_insn_s390): Delete call to init_disasm.
899 (disassembler_options_s390): New function.
900 (print_s390_disassembler_options): Print using information from
901 struct 'options'.
902 * po/opcodes.pot: Regenerate.
903
15c7c1d8
JB		 9042017-02-28 Jan Beulich <jbeulich@suse.com>
905
906 * i386-dis.c (PCMPESTR_Fixup): New.
907 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
908 (prefix_table): Use PCMPESTR_Fixup.
909 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
910 PCMPESTR_Fixup.
911 (vex_w_table): Delete VPCMPESTR{I,M} entries.
912 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
913 Split 64-bit and non-64-bit variants.
914 * opcodes/i386-tbl.h: Re-generate.
915
582e12bf
RS		 9162017-02-24 Richard Sandiford <richard.sandiford@arm.com>
917
918 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
919 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
920 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
921 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
922 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
923 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
924 (OP_SVE_V_HSD): New macros.
925 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
926 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
927 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
928 (aarch64_opcode_table): Add new SVE instructions.
929 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
930 for rotation operands. Add new SVE operands.
931 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
932 (ins_sve_quad_index): Likewise.
933 (ins_imm_rotate): Split into...
934 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
935 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
936 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
937 functions.
938 (aarch64_ins_sve_addr_ri_s4): New function.
939 (aarch64_ins_sve_quad_index): Likewise.
940 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
941 * aarch64-asm-2.c: Regenerate.
942 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
943 (ext_sve_quad_index): Likewise.
944 (ext_imm_rotate): Split into...
945 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
946 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
947 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
948 functions.
949 (aarch64_ext_sve_addr_ri_s4): New function.
950 (aarch64_ext_sve_quad_index): Likewise.
951 (aarch64_ext_sve_index): Allow quad indices.
952 (do_misc_decoding): Likewise.
953 * aarch64-dis-2.c: Regenerate.
954 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
955 aarch64_field_kinds.
956 (OPD_F_OD_MASK): Widen by one bit.
957 (OPD_F_NO_ZR): Bump accordingly.
958 (get_operand_field_width): New function.
959 * aarch64-opc.c (fields): Add new SVE fields.
960 (operand_general_constraint_met_p): Handle new SVE operands.
961 (aarch64_print_operand): Likewise.
962 * aarch64-opc-2.c: Regenerate.
963
f482d304
RS		 9642017-02-24 Richard Sandiford <richard.sandiford@arm.com>
965
966 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
967 (aarch64_feature_compnum): ...this.
968 (SIMD_V8_3): Replace with...
969 (COMPNUM): ...this.
970 (CNUM_INSN): New macro.
971 (aarch64_opcode_table): Use it for the complex number instructions.
972
7db2c588
JB		 9732017-02-24 Jan Beulich <jbeulich@suse.com>
974
975 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
976
1e9d41d4
SL		 9772017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
978
979 Add support for associating SPARC ASIs with an architecture level.
980 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
981 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
982 decoding of SPARC ASIs.
983
53c4d625
JB		 9842017-02-23 Jan Beulich <jbeulich@suse.com>
985
986 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
987 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
988
11648de5
JB		 9892017-02-21 Jan Beulich <jbeulich@suse.com>
990
991 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
992 1 (instead of to itself). Correct typo.
993
f98d33be
AW		 9942017-02-14 Andrew Waterman <andrew@sifive.com>
995
996 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
997 pseudoinstructions.
998
773fb663
RS		 9992017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1000
1001 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1002 (aarch64_sys_reg_supported_p): Handle them.
1003
cc07cda6
CZ		 10042017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1005
1006 * arc-opc.c (UIMM6_20R): Define.
1007 (SIMM12_20): Use above.
1008 (SIMM12_20R): Define.
1009 (SIMM3_5_S): Use above.
1010 (UIMM7_A32_11R_S): Define.
1011 (UIMM7_9_S): Use above.
1012 (UIMM3_13R_S): Define.
1013 (SIMM11_A32_7_S): Use above.
1014 (SIMM9_8R): Define.
1015 (UIMM10_A32_8_S): Use above.
1016 (UIMM8_8R_S): Define.
1017 (W6): Use above.
1018 (arc_relax_opcodes): Use all above defines.
1019
66a5a740
VG		 10202017-02-15 Vineet Gupta <vgupta@synopsys.com>
1021
1022 * arc-regs.h: Distinguish some of the registers different on
1023 ARC700 and HS38 cpus.
1024
7e0de605
AM		 10252017-02-14 Alan Modra <amodra@gmail.com>
1026
1027 PR 21118
1028 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1029 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1030
54064fdb
AM		 10312017-02-11 Stafford Horne <shorne@gmail.com>
1032 Alan Modra <amodra@gmail.com>
1033
1034 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1035 Use insn_bytes_value and insn_int_value directly instead. Don't
1036 free allocated memory until function exit.
1037
dce75bf9
NP		 10382017-02-10 Nicholas Piggin <npiggin@gmail.com>
1039
1040 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1041
1b7e3d2f
NC		 10422017-02-03 Nick Clifton <nickc@redhat.com>
1043
1044 PR 21096
1045 * aarch64-opc.c (print_register_list): Ensure that the register
1046 list index will fir into the tb buffer.
1047 (print_register_offset_address): Likewise.
1048 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1049
8ec5cf65
AD		 10502017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1051
1052 PR 21056
1053 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1054 instructions when the previous fetch packet ends with a 32-bit
1055 instruction.
1056
a1aa5e81
DD		 10572017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1058
1059 * pru-opc.c: Remove vague reference to a future GDB port.
1060
add3afb2
NC		 10612017-01-20 Nick Clifton <nickc@redhat.com>
1062
1063 * po/ga.po: Updated Irish translation.
1064
c13a63b0
SN		 10652017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1066
1067 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1068
9608051a
YQ		 10692017-01-13 Yao Qi <yao.qi@linaro.org>
1070
1071 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1072 if FETCH_DATA returns 0.
1073 (m68k_scan_mask): Likewise.
1074 (print_insn_m68k): Update code to handle -1 return value.
1075
f622ea96
YQ		 10762017-01-13 Yao Qi <yao.qi@linaro.org>
1077
1078 * m68k-dis.c (enum print_insn_arg_error): New.
1079 (NEXTBYTE): Replace -3 with
1080 PRINT_INSN_ARG_MEMORY_ERROR.
1081 (NEXTULONG): Likewise.
1082 (NEXTSINGLE): Likewise.
1083 (NEXTDOUBLE): Likewise.
1084 (NEXTDOUBLE): Likewise.
1085 (NEXTPACKED): Likewise.
1086 (FETCH_ARG): Likewise.
1087 (FETCH_DATA): Update comments.
1088 (print_insn_arg): Update comments. Replace magic numbers with
1089 enum.
1090 (match_insn_m68k): Likewise.
1091
620214f7
IT		 10922017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1093
1094 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1095 * i386-dis-evex.h (evex_table): Updated.
1096 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1097 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1098 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1099 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1100 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1101 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1102 * i386-init.h: Regenerate.
1103 * i386-tbl.h: Ditto.
1104
d95014a2
YQ		 11052017-01-12 Yao Qi <yao.qi@linaro.org>
1106
1107 * msp430-dis.c (msp430_singleoperand): Return -1 if
1108 msp430dis_opcode_signed returns false.
1109 (msp430_doubleoperand): Likewise.
1110 (msp430_branchinstr): Return -1 if
1111 msp430dis_opcode_unsigned returns false.
1112 (msp430x_calla_instr): Likewise.
1113 (print_insn_msp430): Likewise.
1114
0ae60c3e
NC		 11152017-01-05 Nick Clifton <nickc@redhat.com>
1116
1117 PR 20946
1118 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1119 could not be matched.
1120 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1121 NULL.
1122
d74d4880
SN		 11232017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1124
1125 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1126 (aarch64_opcode_table): Use RCPC_INSN.
1127
cc917fd9
KC		 11282017-01-03 Kito Cheng <kito.cheng@gmail.com>
1129
1130 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1131 extension.
1132 * riscv-opcodes/all-opcodes: Likewise.
1133
b52d3cfc
DP		 11342017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1135
1136 * riscv-dis.c (print_insn_args): Add fall through comment.
1137
f90c58d5
NC		 11382017-01-03 Nick Clifton <nickc@redhat.com>
1139
1140 * po/sr.po: New Serbian translation.
1141 * configure.ac (ALL_LINGUAS): Add sr.
1142 * configure: Regenerate.
1143
f47b0d4a
AM		 11442017-01-02 Alan Modra <amodra@gmail.com>
1145
1146 * epiphany-desc.h: Regenerate.
1147 * epiphany-opc.h: Regenerate.
1148 * fr30-desc.h: Regenerate.
1149 * fr30-opc.h: Regenerate.
1150 * frv-desc.h: Regenerate.
1151 * frv-opc.h: Regenerate.
1152 * ip2k-desc.h: Regenerate.
1153 * ip2k-opc.h: Regenerate.
1154 * iq2000-desc.h: Regenerate.
1155 * iq2000-opc.h: Regenerate.
1156 * lm32-desc.h: Regenerate.
1157 * lm32-opc.h: Regenerate.
1158 * m32c-desc.h: Regenerate.
1159 * m32c-opc.h: Regenerate.
1160 * m32r-desc.h: Regenerate.
1161 * m32r-opc.h: Regenerate.
1162 * mep-desc.h: Regenerate.
1163 * mep-opc.h: Regenerate.
1164 * mt-desc.h: Regenerate.
1165 * mt-opc.h: Regenerate.
1166 * or1k-desc.h: Regenerate.
1167 * or1k-opc.h: Regenerate.
1168 * xc16x-desc.h: Regenerate.
1169 * xc16x-opc.h: Regenerate.
1170 * xstormy16-desc.h: Regenerate.
1171 * xstormy16-opc.h: Regenerate.
1172
2571583a
AM		 11732017-01-02 Alan Modra <amodra@gmail.com>
1174
1175 Update year range in copyright notice of all files.
1176
5c1ad6b5 1177For older changes see ChangeLog-2016
3499769a 1178\f
5c1ad6b5 1179Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1180
1181Copying and distribution of this file, with or without modification,
1182are permitted in any medium without royalty provided the copyright
1183notice and this notice are preserved.
1184
1185Local Variables:
1186mode: change-log
1187left-margin: 8
1188fill-column: 74
1189version-control: never
1190End:
GDB Binutils - Deliverables
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