[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2008-04-07  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_VEX_38XX): Add a tab.
	(PREFIX_VEX_3AXX): Likewis.

2008-04-07  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove 4 extra blank lines.

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	* i386-opc.tbl: Likewise.

	* i386-opc.h (CpuCLMUL): Renamed to ...
	(CpuPCLMUL): This.
	(CpuFMA): Updated.
	(i386_cpu_flags): Replace cpuclmul with cpupclmul.

	* i386-init.h: Regenerated.

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_register): New.
	(OP_E_memory): Likewise.
	(OP_VEX): Likewise.
	(OP_EX_Vex): Likewise.
	(OP_EX_VexW): Likewise.
	(OP_XMM_Vex): Likewise.
	(OP_XMM_VexW): Likewise.
	(OP_REG_VexI4): Likewise.
	(PCLMUL_Fixup): Likewise.
	(VEXI4_Fixup): Likewise.
	(VZERO_Fixup): Likewise.
	(VCMP_Fixup): Likewise.
	(VPERMIL2_Fixup): Likewise.
	(rex_original): Likewise.
	(rex_ignored): Likewise.
	(Mxmm): Likewise.
	(XMM): Likewise.
	(EXxmm): Likewise.
	(EXxmmq): Likewise.
	(EXymmq): Likewise.
	(Vex): Likewise.
	(Vex128): Likewise.
	(Vex256): Likewise.
	(VexI4): Likewise.
	(EXdVex): Likewise.
	(EXqVex): Likewise.
	(EXVexW): Likewise.
	(EXdVexW): Likewise.
	(EXqVexW): Likewise.
	(XMVex): Likewise.
	(XMVexW): Likewise.
	(XMVexI4): Likewise.
	(PCLMUL): Likewise.
	(VZERO): Likewise.
	(VCMP): Likewise.
	(VPERMIL2): Likewise.
	(xmm_mode): Likewise.
	(xmmq_mode): Likewise.
	(ymmq_mode): Likewise.
	(vex_mode): Likewise.
	(vex128_mode): Likewise.
	(vex256_mode): Likewise.
	(USE_VEX_C4_TABLE): Likewise.
	(USE_VEX_C5_TABLE): Likewise.
	(USE_VEX_LEN_TABLE): Likewise.
	(VEX_C4_TABLE): Likewise.
	(VEX_C5_TABLE): Likewise.
	(VEX_LEN_TABLE): Likewise.
	(REG_VEX_XX): Likewise.
	(MOD_VEX_XXX): Likewise.
	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	(PREFIX_0F3A44): Likewise.
	(PREFIX_0F3ADF): Likewise.
	(PREFIX_VEX_XXX): Likewise.
	(VEX_OF): Likewise.
	(VEX_OF38): Likewise.
	(VEX_OF3A): Likewise.
	(VEX_LEN_XXX): Likewise.
	(vex): Likewise.
	(need_vex): Likewise.
	(need_vex_reg): Likewise.
	(vex_i4_done): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(OP_REG_VexI4): Likewise.
	(vex_cmp_op): Likewise.
	(pclmul_op): Likewise.
	(vpermil2_op): Likewise.
	(m_mode): Updated.
	(es_reg): Likewise.
	(PREFIX_0F38F0): Likewise.
	(PREFIX_0F3A60): Likewise.
	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
	and PREFIX_VEX_XXX entries.
	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
	PREFIX_0F3ADF.
	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
	Add MOD_VEX_XXX entries.
	(ckprefix): Initialize rex_original and rex_ignored.  Store the
	REX byte in rex_original.
	(get_valid_dis386): Handle the implicit prefix in VEX prefix
	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
	calling get_valid_dis386.  Use rex_original and rex_ignored when
	printing out REX.
	(putop): Handle "XY".
	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
	ymmq_mode.
	(OP_E_extended): Updated to use OP_E_register and
	OP_E_memory.
	(OP_XMM): Handle VEX.
	(OP_EX): Likewise.
	(XMM_Fixup): Likewise.
	(CMP_Fixup): Use ARRAY_SIZE.

	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
	(operand_type_init): Add OPERAND_TYPE_REGYMM and
	OPERAND_TYPE_VEX_IMM4.
	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
	VexImmExt and SSE2AVX.
	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.

	* i386-opc.h (CpuAVX): New.
	(CpuAES): Likewise.
	(CpuCLMUL): Likewise.
	(CpuFMA): Likewise.
	(Vex): Likewise.
	(Vex256): Likewise.
	(VexNDS): Likewise.
	(VexNDD): Likewise.
	(VexW0): Likewise.
	(VexW1): Likewise.
	(Vex0F): Likewise.
	(Vex0F38): Likewise.
	(Vex0F3A): Likewise.
	(Vex3Sources): Likewise.
	(VexImmExt): Likewise.
	(SSE2AVX): Likewise.
	(RegYMM): Likewise.
	(Ymmword): Likewise.
	(Vex_Imm4): Likewise.
	(Implicit1stXmm0): Likewise.
	(CpuXsave): Updated.
	(CpuLM): Likewise.
	(ByteOkIntel): Likewise.
	(OldGcc): Likewise.
	(Control): Likewise.
	(Unspecified): Likewise.
	(OTMax): Likewise.
	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
	vex3sources, veximmext and sse2avx.
	(i386_operand_type): Add regymm, ymmword and vex_imm4.

	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.

	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-03-26  Bernd Schmidt  <bernd.schmidt@analog.com>

	From  Robin Getz  <robin.getz@analog.com>
	* bfin-dis.c (bu32): Typedef.
	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	(constant_formats[]): Add uimm32 and huimm16.
	(fmtconst_val): New.
	(uimm32): Define.
	(huimm32): Define.
	(imm16_val): Define.
	(luimm16_val): Define.
	(struct saved_state): Define.
	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	(get_allreg): New.
	(decode_LDIMMhalf_0): Print out the whole register value.

	From Jie Zhang  <jie.zhang@analog.com>
	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	multiply and multiply-accumulate to data register instruction.

	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	c_imm32, c_huimm32e): Define.
	(constant_formats): Add flags for printing decimal, leading spaces, and
	exact symbols.
	(comment, parallel): Add global flags in all disassembly.
	(fmtconst): Take advantage of new flags, and print default in hex.
	(fmtconst_val): Likewise.
	(decode_macfunc): Be consistant with spaces, tabs, comments,
	capitalization in disassembly, fix minor coding style issues.
	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	_print_insn_bfin, print_insn_bfin): Likewise.

2008-03-17  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

	* aclocal.m4: Regenerate.
	* configure: Likewise.
	* Makefile.in: Likewise.

2008-03-13  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2008-03-07  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c (powerpc_opcodes): Order and format.

2008-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	* i386-tbl.h: Regenerated.

2008-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	x86-64.
	* i386-tbl.h: Regenerated.

2008-02-21  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	and Fword for far indirect jmp. Allow Reg16 and Word for near
	indirect jmp on x86-64. Disallow Fword for lcall.
	* i386-tbl.h: Re-generate.

2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>

	* cr16-opc.c  (cr16_num_optab): Defined

2008-02-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c  (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	* i386-init.h: Regenerated.

2008-02-14  Nick Clifton  <nickc@redhat.com>

	PR binutils/5524
	* configure.in (SHARED_LIBADD): Select the correct host specific
	file extension for shared libraries.
	* configure: Regenerate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.h (RegFlat): New.
	* i386-reg.tbl (flat): Add.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (a_mode): New.
	(cond_jump_mode): Adjust.
	(Ma): Change to a_mode.
	(intel_operand_size): Handle a_mode.
	* i386-opc.tbl: Allow Dword and Qword for bound.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-gen.c (process_i386_registers): Process new fields.
	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	unsigned char. Add dw2_regnum and Dw2Inval.
	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	register names.
	* i386-tbl.h: Re-generate.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
	* i386-init.h: Updated.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flags): Add CpuXsave.

	* i386-opc.h (CpuXsave): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpuxsave.

	* i386-dis.c (MOD_0FAE_REG_4): New.
	(RM_0F01_REG_2): Likewise.
	(MOD_0FAE_REG_5): Updated.
	(RM_0F01_REG_3): Likewise.
	(reg_table): Use MOD_0FAE_REG_4.
	(mod_table): Use RM_0F01_REG_2.  Add MOD_0FAE_REG_4.  Updated
	for xrstor.
	(rm_table): Add RM_0F01_REG_2.

	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-02-11  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	* i386-tbl.h: Re-generate.

2008-02-04  H.J. Lu  <hongjiu.lu@intel.com>

	PR 5715
	* configure: Regenerated.

2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>

	* mips-dis.c: Update copyright.
	(mips_arch_choices): Add Octeon.
	* mips-opc.c: Update copyright.
	(IOCT): New macro.
	(mips_builtin_opcodes): Add Octeon instruction synciobdma.

2008-01-29  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c: Support optional L form mtmsr.

2008-01-24  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_extended): Handle r12 like rsp.

2008-01-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	* i386-init.h: Regenerated.

2008-01-23  Tristan Gingold  <gingold@adacore.com>

	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuMMX2): Removed.
	(CpuSSE): Updated.

	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	CPU_SMX_FLAGS.
	* i386-init.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Use Qword on movddup.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (Mx): New.
	(PREFIX_0FC3): Likewise.
	(PREFIX_0FC7_REG_6): Updated.
	(dis386_twobyte): Use PREFIX_0FC3.
	(prefix_table): Add PREFIX_0FC3.  Use Mq on movntq and movntsd.
	Use Mx on movntps, movntpd, movntdq and movntdqa.  Use Md on
	movntss.

2008-01-14  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	(operand_types): Add Mem.

	* i386-opc.h (IntelSyntax): New.
	* i386-opc.h (Mem): New.
	(Byte): Updated.
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Add intelsyntax.
	(i386_operand_type): Add mem.

	* i386-opc.tbl: Remove Reg16 from movnti.  Add sizes to more
	instructions.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-13  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (Byte): Fix a typo.

2008-01-12  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (operand_type_init): Add Dword to
	OPERAND_TYPE_ACC32.  Add Qword to OPERAND_TYPE_ACC64.
	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	Qword and Xmmword.
	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	Xmmword, Unspecified and Anysize.
	(set_bitfield): Make Mmword an alias of Qword.  Make Oword
	an alias of Xmmword.

	* i386-opc.h (CheckSize): Removed.
	(Byte): Updated.
	(Word): Likewise.
	(Dword): Likewise.
	(Qword): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(OTMax): Likewise.
	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	qword and xmmword.
	(Fword): New.
	(TBYTE): Likewise.
	(Unspecified): Likewise.
	(Anysize): Likewise.
	(i386_operand_type): Add byte, word, dword, fword, qword,
	tbyte xmmword, unspecified and anysize.

	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	Tbyte, Xmmword, Unspecified and Anysize.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-10  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	(REG_0F18): Updated.
	(reg_table): Updated.
	(dis386_twobyte): Updated.  Use "nopQ" on 0x19 to 0x1e.
	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (set_bitfield): Use fail () on error.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (lineno): New.
	(filename): Likewise.
	(set_bitfield): Report filename and line numer on error.
	(process_i386_opcodes): Set filename and update lineno.
	(process_i386_registers): Likewise.

2008-01-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	ATTSyntax.

	* i386-opc.h (IntelMnemonic): Renamed to ..
	(ATTSyntax): This
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	and intelsyntax.

	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax 
	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	* i386-tbl.h: Regenerated.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c: Update copyright to 2008.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	* i386-tbl.h: Regenerated.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	CpuSSE4_2_Or_ABM.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	(CpuSSE4_2_Or_ABM): Likewise.
	(CpuLM): Updated.
	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.

	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
	and CpuPadLock, respectively.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove No_xSuf.

	* i386-opc.h (No_xSuf): Removed.
	(CheckSize): Updated.

	* i386-tbl.h: Regenerated.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	CPU_SSE5_FLAGS.
	(cpu_flags): Add CpuSSE4_2_Or_ABM.

	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpusse4_2_or_abm.

	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	CpuABM|CpuSSE4_2 on popcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h: Update comments.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	Byte, Word, Dword, QWord and Xmmword.

	* i386-opc.h (No_xSuf): New.
	(CheckSize): Likewise.
	(Byte): Likewise.
	(Word): Likewise.
	(Dword): Likewise.
	(QWord): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	Dword, QWord and Xmmword.

	* i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
	used.
	* i386-tbl.h: Regenerated.

2008-01-02  Mark Kettenis  <kettenis@gnu.org>

	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	From Miod Vallat.

For older changes see ChangeLog-2007
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
06c8514a L	1	2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
	2
	3	* i386-dis.c (PREFIX_VEX_38XX): Add a tab.
	4	(PREFIX_VEX_3AXX): Likewis.
	5
b122c285 L	6	2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
	7
	8	* i386-opc.tbl: Remove 4 extra blank lines.
	9
594ab6a3 L	10	2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
	11
	12	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	13	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	14	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	15	* i386-opc.tbl: Likewise.
	16
	17	* i386-opc.h (CpuCLMUL): Renamed to ...
	18	(CpuPCLMUL): This.
	19	(CpuFMA): Updated.
	20	(i386_cpu_flags): Replace cpuclmul with cpupclmul.
	21
	22	* i386-init.h: Regenerated.
	23
c0f3af97 L	24	2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
	25
	26	* i386-dis.c (OP_E_register): New.
	27	(OP_E_memory): Likewise.
	28	(OP_VEX): Likewise.
	29	(OP_EX_Vex): Likewise.
	30	(OP_EX_VexW): Likewise.
	31	(OP_XMM_Vex): Likewise.
	32	(OP_XMM_VexW): Likewise.
	33	(OP_REG_VexI4): Likewise.
	34	(PCLMUL_Fixup): Likewise.
	35	(VEXI4_Fixup): Likewise.
	36	(VZERO_Fixup): Likewise.
	37	(VCMP_Fixup): Likewise.
	38	(VPERMIL2_Fixup): Likewise.
	39	(rex_original): Likewise.
	40	(rex_ignored): Likewise.
	41	(Mxmm): Likewise.
	42	(XMM): Likewise.
	43	(EXxmm): Likewise.
	44	(EXxmmq): Likewise.
	45	(EXymmq): Likewise.
	46	(Vex): Likewise.
	47	(Vex128): Likewise.
	48	(Vex256): Likewise.
	49	(VexI4): Likewise.
	50	(EXdVex): Likewise.
	51	(EXqVex): Likewise.
	52	(EXVexW): Likewise.
	53	(EXdVexW): Likewise.
	54	(EXqVexW): Likewise.
	55	(XMVex): Likewise.
	56	(XMVexW): Likewise.
	57	(XMVexI4): Likewise.
	58	(PCLMUL): Likewise.
	59	(VZERO): Likewise.
	60	(VCMP): Likewise.
	61	(VPERMIL2): Likewise.
	62	(xmm_mode): Likewise.
	63	(xmmq_mode): Likewise.
	64	(ymmq_mode): Likewise.
	65	(vex_mode): Likewise.
	66	(vex128_mode): Likewise.
	67	(vex256_mode): Likewise.
	68	(USE_VEX_C4_TABLE): Likewise.
	69	(USE_VEX_C5_TABLE): Likewise.
	70	(USE_VEX_LEN_TABLE): Likewise.
	71	(VEX_C4_TABLE): Likewise.
	72	(VEX_C5_TABLE): Likewise.
	73	(VEX_LEN_TABLE): Likewise.
	74	(REG_VEX_XX): Likewise.
	75	(MOD_VEX_XXX): Likewise.
	76	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	77	(PREFIX_0F3A44): Likewise.
	78	(PREFIX_0F3ADF): Likewise.
	79	(PREFIX_VEX_XXX): Likewise.
	80	(VEX_OF): Likewise.
	81	(VEX_OF38): Likewise.
	82	(VEX_OF3A): Likewise.
	83	(VEX_LEN_XXX): Likewise.
	84	(vex): Likewise.
	85	(need_vex): Likewise.
	86	(need_vex_reg): Likewise.
	87	(vex_i4_done): Likewise.
88	(vex_table): Likewise.
89	(vex_len_table): Likewise.
90	(OP_REG_VexI4): Likewise.
91	(vex_cmp_op): Likewise.
92	(pclmul_op): Likewise.
93	(vpermil2_op): Likewise.
94	(m_mode): Updated.
95	(es_reg): Likewise.
96	(PREFIX_0F38F0): Likewise.
97	(PREFIX_0F3A60): Likewise.
98	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
99	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
100	and PREFIX_VEX_XXX entries.
101	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
102	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
103	PREFIX_0F3ADF.
104	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
105	Add MOD_VEX_XXX entries.
106	(ckprefix): Initialize rex_original and rex_ignored. Store the
107	REX byte in rex_original.
108	(get_valid_dis386): Handle the implicit prefix in VEX prefix
109	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
110	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
111	calling get_valid_dis386. Use rex_original and rex_ignored when
112	printing out REX.
113	(putop): Handle "XY".
114	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
115	ymmq_mode.
116	(OP_E_extended): Updated to use OP_E_register and
117	OP_E_memory.
118	(OP_XMM): Handle VEX.
119	(OP_EX): Likewise.
120	(XMM_Fixup): Likewise.
121	(CMP_Fixup): Use ARRAY_SIZE.
122
123	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
124	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
125	(operand_type_init): Add OPERAND_TYPE_REGYMM and
126	OPERAND_TYPE_VEX_IMM4.
127	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
128	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
129	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
130	VexImmExt and SSE2AVX.
131	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
132
133	* i386-opc.h (CpuAVX): New.
134	(CpuAES): Likewise.
135	(CpuCLMUL): Likewise.
136	(CpuFMA): Likewise.
137	(Vex): Likewise.
138	(Vex256): Likewise.
139	(VexNDS): Likewise.
140	(VexNDD): Likewise.
141	(VexW0): Likewise.
142	(VexW1): Likewise.
143	(Vex0F): Likewise.
144	(Vex0F38): Likewise.
145	(Vex0F3A): Likewise.
146	(Vex3Sources): Likewise.
147	(VexImmExt): Likewise.
148	(SSE2AVX): Likewise.
149	(RegYMM): Likewise.
150	(Ymmword): Likewise.
151	(Vex_Imm4): Likewise.
152	(Implicit1stXmm0): Likewise.
153	(CpuXsave): Updated.
154	(CpuLM): Likewise.
155	(ByteOkIntel): Likewise.
156	(OldGcc): Likewise.
157	(Control): Likewise.
158	(Unspecified): Likewise.
159	(OTMax): Likewise.
160	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
161	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
162	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
163	vex3sources, veximmext and sse2avx.
164	(i386_operand_type): Add regymm, ymmword and vex_imm4.
165
166	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
167
168	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
169
170	* i386-init.h: Regenerated.
171	* i386-tbl.h: Likewise.
172
b21c9cb4 BS	173	2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
	174
	175	From Robin Getz <robin.getz@analog.com>
	176	* bfin-dis.c (bu32): Typedef.
	177	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	178	(constant_formats[]): Add uimm32 and huimm16.
	179	(fmtconst_val): New.
	180	(uimm32): Define.
	181	(huimm32): Define.
	182	(imm16_val): Define.
	183	(luimm16_val): Define.
	184	(struct saved_state): Define.
	185	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	186	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	187	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	188	(get_allreg): New.
	189	(decode_LDIMMhalf_0): Print out the whole register value.
	190
ee171c8f BS	191	From Jie Zhang <jie.zhang@analog.com>
	192	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	193	multiply and multiply-accumulate to data register instruction.
	194
086134ec BS	195	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	196	c_imm32, c_huimm32e): Define.
	197	(constant_formats): Add flags for printing decimal, leading spaces, and
	198	exact symbols.
	199	(comment, parallel): Add global flags in all disassembly.
	200	(fmtconst): Take advantage of new flags, and print default in hex.
	201	(fmtconst_val): Likewise.
	202	(decode_macfunc): Be consistant with spaces, tabs, comments,
	203	capitalization in disassembly, fix minor coding style issues.
	204	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	205	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	206	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	207	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	208	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	209	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	210	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	211	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	212	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	213	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	214	_print_insn_bfin, print_insn_bfin): Likewise.
	215
58c85be7 RW	216	2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
	217
	218	* aclocal.m4: Regenerate.
	219	* configure: Likewise.
	220	* Makefile.in: Likewise.
	221
50e7d84b AM	222	2008-03-13 Alan Modra <amodra@bigpond.net.au>
	223
	224	* Makefile.am: Run "make dep-am".
	225	* Makefile.in: Regenerate.
	226	* configure: Regenerate.
	227
de866fcc AM	228	2008-03-07 Alan Modra <amodra@bigpond.net.au>
	229
	230	* ppc-opc.c (powerpc_opcodes): Order and format.
	231
28dbc079 L	232	2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
	233
	234	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	235	* i386-tbl.h: Regenerated.
	236
849830bd L	237	2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
	238
	239	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	240	x86-64.
	241	* i386-tbl.h: Regenerated.
	242
743ddb6b JB	243	2008-02-21 Jan Beulich <jbeulich@novell.com>
	244
	245	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	246	and Fword for far indirect jmp. Allow Reg16 and Word for near
	247	indirect jmp on x86-64. Disallow Fword for lcall.
	248	* i386-tbl.h: Re-generate.
	249
796d5313 NC	250	2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
	251
	252	* cr16-opc.c (cr16_num_optab): Defined
	253
65da13b5 L	254	2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
	255
	256	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	257	* i386-init.h: Regenerated.
	258
0e336180 NC	259	2008-02-14 Nick Clifton <nickc@redhat.com>
	260
	261	PR binutils/5524
	262	* configure.in (SHARED_LIBADD): Select the correct host specific
	263	file extension for shared libraries.
	264	* configure: Regenerate.
	265
b7240065 JB	266	2008-02-13 Jan Beulich <jbeulich@novell.com>
	267
	268	* i386-opc.h (RegFlat): New.
	269	* i386-reg.tbl (flat): Add.
	270	* i386-tbl.h: Re-generate.
	271
34b772a6 JB	272	2008-02-13 Jan Beulich <jbeulich@novell.com>
	273
	274	* i386-dis.c (a_mode): New.
	275	(cond_jump_mode): Adjust.
	276	(Ma): Change to a_mode.
	277	(intel_operand_size): Handle a_mode.
	278	* i386-opc.tbl: Allow Dword and Qword for bound.
	279	* i386-tbl.h: Re-generate.
	280
a60de03c JB	281	2008-02-13 Jan Beulich <jbeulich@novell.com>
	282
	283	* i386-gen.c (process_i386_registers): Process new fields.
	284	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	285	unsigned char. Add dw2_regnum and Dw2Inval.
	286	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	287	register names.
	288	* i386-tbl.h: Re-generate.
	289
f03fe4c1 L	290	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
f03fe4c1 L	291
4b6bc8eb	292	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1 L	293	* i386-init.h: Updated.
f03fe4c1 L	294
475a2301 L	295	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
	296
	297	* i386-gen.c (cpu_flags): Add CpuXsave.
	298
	299	* i386-opc.h (CpuXsave): New.
4b6bc8eb	300	(CpuLM): Updated.
475a2301 L	301	(i386_cpu_flags): Add cpuxsave.
	302
	303	* i386-dis.c (MOD_0FAE_REG_4): New.
	304	(RM_0F01_REG_2): Likewise.
	305	(MOD_0FAE_REG_5): Updated.
	306	(RM_0F01_REG_3): Likewise.
	307	(reg_table): Use MOD_0FAE_REG_4.
	308	(mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
	309	for xrstor.
	310	(rm_table): Add RM_0F01_REG_2.
	311
	312	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	313	* i386-init.h: Regenerated.
	314	* i386-tbl.h: Likewise.
	315
595785c6	316	2008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc	317
595785c6 JB	318	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	319	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	320	* i386-tbl.h: Re-generate.
	321
bb8541b9 L	322	2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
	323
	324	PR 5715
	325	* configure: Regenerated.
	326
57b592a3 AN	327	2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
	328
	329	* mips-dis.c: Update copyright.
	330	(mips_arch_choices): Add Octeon.
	331	* mips-opc.c: Update copyright.
	332	(IOCT): New macro.
	333	(mips_builtin_opcodes): Add Octeon instruction synciobdma.
	334
930bb4cf AM	335	2008-01-29 Alan Modra <amodra@bigpond.net.au>
	336
	337	* ppc-opc.c: Support optional L form mtmsr.
	338
82c18208 L	339	2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
	340
	341	* i386-dis.c (OP_E_extended): Handle r12 like rsp.
	342
599121aa L	343	2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
	344
	345	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	346	* i386-init.h: Regenerated.
	347
80098f51 TG	348	2008-01-23 Tristan Gingold <gingold@adacore.com>
	349
	350	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	351	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
	352
115c7c25 L	353	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	354
	355	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	356	(cpu_flags): Likewise.
	357
	358	* i386-opc.h (CpuMMX2): Removed.
	359	(CpuSSE): Updated.
	360
	361	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE\|Cpu3dnowA.
	362	* i386-init.h: Regenerated.
	363	* i386-tbl.h: Likewise.
	364
6305a203 L	365	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	366
	367	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	368	CPU_SMX_FLAGS.
	369	* i386-init.h: Regenerated.
	370
fd07a1c8 L	371	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	372
	373	* i386-opc.tbl: Use Qword on movddup.
	374	* i386-tbl.h: Regenerated.
	375
321fd21e L	376	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	377
	378	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	379	* i386-tbl.h: Regenerated.
	380
4ee52178 L	381	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	382
	383	* i386-dis.c (Mx): New.
	384	(PREFIX_0FC3): Likewise.
	385	(PREFIX_0FC7_REG_6): Updated.
	386	(dis386_twobyte): Use PREFIX_0FC3.
	387	(prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
	388	Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
	389	movntss.
	390
5c07affc L	391	2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
	392
	393	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	394	(operand_types): Add Mem.
	395
	396	* i386-opc.h (IntelSyntax): New.
	397	* i386-opc.h (Mem): New.
	398	(Byte): Updated.
	399	(Opcode_Modifier_Max): Updated.
	400	(i386_opcode_modifier): Add intelsyntax.
	401	(i386_operand_type): Add mem.
	402
	403	* i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
	404	instructions.
	405
	406	* i386-reg.tbl: Add size for accumulator.
	407
	408	* i386-init.h: Regenerated.
	409	* i386-tbl.h: Likewise.
	410
0d6a2f58 L	411	2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
	412
	413	* i386-opc.h (Byte): Fix a typo.
	414
7d5e4556 L	415	2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
	416
	417	PR gas/5534
	418	* i386-gen.c (operand_type_init): Add Dword to
	419	OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
	420	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	421	Qword and Xmmword.
	422	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	423	Xmmword, Unspecified and Anysize.
	424	(set_bitfield): Make Mmword an alias of Qword. Make Oword
	425	an alias of Xmmword.
	426
	427	* i386-opc.h (CheckSize): Removed.
	428	(Byte): Updated.
	429	(Word): Likewise.
	430	(Dword): Likewise.
	431	(Qword): Likewise.
	432	(Xmmword): Likewise.
	433	(FWait): Updated.
	434	(OTMax): Likewise.
	435	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	436	qword and xmmword.
	437	(Fword): New.
	438	(TBYTE): Likewise.
	439	(Unspecified): Likewise.
	440	(Anysize): Likewise.
	441	(i386_operand_type): Add byte, word, dword, fword, qword,
	442	tbyte xmmword, unspecified and anysize.
	443
	444	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	445	Tbyte, Xmmword, Unspecified and Anysize.
	446
	447	* i386-reg.tbl: Add size for accumulator.
	448
	449	* i386-init.h: Regenerated.
	450	* i386-tbl.h: Likewise.
	451
b5b1fc4f L	452	2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
	453
	454	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	455	(REG_0F18): Updated.
	456	(reg_table): Updated.
	457	(dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
	458	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
	459
50e8458f L	460	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	461
	462	* i386-gen.c (set_bitfield): Use fail () on error.
	463
3d4d5afa L	464	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	465
	466	* i386-gen.c (lineno): New.
	467	(filename): Likewise.
	468	(set_bitfield): Report filename and line numer on error.
	469	(process_i386_opcodes): Set filename and update lineno.
	470	(process_i386_registers): Likewise.
	471
e1d4d893 L	472	2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
	473
	474	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	475	ATTSyntax.
	476
	477	* i386-opc.h (IntelMnemonic): Renamed to ..
	478	(ATTSyntax): This
	479	(Opcode_Modifier_Max): Updated.
	480	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	481	and intelsyntax.
	482
	483	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
	484	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	485	* i386-tbl.h: Regenerated.
	486
6f143e4d L	487	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	488
	489	* i386-gen.c: Update copyright to 2008.
	490	* i386-opc.h: Likewise.
	491	* i386-opc.tbl: Likewise.
	492
	493	* i386-init.h: Regenerated.
	494	* i386-tbl.h: Likewise.
	495
c6add537 L	496	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	497
	498	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	499	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	500	* i386-tbl.h: Regenerated.
	501
3629bb00 L	502	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	503
	504	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	505	CpuSSE4_2_Or_ABM.
	506	(cpu_flags): Likewise.
	507
	508	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	509	(CpuSSE4_2_Or_ABM): Likewise.
	510	(CpuLM): Updated.
	511	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
	512
	513	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	514	Cpu686\|CpuPadLock with CpuSSE4_1\|CpuSSE5, CpuABM\|CpuSSE4_2
	515	and CpuPadLock, respectively.
	516	* i386-init.h: Regenerated.
	517	* i386-tbl.h: Likewise.
	518
24995bd6 L	519	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	520
	521	* i386-gen.c (opcode_modifiers): Remove No_xSuf.
	522
	523	* i386-opc.h (No_xSuf): Removed.
	524	(CheckSize): Updated.
	525
	526	* i386-tbl.h: Regenerated.
	527
e0329a22 L	528	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	529
	530	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	531	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	532	CPU_SSE5_FLAGS.
	533	(cpu_flags): Add CpuSSE4_2_Or_ABM.
	534
	535	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	536	(CpuLM): Updated.
	537	(i386_cpu_flags): Add cpusse4_2_or_abm.
	538
	539	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	540	CpuABM\|CpuSSE4_2 on popcnt.
	541	* i386-init.h: Regenerated.
	542	* i386-tbl.h: Likewise.
	543
f2a9c676 L	544	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	545
	546	* i386-opc.h: Update comments.
	547
d978b5be L	548	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	549
	550	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	551	* i386-opc.h: Likewise.
	552	* i386-opc.tbl: Likewise.
	553
582d5edd L	554	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	555
	556	PR gas/5534
	557	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	558	Byte, Word, Dword, QWord and Xmmword.
	559
	560	* i386-opc.h (No_xSuf): New.
	561	(CheckSize): Likewise.
	562	(Byte): Likewise.
	563	(Word): Likewise.
	564	(Dword): Likewise.
	565	(QWord): Likewise.
	566	(Xmmword): Likewise.
	567	(FWait): Updated.
	568	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	569	Dword, QWord and Xmmword.
	570
	571	* i386-opc.tbl: Add CheckSize\|QWord to movq if IgnoreSize is
	572	used.
	573	* i386-tbl.h: Regenerated.
	574
3fe15143 MK	575	2008-01-02 Mark Kettenis <kettenis@gnu.org>
	576
	577	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	578	From Miod Vallat.
	579
6c7ac64e	580	For older changes see ChangeLog-2007
252b5132 RH	581	\f
252b5132 RH	582	Local Variables:
2f6d2f85 NC	583	mode: change-log
	584	left-margin: 8
	585	fill-column: 74
252b5132 RH	586	version-control: never
252b5132 RH	587	End: