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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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9b4e5766
PB		 12008-08-01 Peter Bergner <bergner@vnet.ibm.com>
2
3 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
4 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
5 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
6 * ppc-opc.c (insert_xt6): New static function.
7 (extract_xt6): Likewise.
8 (insert_xa6): Likewise.
9 (extract_xa6: Likewise.
10 (insert_xb6): Likewise.
11 (extract_xb6): Likewise.
12 (insert_xb6s): Likewise.
13 (extract_xb6s): Likewise.
14 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
15 XX3DM_MASK, PPCVSX): New.
16 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
17 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
18
20fd6e2e
PA		 192008-08-01 Pedro Alves <pedro@codesourcery.com>
20
21 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
22 * Makefile.in: Regenerate.
23
a656ed5b
L		 242008-08-01 H.J. Lu <hongjiu.lu@intel.com>
25
26 * i386-reg.tbl: Use Dw2Inval on AVX registers.
27 * i386-tbl.h: Regenerated.
28
081ba1b3
AM		 292008-07-30 Michael J. Eager <eager@eagercon.com>
30
31 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
32 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
33 (insert_sprg, PPC405): Use PPC_OPCODE_405.
34 (powerpc_opcodes): Add Xilinx APU related opcodes.
35
0af1713e
AM		 362008-07-30 Alan Modra <amodra@bigpond.net.au>
37
38 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
39
30c09090
RS		 402008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
41
42 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
43
c27e721e
AN		 442008-07-07 Adam Nemet <anemet@caviumnetworks.com>
45
46 * mips-opc.c (CP): New macro.
47 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
48 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
49 dmtc2 Octeon instructions.
50
bd2e2557
SS		 512008-07-07 Stan Shebs <stan@codesourcery.com>
52
53 * dis-init.c (init_disassemble_info): Init endian_code field.
54 * arm-dis.c (print_insn): Disassemble code according to
55 setting of endian_code.
56 (print_insn_big_arm): Detect when BE8 extension flag has been set.
57
6ba2a415
RS		 582008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
59
60 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
61 for ELF symbols.
62
c8187e15
PB		 632008-06-25 Peter Bergner <bergner@vnet.ibm.com>
64
65 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
66 (print_ppc_disassembler_options): Likewise.
67 * ppc-opc.c (PPC464): Define.
68 (powerpc_opcodes): Add mfdcrux and mtdcrux.
69
7a283e07
RW		 702008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
71
72 * configure: Regenerate.
73
fa452fa6
PB		 742008-06-13 Peter Bergner <bergner@vnet.ibm.com>
75
76 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
77 ppc_cpu_t typedef.
78 (struct dis_private): New.
79 (POWERPC_DIALECT): New define.
80 (powerpc_dialect): Renamed to...
81 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
82 struct dis_private.
83 (print_insn_big_powerpc): Update for using structure in
84 info->private_data.
85 (print_insn_little_powerpc): Likewise.
86 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
87 (skip_optional_operands): Likewise.
88 (print_insn_powerpc): Likewise. Remove initialization of dialect.
89 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
90 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
91 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
92 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
93 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
94 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
95 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
96 param to be of type ppc_cpu_t. Update prototype.
97
bb35fb24
NC		 982008-06-12 Adam Nemet <anemet@caviumnetworks.com>
99
100 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
101 +s, +S.
102 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
103 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
104 syncw, syncws, vm3mulu, vm0 and vmulu.
105
dd3cbb7e
NC		 106 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
107 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
108 seqi, sne and snei.
109
a5dabbb0
L		 1102008-05-30 H.J. Lu <hongjiu.lu@intel.com>
111
112 * i386-opc.tbl: Add vmovd with 64bit operand.
113 * i386-tbl.h: Regenerated.
114
725a9891
MS		 1152008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
116
117 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
118
cbc80391
L		 1192008-05-22 H.J. Lu <hongjiu.lu@intel.com>
120
121 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
122 * i386-tbl.h: Regenerated.
123
116615c5
L		 1242008-05-22 H.J. Lu <hongjiu.lu@intel.com>
125
126 PR gas/6517
127 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
128 into 32bit and 64bit. Remove Reg64|Qword and add
129 IgnoreSize|No_qSuf on 32bit version.
130 * i386-tbl.h: Regenerated.
131
d9479f2d
L		 1322008-05-21 H.J. Lu <hongjiu.lu@intel.com>
133
134 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
135 * i386-tbl.h: Regenerated.
136
3ce6fddb
NC		 1372008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
138
139 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
140
8944f3c2
AM		 1412008-05-14 Alan Modra <amodra@bigpond.net.au>
142
143 * Makefile.am: Run "make dep-am".
144 * Makefile.in: Regenerate.
145
f1f8f695
L		 1462008-05-02 H.J. Lu <hongjiu.lu@intel.com>
147
148 * i386-dis.c (MOVBE_Fixup): New.
149 (Mo): Likewise.
150 (PREFIX_0F3880): Likewise.
151 (PREFIX_0F3881): Likewise.
152 (PREFIX_0F38F0): Updated.
153 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
154 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
155 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
156
157 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
158 CPU_EPT_FLAGS.
159 (cpu_flags): Add CpuMovbe and CpuEPT.
160
161 * i386-opc.h (CpuMovbe): New.
162 (CpuEPT): Likewise.
163 (CpuLM): Updated.
164 (i386_cpu_flags): Add cpumovbe and cpuept.
165
166 * i386-opc.tbl: Add entries for movbe and EPT instructions.
167 * i386-init.h: Regenerated.
168 * i386-tbl.h: Likewise.
169
89aa3097
AN		 1702008-04-29 Adam Nemet <anemet@caviumnetworks.com>
171
172 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
173 the two drem and the two dremu macros.
174
39c5c168
AN		 1752008-04-28 Adam Nemet <anemet@caviumnetworks.com>
176
177 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
178 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
179 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
180 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
181
f04d18b7
DM		 1822008-04-25 David S. Miller <davem@davemloft.net>
183
184 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
185 instead of %sys_tick_cmpr, as suggested in architecture manuals.
186
6194aaab
L		 1872008-04-23 Paolo Bonzini <bonzini@gnu.org>
188
189 * aclocal.m4: Regenerate.
190 * configure: Regenerate.
191
1a6b486f
DM		 1922008-04-23 David S. Miller <davem@davemloft.net>
193
194 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
195 extended values.
196 (prefetch_table): Add missing values.
197
81f8a913
L		 1982008-04-22 H.J. Lu <hongjiu.lu@intel.com>
199
200 * i386-gen.c (opcode_modifiers): Add NoAVX.
201
202 * i386-opc.h (NoAVX): New.
203 (OldGcc): Updated.
204 (i386_opcode_modifier): Add noavx.
205
206 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
207 instructions which don't have AVX equivalent.
208 * i386-tbl.h: Regenerated.
209
dae39acc
L		 2102008-04-18 H.J. Lu <hongjiu.lu@intel.com>
211
212 * i386-dis.c (OP_VEX_FMA): New.
213 (OP_EX_VexImmW): Likewise.
214 (VexFMA): Likewise.
215 (Vex128FMA): Likewise.
216 (EXVexImmW): Likewise.
217 (get_vex_imm8): Likewise.
218 (OP_EX_VexReg): Likewise.
219 (vex_i4_done): Renamed to ...
220 (vex_w_done): This.
221 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
222 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
223 FMA instructions.
224 (print_insn): Updated.
225 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
226 (OP_REG_VexI4): Check invalid high registers.
227
ce886ab1
DR		 2282008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
229 Michael Meissner <michael.meissner@amd.com>
230
231 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
232 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 233
19a6653c
AM		 2342008-04-14 Edmar Wienskoski <edmar@freescale.com>
235
236 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
237 accept Power E500MC instructions.
238 (print_ppc_disassembler_options): Document -Me500mc.
239 * ppc-opc.c (DUIS, DUI, T): New.
240 (XRT, XRTRA): Likewise.
241 (E500MC): Likewise.
242 (powerpc_opcodes): Add new Power E500MC instructions.
243
112b7c50
AK		 2442008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
245
246 * s390-dis.c (init_disasm): Evaluate disassembler_options.
247 (print_s390_disassembler_options): New function.
248 * disassemble.c (disassembler_usage): Invoke
249 print_s390_disassembler_options.
250
7ff42648
AK		 2512008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
252
253 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
254 of local variables used for mnemonic parsing: prefix, suffix and
255 number.
256
45a5551e
AK		 2572008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
258
259 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
260 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
261 (s390_crb_extensions): New extensions table.
262 (insertExpandedMnemonic): Handle '$' tag.
263 * s390-opc.txt: Remove conditional jump variants which can now
264 be expanded automatically.
265 Replace '*' tag with '$' in the compare and branch instructions.
266
06c8514a
L		 2672008-04-07 H.J. Lu <hongjiu.lu@intel.com>
268
269 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
270 (PREFIX_VEX_3AXX): Likewis.
271
b122c285
L		 2722008-04-07 H.J. Lu <hongjiu.lu@intel.com>
273
274 * i386-opc.tbl: Remove 4 extra blank lines.
275
594ab6a3
L		 2762008-04-04 H.J. Lu <hongjiu.lu@intel.com>
277
278 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
279 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
280 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
281 * i386-opc.tbl: Likewise.
282
283 * i386-opc.h (CpuCLMUL): Renamed to ...
284 (CpuPCLMUL): This.
285 (CpuFMA): Updated.
286 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
287
288 * i386-init.h: Regenerated.
289
c0f3af97
L		 2902008-04-03 H.J. Lu <hongjiu.lu@intel.com>
291
292 * i386-dis.c (OP_E_register): New.
293 (OP_E_memory): Likewise.
294 (OP_VEX): Likewise.
295 (OP_EX_Vex): Likewise.
296 (OP_EX_VexW): Likewise.
297 (OP_XMM_Vex): Likewise.
298 (OP_XMM_VexW): Likewise.
299 (OP_REG_VexI4): Likewise.
300 (PCLMUL_Fixup): Likewise.
301 (VEXI4_Fixup): Likewise.
302 (VZERO_Fixup): Likewise.
303 (VCMP_Fixup): Likewise.
304 (VPERMIL2_Fixup): Likewise.
305 (rex_original): Likewise.
306 (rex_ignored): Likewise.
307 (Mxmm): Likewise.
308 (XMM): Likewise.
309 (EXxmm): Likewise.
310 (EXxmmq): Likewise.
311 (EXymmq): Likewise.
312 (Vex): Likewise.
313 (Vex128): Likewise.
314 (Vex256): Likewise.
315 (VexI4): Likewise.
316 (EXdVex): Likewise.
317 (EXqVex): Likewise.
318 (EXVexW): Likewise.
319 (EXdVexW): Likewise.
320 (EXqVexW): Likewise.
321 (XMVex): Likewise.
322 (XMVexW): Likewise.
323 (XMVexI4): Likewise.
324 (PCLMUL): Likewise.
325 (VZERO): Likewise.
326 (VCMP): Likewise.
327 (VPERMIL2): Likewise.
328 (xmm_mode): Likewise.
329 (xmmq_mode): Likewise.
330 (ymmq_mode): Likewise.
331 (vex_mode): Likewise.
332 (vex128_mode): Likewise.
333 (vex256_mode): Likewise.
334 (USE_VEX_C4_TABLE): Likewise.
335 (USE_VEX_C5_TABLE): Likewise.
336 (USE_VEX_LEN_TABLE): Likewise.
337 (VEX_C4_TABLE): Likewise.
338 (VEX_C5_TABLE): Likewise.
339 (VEX_LEN_TABLE): Likewise.
340 (REG_VEX_XX): Likewise.
341 (MOD_VEX_XXX): Likewise.
342 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
343 (PREFIX_0F3A44): Likewise.
344 (PREFIX_0F3ADF): Likewise.
345 (PREFIX_VEX_XXX): Likewise.
346 (VEX_OF): Likewise.
347 (VEX_OF38): Likewise.
348 (VEX_OF3A): Likewise.
349 (VEX_LEN_XXX): Likewise.
350 (vex): Likewise.
351 (need_vex): Likewise.
352 (need_vex_reg): Likewise.
353 (vex_i4_done): Likewise.
354 (vex_table): Likewise.
355 (vex_len_table): Likewise.
356 (OP_REG_VexI4): Likewise.
357 (vex_cmp_op): Likewise.
358 (pclmul_op): Likewise.
359 (vpermil2_op): Likewise.
360 (m_mode): Updated.
361 (es_reg): Likewise.
362 (PREFIX_0F38F0): Likewise.
363 (PREFIX_0F3A60): Likewise.
364 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
365 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
366 and PREFIX_VEX_XXX entries.
367 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
368 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
369 PREFIX_0F3ADF.
370 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
371 Add MOD_VEX_XXX entries.
372 (ckprefix): Initialize rex_original and rex_ignored. Store the
373 REX byte in rex_original.
374 (get_valid_dis386): Handle the implicit prefix in VEX prefix
375 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
376 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
377 calling get_valid_dis386. Use rex_original and rex_ignored when
378 printing out REX.
379 (putop): Handle "XY".
380 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
381 ymmq_mode.
382 (OP_E_extended): Updated to use OP_E_register and
383 OP_E_memory.
384 (OP_XMM): Handle VEX.
385 (OP_EX): Likewise.
386 (XMM_Fixup): Likewise.
387 (CMP_Fixup): Use ARRAY_SIZE.
388
389 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
390 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
391 (operand_type_init): Add OPERAND_TYPE_REGYMM and
392 OPERAND_TYPE_VEX_IMM4.
393 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
394 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
395 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
396 VexImmExt and SSE2AVX.
397 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
398
399 * i386-opc.h (CpuAVX): New.
400 (CpuAES): Likewise.
401 (CpuCLMUL): Likewise.
402 (CpuFMA): Likewise.
403 (Vex): Likewise.
404 (Vex256): Likewise.
405 (VexNDS): Likewise.
406 (VexNDD): Likewise.
407 (VexW0): Likewise.
408 (VexW1): Likewise.
409 (Vex0F): Likewise.
410 (Vex0F38): Likewise.
411 (Vex0F3A): Likewise.
412 (Vex3Sources): Likewise.
413 (VexImmExt): Likewise.
414 (SSE2AVX): Likewise.
415 (RegYMM): Likewise.
416 (Ymmword): Likewise.
417 (Vex_Imm4): Likewise.
418 (Implicit1stXmm0): Likewise.
419 (CpuXsave): Updated.
420 (CpuLM): Likewise.
421 (ByteOkIntel): Likewise.
422 (OldGcc): Likewise.
423 (Control): Likewise.
424 (Unspecified): Likewise.
425 (OTMax): Likewise.
426 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
427 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
428 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
429 vex3sources, veximmext and sse2avx.
430 (i386_operand_type): Add regymm, ymmword and vex_imm4.
431
432 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
433
434 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
435
436 * i386-init.h: Regenerated.
437 * i386-tbl.h: Likewise.
438
b21c9cb4
BS		 4392008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
440
441 From Robin Getz <robin.getz@analog.com>
442 * bfin-dis.c (bu32): Typedef.
443 (enum const_forms_t): Add c_uimm32 and c_huimm32.
444 (constant_formats[]): Add uimm32 and huimm16.
445 (fmtconst_val): New.
446 (uimm32): Define.
447 (huimm32): Define.
448 (imm16_val): Define.
449 (luimm16_val): Define.
450 (struct saved_state): Define.
451 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
452 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
453 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
454 (get_allreg): New.
455 (decode_LDIMMhalf_0): Print out the whole register value.
456
ee171c8f
BS		 457 From Jie Zhang <jie.zhang@analog.com>
458 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
459 multiply and multiply-accumulate to data register instruction.
460
086134ec
BS		 461 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
462 c_imm32, c_huimm32e): Define.
463 (constant_formats): Add flags for printing decimal, leading spaces, and
464 exact symbols.
465 (comment, parallel): Add global flags in all disassembly.
466 (fmtconst): Take advantage of new flags, and print default in hex.
467 (fmtconst_val): Likewise.
468 (decode_macfunc): Be consistant with spaces, tabs, comments,
469 capitalization in disassembly, fix minor coding style issues.
470 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
471 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
472 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
473 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
474 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
475 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
476 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
477 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
478 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
479 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
480 _print_insn_bfin, print_insn_bfin): Likewise.
481
58c85be7
RW		 4822008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
483
484 * aclocal.m4: Regenerate.
485 * configure: Likewise.
486 * Makefile.in: Likewise.
487
50e7d84b
AM		 4882008-03-13 Alan Modra <amodra@bigpond.net.au>
489
490 * Makefile.am: Run "make dep-am".
491 * Makefile.in: Regenerate.
492 * configure: Regenerate.
493
de866fcc
AM		 4942008-03-07 Alan Modra <amodra@bigpond.net.au>
495
496 * ppc-opc.c (powerpc_opcodes): Order and format.
497
28dbc079
L		 4982008-03-01 H.J. Lu <hongjiu.lu@intel.com>
499
500 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
501 * i386-tbl.h: Regenerated.
502
849830bd
L		 5032008-02-23 H.J. Lu <hongjiu.lu@intel.com>
504
505 * i386-opc.tbl: Disallow 16-bit near indirect branches for
506 x86-64.
507 * i386-tbl.h: Regenerated.
508
743ddb6b
JB		 5092008-02-21 Jan Beulich <jbeulich@novell.com>
510
511 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
512 and Fword for far indirect jmp. Allow Reg16 and Word for near
513 indirect jmp on x86-64. Disallow Fword for lcall.
514 * i386-tbl.h: Re-generate.
515
796d5313
NC		 5162008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
517
518 * cr16-opc.c (cr16_num_optab): Defined
519
65da13b5
L		 5202008-02-16 H.J. Lu <hongjiu.lu@intel.com>
521
522 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
523 * i386-init.h: Regenerated.
524
0e336180
NC		 5252008-02-14 Nick Clifton <nickc@redhat.com>
526
527 PR binutils/5524
528 * configure.in (SHARED_LIBADD): Select the correct host specific
529 file extension for shared libraries.
530 * configure: Regenerate.
531
b7240065
JB		 5322008-02-13 Jan Beulich <jbeulich@novell.com>
533
534 * i386-opc.h (RegFlat): New.
535 * i386-reg.tbl (flat): Add.
536 * i386-tbl.h: Re-generate.
537
34b772a6
JB		 5382008-02-13 Jan Beulich <jbeulich@novell.com>
539
540 * i386-dis.c (a_mode): New.
541 (cond_jump_mode): Adjust.
542 (Ma): Change to a_mode.
543 (intel_operand_size): Handle a_mode.
544 * i386-opc.tbl: Allow Dword and Qword for bound.
545 * i386-tbl.h: Re-generate.
546
a60de03c
JB		 5472008-02-13 Jan Beulich <jbeulich@novell.com>
548
549 * i386-gen.c (process_i386_registers): Process new fields.
550 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
551 unsigned char. Add dw2_regnum and Dw2Inval.
552 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
553 register names.
554 * i386-tbl.h: Re-generate.
555
f03fe4c1
L		 5562008-02-11 H.J. Lu <hongjiu.lu@intel.com>
557
4b6bc8eb 558 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 559 * i386-init.h: Updated.
560
475a2301
L		 5612008-02-11 H.J. Lu <hongjiu.lu@intel.com>
562
563 * i386-gen.c (cpu_flags): Add CpuXsave.
564
565 * i386-opc.h (CpuXsave): New.
4b6bc8eb 566 (CpuLM): Updated.
475a2301
L		 567 (i386_cpu_flags): Add cpuxsave.
568
569 * i386-dis.c (MOD_0FAE_REG_4): New.
570 (RM_0F01_REG_2): Likewise.
571 (MOD_0FAE_REG_5): Updated.
572 (RM_0F01_REG_3): Likewise.
573 (reg_table): Use MOD_0FAE_REG_4.
574 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
575 for xrstor.
576 (rm_table): Add RM_0F01_REG_2.
577
578 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
579 * i386-init.h: Regenerated.
580 * i386-tbl.h: Likewise.
581
595785c6 5822008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 583
595785c6
JB		 584 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
585 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
586 * i386-tbl.h: Re-generate.
587
bb8541b9
L		 5882008-02-04 H.J. Lu <hongjiu.lu@intel.com>
589
590 PR 5715
591 * configure: Regenerated.
592
57b592a3
AN		 5932008-02-04 Adam Nemet <anemet@caviumnetworks.com>
594
595 * mips-dis.c: Update copyright.
596 (mips_arch_choices): Add Octeon.
597 * mips-opc.c: Update copyright.
598 (IOCT): New macro.
599 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
600
930bb4cf
AM		 6012008-01-29 Alan Modra <amodra@bigpond.net.au>
602
603 * ppc-opc.c: Support optional L form mtmsr.
604
82c18208
L		 6052008-01-24 H.J. Lu <hongjiu.lu@intel.com>
606
607 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
608
599121aa
L		 6092008-01-23 H.J. Lu <hongjiu.lu@intel.com>
610
611 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
612 * i386-init.h: Regenerated.
613
80098f51
TG		 6142008-01-23 Tristan Gingold <gingold@adacore.com>
615
616 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
617 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
618
115c7c25
L		 6192008-01-22 H.J. Lu <hongjiu.lu@intel.com>
620
621 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
622 (cpu_flags): Likewise.
623
624 * i386-opc.h (CpuMMX2): Removed.
625 (CpuSSE): Updated.
626
627 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
628 * i386-init.h: Regenerated.
629 * i386-tbl.h: Likewise.
630
6305a203
L		 6312008-01-22 H.J. Lu <hongjiu.lu@intel.com>
632
633 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
634 CPU_SMX_FLAGS.
635 * i386-init.h: Regenerated.
636
fd07a1c8
L		 6372008-01-15 H.J. Lu <hongjiu.lu@intel.com>
638
639 * i386-opc.tbl: Use Qword on movddup.
640 * i386-tbl.h: Regenerated.
641
321fd21e
L		 6422008-01-15 H.J. Lu <hongjiu.lu@intel.com>
643
644 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
645 * i386-tbl.h: Regenerated.
646
4ee52178
L		 6472008-01-15 H.J. Lu <hongjiu.lu@intel.com>
648
649 * i386-dis.c (Mx): New.
650 (PREFIX_0FC3): Likewise.
651 (PREFIX_0FC7_REG_6): Updated.
652 (dis386_twobyte): Use PREFIX_0FC3.
653 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
654 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
655 movntss.
656
5c07affc
L		 6572008-01-14 H.J. Lu <hongjiu.lu@intel.com>
658
659 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
660 (operand_types): Add Mem.
661
662 * i386-opc.h (IntelSyntax): New.
663 * i386-opc.h (Mem): New.
664 (Byte): Updated.
665 (Opcode_Modifier_Max): Updated.
666 (i386_opcode_modifier): Add intelsyntax.
667 (i386_operand_type): Add mem.
668
669 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
670 instructions.
671
672 * i386-reg.tbl: Add size for accumulator.
673
674 * i386-init.h: Regenerated.
675 * i386-tbl.h: Likewise.
676
0d6a2f58
L		 6772008-01-13 H.J. Lu <hongjiu.lu@intel.com>
678
679 * i386-opc.h (Byte): Fix a typo.
680
7d5e4556
L		 6812008-01-12 H.J. Lu <hongjiu.lu@intel.com>
682
683 PR gas/5534
684 * i386-gen.c (operand_type_init): Add Dword to
685 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
686 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
687 Qword and Xmmword.
688 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
689 Xmmword, Unspecified and Anysize.
690 (set_bitfield): Make Mmword an alias of Qword. Make Oword
691 an alias of Xmmword.
692
693 * i386-opc.h (CheckSize): Removed.
694 (Byte): Updated.
695 (Word): Likewise.
696 (Dword): Likewise.
697 (Qword): Likewise.
698 (Xmmword): Likewise.
699 (FWait): Updated.
700 (OTMax): Likewise.
701 (i386_opcode_modifier): Remove checksize, byte, word, dword,
702 qword and xmmword.
703 (Fword): New.
704 (TBYTE): Likewise.
705 (Unspecified): Likewise.
706 (Anysize): Likewise.
707 (i386_operand_type): Add byte, word, dword, fword, qword,
708 tbyte xmmword, unspecified and anysize.
709
710 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
711 Tbyte, Xmmword, Unspecified and Anysize.
712
713 * i386-reg.tbl: Add size for accumulator.
714
715 * i386-init.h: Regenerated.
716 * i386-tbl.h: Likewise.
717
b5b1fc4f
L		 7182008-01-10 H.J. Lu <hongjiu.lu@intel.com>
719
720 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
721 (REG_0F18): Updated.
722 (reg_table): Updated.
723 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
724 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
725
50e8458f
L		 7262008-01-08 H.J. Lu <hongjiu.lu@intel.com>
727
728 * i386-gen.c (set_bitfield): Use fail () on error.
729
3d4d5afa
L		 7302008-01-08 H.J. Lu <hongjiu.lu@intel.com>
731
732 * i386-gen.c (lineno): New.
733 (filename): Likewise.
734 (set_bitfield): Report filename and line numer on error.
735 (process_i386_opcodes): Set filename and update lineno.
736 (process_i386_registers): Likewise.
737
e1d4d893
L		 7382008-01-05 H.J. Lu <hongjiu.lu@intel.com>
739
740 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
741 ATTSyntax.
742
743 * i386-opc.h (IntelMnemonic): Renamed to ..
744 (ATTSyntax): This
745 (Opcode_Modifier_Max): Updated.
746 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
747 and intelsyntax.
748
8944f3c2 749 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 750 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
751 * i386-tbl.h: Regenerated.
752
6f143e4d
L		 7532008-01-04 H.J. Lu <hongjiu.lu@intel.com>
754
755 * i386-gen.c: Update copyright to 2008.
756 * i386-opc.h: Likewise.
757 * i386-opc.tbl: Likewise.
758
759 * i386-init.h: Regenerated.
760 * i386-tbl.h: Likewise.
761
c6add537
L		 7622008-01-04 H.J. Lu <hongjiu.lu@intel.com>
763
764 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
765 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
766 * i386-tbl.h: Regenerated.
767
3629bb00
L		 7682008-01-03 H.J. Lu <hongjiu.lu@intel.com>
769
770 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
771 CpuSSE4_2_Or_ABM.
772 (cpu_flags): Likewise.
773
774 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
775 (CpuSSE4_2_Or_ABM): Likewise.
776 (CpuLM): Updated.
777 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
778
779 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
780 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
781 and CpuPadLock, respectively.
782 * i386-init.h: Regenerated.
783 * i386-tbl.h: Likewise.
784
24995bd6
L		 7852008-01-03 H.J. Lu <hongjiu.lu@intel.com>
786
787 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
788
789 * i386-opc.h (No_xSuf): Removed.
790 (CheckSize): Updated.
791
792 * i386-tbl.h: Regenerated.
793
e0329a22
L		 7942008-01-02 H.J. Lu <hongjiu.lu@intel.com>
795
796 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
797 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
798 CPU_SSE5_FLAGS.
799 (cpu_flags): Add CpuSSE4_2_Or_ABM.
800
801 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
802 (CpuLM): Updated.
803 (i386_cpu_flags): Add cpusse4_2_or_abm.
804
805 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
806 CpuABM|CpuSSE4_2 on popcnt.
807 * i386-init.h: Regenerated.
808 * i386-tbl.h: Likewise.
809
f2a9c676
L		 8102008-01-02 H.J. Lu <hongjiu.lu@intel.com>
811
812 * i386-opc.h: Update comments.
813
d978b5be
L		 8142008-01-02 H.J. Lu <hongjiu.lu@intel.com>
815
816 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
817 * i386-opc.h: Likewise.
818 * i386-opc.tbl: Likewise.
819
582d5edd
L		 8202008-01-02 H.J. Lu <hongjiu.lu@intel.com>
821
822 PR gas/5534
823 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
824 Byte, Word, Dword, QWord and Xmmword.
825
826 * i386-opc.h (No_xSuf): New.
827 (CheckSize): Likewise.
828 (Byte): Likewise.
829 (Word): Likewise.
830 (Dword): Likewise.
831 (QWord): Likewise.
832 (Xmmword): Likewise.
833 (FWait): Updated.
834 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
835 Dword, QWord and Xmmword.
836
837 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
838 used.
839 * i386-tbl.h: Regenerated.
840
3fe15143
MK		 8412008-01-02 Mark Kettenis <kettenis@gnu.org>
842
843 * m88k-dis.c (instructions): Fix fcvt.* instructions.
844 From Miod Vallat.
845
6c7ac64e 846For older changes see ChangeLog-2007
252b5132
RH		 847\f
848Local Variables:
2f6d2f85
NC		 849mode: change-log
850left-margin: 8
851fill-column: 74
252b5132
RH		 852version-control: never
853End:
GDB Binutils - Deliverables
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