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* elflink.c (elf_link_add_object_symbols): Don't ignore returned
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1927a18f
L		 12008-09-29 H.J. Lu <hongjiu.lu@intel.com>
2
3 * aclocal.m4: Regenerated.
4 * configure: Likewise.
5 * Makefile.in: Likewise.
6
afac680a
NC		 72008-09-29 Nick Clifton <nickc@redhat.com>
8
9 * po/vi.po: Updated Vietnamese translation.
10 * po/fr.po: Updated French translation.
11
b40d5eb9
AK		 122008-09-26 Florian Krohm <fkrohm@us.ibm.com>
13
14 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
15 (cfxr, cfdr, cfer, clclu): Add esa flag.
16 (sqd): Instruction added.
17 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
18 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
19
d0411736
AM		 202008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
21
22 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
23 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
24
3e126784
L		 252008-09-11 H.J. Lu <hongjiu.lu@intel.com>
26
27 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
28 * i386-tbl.h: Regenerated.
29
ddab3d59
JB		 302008-08-28 Jan Beulich <jbeulich@novell.com>
31
32 * i386-dis.c (dis386): Adjust far return mnemonics.
33 * i386-opc.tbl: Add retf.
34 * i386-tbl.h: Re-generate.
35
b19d5385
JB		 362008-08-28 Jan Beulich <jbeulich@novell.com>
37
38 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
39
1ca35711
L		 402008-08-28 H.J. Lu <hongjiu.lu@intel.com>
41
42 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
43 * ia64-gen.c (lookup_specifier): Likewise.
44
45 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
46 * ia64-raw.tbl: Likewise.
47 * ia64-waw.tbl: Likewise.
48 * ia64-asmtab.c: Regenerated.
49
515c56e7
L		 502008-08-27 H.J. Lu <hongjiu.lu@intel.com>
51
52 * i386-opc.tbl: Correct fidivr operand size.
53
54 * i386-tbl.h: Regenerated.
55
da594c4a
AM		 562008-08-24 Alan Modra <amodra@bigpond.net.au>
57
58 * configure.in: Update a number of obsolete autoconf macros.
59 * aclocal.m4: Regenerate.
60
a5ff0eb2
L		 612008-08-20 H.J. Lu <hongjiu.lu@intel.com>
62
63 AVX Programming Reference (August, 2008)
64 * i386-dis.c (PREFIX_VEX_38DB): New.
65 (PREFIX_VEX_38DC): Likewise.
66 (PREFIX_VEX_38DD): Likewise.
67 (PREFIX_VEX_38DE): Likewise.
68 (PREFIX_VEX_38DF): Likewise.
69 (PREFIX_VEX_3ADF): Likewise.
70 (VEX_LEN_38DB_P_2): Likewise.
71 (VEX_LEN_38DC_P_2): Likewise.
72 (VEX_LEN_38DD_P_2): Likewise.
73 (VEX_LEN_38DE_P_2): Likewise.
74 (VEX_LEN_38DF_P_2): Likewise.
75 (VEX_LEN_3ADF_P_2): Likewise.
76 (PREFIX_VEX_3A04): Updated.
77 (VEX_LEN_3A06_P_2): Likewise.
78 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
79 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
80 (x86_64_table): Likewise.
81 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
82 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
83 VEX_LEN_3ADF_P_2.
84
85 * i386-opc.tbl: Add AES + AVX instructions.
86 * i386-init.h: Regenerated.
87 * i386-tbl.h: Likewise.
88
7dc6076f
AK		 892008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
90
91 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
92 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
93
7357c5b6
AM		 942008-08-15 Alan Modra <amodra@bigpond.net.au>
95
96 PR 6526
97 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
98 * Makefile.in: Regenerate.
99 * aclocal.m4: Regenerate.
100 * config.in: Regenerate.
101 * configure: Regenerate.
102
899d85be
AM		 1032008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
104
105 PR 6825
106 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
107
dfb07592
L		 1082008-08-12 H.J. Lu <hongjiu.lu@intel.com>
109
110 * i386-opc.tbl: Add syscall and sysret for Cpu64.
111
112 * i386-tbl.h: Regenerated.
113
323ee3f4
AM		 1142008-08-04 Alan Modra <amodra@bigpond.net.au>
115
116 * Makefile.am (POTFILES.in): Set LC_ALL=C.
117 * Makefile.in: Regenerate.
118 * po/POTFILES.in: Regenerate.
119
9b4e5766
PB		 1202008-08-01 Peter Bergner <bergner@vnet.ibm.com>
121
122 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
123 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
124 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
125 * ppc-opc.c (insert_xt6): New static function.
126 (extract_xt6): Likewise.
127 (insert_xa6): Likewise.
128 (extract_xa6: Likewise.
129 (insert_xb6): Likewise.
130 (extract_xb6): Likewise.
131 (insert_xb6s): Likewise.
132 (extract_xb6s): Likewise.
133 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
134 XX3DM_MASK, PPCVSX): New.
135 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
136 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
137
20fd6e2e
PA		 1382008-08-01 Pedro Alves <pedro@codesourcery.com>
139
140 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
141 * Makefile.in: Regenerate.
142
a656ed5b
L		 1432008-08-01 H.J. Lu <hongjiu.lu@intel.com>
144
145 * i386-reg.tbl: Use Dw2Inval on AVX registers.
146 * i386-tbl.h: Regenerated.
147
081ba1b3
AM		 1482008-07-30 Michael J. Eager <eager@eagercon.com>
149
150 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
151 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
152 (insert_sprg, PPC405): Use PPC_OPCODE_405.
153 (powerpc_opcodes): Add Xilinx APU related opcodes.
154
0af1713e
AM		 1552008-07-30 Alan Modra <amodra@bigpond.net.au>
156
157 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
158
30c09090
RS		 1592008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
160
161 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
162
c27e721e
AN		 1632008-07-07 Adam Nemet <anemet@caviumnetworks.com>
164
165 * mips-opc.c (CP): New macro.
166 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
167 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
168 dmtc2 Octeon instructions.
169
bd2e2557
SS		 1702008-07-07 Stan Shebs <stan@codesourcery.com>
171
172 * dis-init.c (init_disassemble_info): Init endian_code field.
173 * arm-dis.c (print_insn): Disassemble code according to
174 setting of endian_code.
175 (print_insn_big_arm): Detect when BE8 extension flag has been set.
176
6ba2a415
RS		 1772008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
178
179 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
180 for ELF symbols.
181
c8187e15
PB		 1822008-06-25 Peter Bergner <bergner@vnet.ibm.com>
183
184 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
185 (print_ppc_disassembler_options): Likewise.
186 * ppc-opc.c (PPC464): Define.
187 (powerpc_opcodes): Add mfdcrux and mtdcrux.
188
7a283e07
RW		 1892008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
190
191 * configure: Regenerate.
192
fa452fa6
PB		 1932008-06-13 Peter Bergner <bergner@vnet.ibm.com>
194
195 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
196 ppc_cpu_t typedef.
197 (struct dis_private): New.
198 (POWERPC_DIALECT): New define.
199 (powerpc_dialect): Renamed to...
200 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
201 struct dis_private.
202 (print_insn_big_powerpc): Update for using structure in
203 info->private_data.
204 (print_insn_little_powerpc): Likewise.
205 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
206 (skip_optional_operands): Likewise.
207 (print_insn_powerpc): Likewise. Remove initialization of dialect.
208 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
209 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
210 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
211 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
212 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
213 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
214 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
215 param to be of type ppc_cpu_t. Update prototype.
216
bb35fb24
NC		 2172008-06-12 Adam Nemet <anemet@caviumnetworks.com>
218
219 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
220 +s, +S.
221 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
222 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
223 syncw, syncws, vm3mulu, vm0 and vmulu.
224
dd3cbb7e
NC		 225 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
226 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
227 seqi, sne and snei.
228
a5dabbb0
L		 2292008-05-30 H.J. Lu <hongjiu.lu@intel.com>
230
231 * i386-opc.tbl: Add vmovd with 64bit operand.
232 * i386-tbl.h: Regenerated.
233
725a9891
MS		 2342008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
235
236 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
237
cbc80391
L		 2382008-05-22 H.J. Lu <hongjiu.lu@intel.com>
239
240 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
241 * i386-tbl.h: Regenerated.
242
116615c5
L		 2432008-05-22 H.J. Lu <hongjiu.lu@intel.com>
244
245 PR gas/6517
246 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
247 into 32bit and 64bit. Remove Reg64|Qword and add
248 IgnoreSize|No_qSuf on 32bit version.
249 * i386-tbl.h: Regenerated.
250
d9479f2d
L		 2512008-05-21 H.J. Lu <hongjiu.lu@intel.com>
252
253 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
254 * i386-tbl.h: Regenerated.
255
3ce6fddb
NC		 2562008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
257
258 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
259
8944f3c2
AM		 2602008-05-14 Alan Modra <amodra@bigpond.net.au>
261
262 * Makefile.am: Run "make dep-am".
263 * Makefile.in: Regenerate.
264
f1f8f695
L		 2652008-05-02 H.J. Lu <hongjiu.lu@intel.com>
266
267 * i386-dis.c (MOVBE_Fixup): New.
268 (Mo): Likewise.
269 (PREFIX_0F3880): Likewise.
270 (PREFIX_0F3881): Likewise.
271 (PREFIX_0F38F0): Updated.
272 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
273 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
274 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
275
276 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
277 CPU_EPT_FLAGS.
278 (cpu_flags): Add CpuMovbe and CpuEPT.
279
280 * i386-opc.h (CpuMovbe): New.
281 (CpuEPT): Likewise.
282 (CpuLM): Updated.
283 (i386_cpu_flags): Add cpumovbe and cpuept.
284
285 * i386-opc.tbl: Add entries for movbe and EPT instructions.
286 * i386-init.h: Regenerated.
287 * i386-tbl.h: Likewise.
288
89aa3097
AN		 2892008-04-29 Adam Nemet <anemet@caviumnetworks.com>
290
291 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
292 the two drem and the two dremu macros.
293
39c5c168
AN		 2942008-04-28 Adam Nemet <anemet@caviumnetworks.com>
295
296 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
297 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
298 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
299 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
300
f04d18b7
DM		 3012008-04-25 David S. Miller <davem@davemloft.net>
302
303 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
304 instead of %sys_tick_cmpr, as suggested in architecture manuals.
305
6194aaab
L		 3062008-04-23 Paolo Bonzini <bonzini@gnu.org>
307
308 * aclocal.m4: Regenerate.
309 * configure: Regenerate.
310
1a6b486f
DM		 3112008-04-23 David S. Miller <davem@davemloft.net>
312
313 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
314 extended values.
315 (prefetch_table): Add missing values.
316
81f8a913
L		 3172008-04-22 H.J. Lu <hongjiu.lu@intel.com>
318
319 * i386-gen.c (opcode_modifiers): Add NoAVX.
320
321 * i386-opc.h (NoAVX): New.
322 (OldGcc): Updated.
323 (i386_opcode_modifier): Add noavx.
324
325 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
326 instructions which don't have AVX equivalent.
327 * i386-tbl.h: Regenerated.
328
dae39acc
L		 3292008-04-18 H.J. Lu <hongjiu.lu@intel.com>
330
331 * i386-dis.c (OP_VEX_FMA): New.
332 (OP_EX_VexImmW): Likewise.
333 (VexFMA): Likewise.
334 (Vex128FMA): Likewise.
335 (EXVexImmW): Likewise.
336 (get_vex_imm8): Likewise.
337 (OP_EX_VexReg): Likewise.
338 (vex_i4_done): Renamed to ...
339 (vex_w_done): This.
340 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
341 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
342 FMA instructions.
343 (print_insn): Updated.
344 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
345 (OP_REG_VexI4): Check invalid high registers.
346
ce886ab1
DR		 3472008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
348 Michael Meissner <michael.meissner@amd.com>
349
350 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
351 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 352
19a6653c
AM		 3532008-04-14 Edmar Wienskoski <edmar@freescale.com>
354
355 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
356 accept Power E500MC instructions.
357 (print_ppc_disassembler_options): Document -Me500mc.
358 * ppc-opc.c (DUIS, DUI, T): New.
359 (XRT, XRTRA): Likewise.
360 (E500MC): Likewise.
361 (powerpc_opcodes): Add new Power E500MC instructions.
362
112b7c50
AK		 3632008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
364
365 * s390-dis.c (init_disasm): Evaluate disassembler_options.
366 (print_s390_disassembler_options): New function.
367 * disassemble.c (disassembler_usage): Invoke
368 print_s390_disassembler_options.
369
7ff42648
AK		 3702008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
371
372 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
373 of local variables used for mnemonic parsing: prefix, suffix and
374 number.
375
45a5551e
AK		 3762008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
377
378 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
379 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
380 (s390_crb_extensions): New extensions table.
381 (insertExpandedMnemonic): Handle '$' tag.
382 * s390-opc.txt: Remove conditional jump variants which can now
383 be expanded automatically.
384 Replace '*' tag with '$' in the compare and branch instructions.
385
06c8514a
L		 3862008-04-07 H.J. Lu <hongjiu.lu@intel.com>
387
388 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
389 (PREFIX_VEX_3AXX): Likewis.
390
b122c285
L		 3912008-04-07 H.J. Lu <hongjiu.lu@intel.com>
392
393 * i386-opc.tbl: Remove 4 extra blank lines.
394
594ab6a3
L		 3952008-04-04 H.J. Lu <hongjiu.lu@intel.com>
396
397 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
398 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
399 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
400 * i386-opc.tbl: Likewise.
401
402 * i386-opc.h (CpuCLMUL): Renamed to ...
403 (CpuPCLMUL): This.
404 (CpuFMA): Updated.
405 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
406
407 * i386-init.h: Regenerated.
408
c0f3af97
L		 4092008-04-03 H.J. Lu <hongjiu.lu@intel.com>
410
411 * i386-dis.c (OP_E_register): New.
412 (OP_E_memory): Likewise.
413 (OP_VEX): Likewise.
414 (OP_EX_Vex): Likewise.
415 (OP_EX_VexW): Likewise.
416 (OP_XMM_Vex): Likewise.
417 (OP_XMM_VexW): Likewise.
418 (OP_REG_VexI4): Likewise.
419 (PCLMUL_Fixup): Likewise.
420 (VEXI4_Fixup): Likewise.
421 (VZERO_Fixup): Likewise.
422 (VCMP_Fixup): Likewise.
423 (VPERMIL2_Fixup): Likewise.
424 (rex_original): Likewise.
425 (rex_ignored): Likewise.
426 (Mxmm): Likewise.
427 (XMM): Likewise.
428 (EXxmm): Likewise.
429 (EXxmmq): Likewise.
430 (EXymmq): Likewise.
431 (Vex): Likewise.
432 (Vex128): Likewise.
433 (Vex256): Likewise.
434 (VexI4): Likewise.
435 (EXdVex): Likewise.
436 (EXqVex): Likewise.
437 (EXVexW): Likewise.
438 (EXdVexW): Likewise.
439 (EXqVexW): Likewise.
440 (XMVex): Likewise.
441 (XMVexW): Likewise.
442 (XMVexI4): Likewise.
443 (PCLMUL): Likewise.
444 (VZERO): Likewise.
445 (VCMP): Likewise.
446 (VPERMIL2): Likewise.
447 (xmm_mode): Likewise.
448 (xmmq_mode): Likewise.
449 (ymmq_mode): Likewise.
450 (vex_mode): Likewise.
451 (vex128_mode): Likewise.
452 (vex256_mode): Likewise.
453 (USE_VEX_C4_TABLE): Likewise.
454 (USE_VEX_C5_TABLE): Likewise.
455 (USE_VEX_LEN_TABLE): Likewise.
456 (VEX_C4_TABLE): Likewise.
457 (VEX_C5_TABLE): Likewise.
458 (VEX_LEN_TABLE): Likewise.
459 (REG_VEX_XX): Likewise.
460 (MOD_VEX_XXX): Likewise.
461 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
462 (PREFIX_0F3A44): Likewise.
463 (PREFIX_0F3ADF): Likewise.
464 (PREFIX_VEX_XXX): Likewise.
465 (VEX_OF): Likewise.
466 (VEX_OF38): Likewise.
467 (VEX_OF3A): Likewise.
468 (VEX_LEN_XXX): Likewise.
469 (vex): Likewise.
470 (need_vex): Likewise.
471 (need_vex_reg): Likewise.
472 (vex_i4_done): Likewise.
473 (vex_table): Likewise.
474 (vex_len_table): Likewise.
475 (OP_REG_VexI4): Likewise.
476 (vex_cmp_op): Likewise.
477 (pclmul_op): Likewise.
478 (vpermil2_op): Likewise.
479 (m_mode): Updated.
480 (es_reg): Likewise.
481 (PREFIX_0F38F0): Likewise.
482 (PREFIX_0F3A60): Likewise.
483 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
484 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
485 and PREFIX_VEX_XXX entries.
486 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
487 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
488 PREFIX_0F3ADF.
489 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
490 Add MOD_VEX_XXX entries.
491 (ckprefix): Initialize rex_original and rex_ignored. Store the
492 REX byte in rex_original.
493 (get_valid_dis386): Handle the implicit prefix in VEX prefix
494 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
495 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
496 calling get_valid_dis386. Use rex_original and rex_ignored when
497 printing out REX.
498 (putop): Handle "XY".
499 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
500 ymmq_mode.
501 (OP_E_extended): Updated to use OP_E_register and
502 OP_E_memory.
503 (OP_XMM): Handle VEX.
504 (OP_EX): Likewise.
505 (XMM_Fixup): Likewise.
506 (CMP_Fixup): Use ARRAY_SIZE.
507
508 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
509 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
510 (operand_type_init): Add OPERAND_TYPE_REGYMM and
511 OPERAND_TYPE_VEX_IMM4.
512 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
513 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
514 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
515 VexImmExt and SSE2AVX.
516 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
517
518 * i386-opc.h (CpuAVX): New.
519 (CpuAES): Likewise.
520 (CpuCLMUL): Likewise.
521 (CpuFMA): Likewise.
522 (Vex): Likewise.
523 (Vex256): Likewise.
524 (VexNDS): Likewise.
525 (VexNDD): Likewise.
526 (VexW0): Likewise.
527 (VexW1): Likewise.
528 (Vex0F): Likewise.
529 (Vex0F38): Likewise.
530 (Vex0F3A): Likewise.
531 (Vex3Sources): Likewise.
532 (VexImmExt): Likewise.
533 (SSE2AVX): Likewise.
534 (RegYMM): Likewise.
535 (Ymmword): Likewise.
536 (Vex_Imm4): Likewise.
537 (Implicit1stXmm0): Likewise.
538 (CpuXsave): Updated.
539 (CpuLM): Likewise.
540 (ByteOkIntel): Likewise.
541 (OldGcc): Likewise.
542 (Control): Likewise.
543 (Unspecified): Likewise.
544 (OTMax): Likewise.
545 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
546 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
547 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
548 vex3sources, veximmext and sse2avx.
549 (i386_operand_type): Add regymm, ymmword and vex_imm4.
550
551 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
552
553 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
554
555 * i386-init.h: Regenerated.
556 * i386-tbl.h: Likewise.
557
b21c9cb4
BS		 5582008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
559
560 From Robin Getz <robin.getz@analog.com>
561 * bfin-dis.c (bu32): Typedef.
562 (enum const_forms_t): Add c_uimm32 and c_huimm32.
563 (constant_formats[]): Add uimm32 and huimm16.
564 (fmtconst_val): New.
565 (uimm32): Define.
566 (huimm32): Define.
567 (imm16_val): Define.
568 (luimm16_val): Define.
569 (struct saved_state): Define.
570 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
571 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
572 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
573 (get_allreg): New.
574 (decode_LDIMMhalf_0): Print out the whole register value.
575
ee171c8f
BS		 576 From Jie Zhang <jie.zhang@analog.com>
577 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
578 multiply and multiply-accumulate to data register instruction.
579
086134ec
BS		 580 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
581 c_imm32, c_huimm32e): Define.
582 (constant_formats): Add flags for printing decimal, leading spaces, and
583 exact symbols.
584 (comment, parallel): Add global flags in all disassembly.
585 (fmtconst): Take advantage of new flags, and print default in hex.
586 (fmtconst_val): Likewise.
587 (decode_macfunc): Be consistant with spaces, tabs, comments,
588 capitalization in disassembly, fix minor coding style issues.
589 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
590 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
591 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
592 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
593 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
594 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
595 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
596 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
597 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
598 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
599 _print_insn_bfin, print_insn_bfin): Likewise.
600
58c85be7
RW		 6012008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
602
603 * aclocal.m4: Regenerate.
604 * configure: Likewise.
605 * Makefile.in: Likewise.
606
50e7d84b
AM		 6072008-03-13 Alan Modra <amodra@bigpond.net.au>
608
609 * Makefile.am: Run "make dep-am".
610 * Makefile.in: Regenerate.
611 * configure: Regenerate.
612
de866fcc
AM		 6132008-03-07 Alan Modra <amodra@bigpond.net.au>
614
615 * ppc-opc.c (powerpc_opcodes): Order and format.
616
28dbc079
L		 6172008-03-01 H.J. Lu <hongjiu.lu@intel.com>
618
619 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
620 * i386-tbl.h: Regenerated.
621
849830bd
L		 6222008-02-23 H.J. Lu <hongjiu.lu@intel.com>
623
624 * i386-opc.tbl: Disallow 16-bit near indirect branches for
625 x86-64.
626 * i386-tbl.h: Regenerated.
627
743ddb6b
JB		 6282008-02-21 Jan Beulich <jbeulich@novell.com>
629
630 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
631 and Fword for far indirect jmp. Allow Reg16 and Word for near
632 indirect jmp on x86-64. Disallow Fword for lcall.
633 * i386-tbl.h: Re-generate.
634
796d5313
NC		 6352008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
636
637 * cr16-opc.c (cr16_num_optab): Defined
638
65da13b5
L		 6392008-02-16 H.J. Lu <hongjiu.lu@intel.com>
640
641 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
642 * i386-init.h: Regenerated.
643
0e336180
NC		 6442008-02-14 Nick Clifton <nickc@redhat.com>
645
646 PR binutils/5524
647 * configure.in (SHARED_LIBADD): Select the correct host specific
648 file extension for shared libraries.
649 * configure: Regenerate.
650
b7240065
JB		 6512008-02-13 Jan Beulich <jbeulich@novell.com>
652
653 * i386-opc.h (RegFlat): New.
654 * i386-reg.tbl (flat): Add.
655 * i386-tbl.h: Re-generate.
656
34b772a6
JB		 6572008-02-13 Jan Beulich <jbeulich@novell.com>
658
659 * i386-dis.c (a_mode): New.
660 (cond_jump_mode): Adjust.
661 (Ma): Change to a_mode.
662 (intel_operand_size): Handle a_mode.
663 * i386-opc.tbl: Allow Dword and Qword for bound.
664 * i386-tbl.h: Re-generate.
665
a60de03c
JB		 6662008-02-13 Jan Beulich <jbeulich@novell.com>
667
668 * i386-gen.c (process_i386_registers): Process new fields.
669 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
670 unsigned char. Add dw2_regnum and Dw2Inval.
671 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
672 register names.
673 * i386-tbl.h: Re-generate.
674
f03fe4c1
L		 6752008-02-11 H.J. Lu <hongjiu.lu@intel.com>
676
4b6bc8eb 677 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 678 * i386-init.h: Updated.
679
475a2301
L		 6802008-02-11 H.J. Lu <hongjiu.lu@intel.com>
681
682 * i386-gen.c (cpu_flags): Add CpuXsave.
683
684 * i386-opc.h (CpuXsave): New.
4b6bc8eb 685 (CpuLM): Updated.
475a2301
L		 686 (i386_cpu_flags): Add cpuxsave.
687
688 * i386-dis.c (MOD_0FAE_REG_4): New.
689 (RM_0F01_REG_2): Likewise.
690 (MOD_0FAE_REG_5): Updated.
691 (RM_0F01_REG_3): Likewise.
692 (reg_table): Use MOD_0FAE_REG_4.
693 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
694 for xrstor.
695 (rm_table): Add RM_0F01_REG_2.
696
697 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
698 * i386-init.h: Regenerated.
699 * i386-tbl.h: Likewise.
700
595785c6 7012008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 702
595785c6
JB		 703 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
704 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
705 * i386-tbl.h: Re-generate.
706
bb8541b9
L		 7072008-02-04 H.J. Lu <hongjiu.lu@intel.com>
708
709 PR 5715
710 * configure: Regenerated.
711
57b592a3
AN		 7122008-02-04 Adam Nemet <anemet@caviumnetworks.com>
713
714 * mips-dis.c: Update copyright.
715 (mips_arch_choices): Add Octeon.
716 * mips-opc.c: Update copyright.
717 (IOCT): New macro.
718 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
719
930bb4cf
AM		 7202008-01-29 Alan Modra <amodra@bigpond.net.au>
721
722 * ppc-opc.c: Support optional L form mtmsr.
723
82c18208
L		 7242008-01-24 H.J. Lu <hongjiu.lu@intel.com>
725
726 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
727
599121aa
L		 7282008-01-23 H.J. Lu <hongjiu.lu@intel.com>
729
730 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
731 * i386-init.h: Regenerated.
732
80098f51
TG		 7332008-01-23 Tristan Gingold <gingold@adacore.com>
734
735 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
736 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
737
115c7c25
L		 7382008-01-22 H.J. Lu <hongjiu.lu@intel.com>
739
740 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
741 (cpu_flags): Likewise.
742
743 * i386-opc.h (CpuMMX2): Removed.
744 (CpuSSE): Updated.
745
746 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
747 * i386-init.h: Regenerated.
748 * i386-tbl.h: Likewise.
749
6305a203
L		 7502008-01-22 H.J. Lu <hongjiu.lu@intel.com>
751
752 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
753 CPU_SMX_FLAGS.
754 * i386-init.h: Regenerated.
755
fd07a1c8
L		 7562008-01-15 H.J. Lu <hongjiu.lu@intel.com>
757
758 * i386-opc.tbl: Use Qword on movddup.
759 * i386-tbl.h: Regenerated.
760
321fd21e
L		 7612008-01-15 H.J. Lu <hongjiu.lu@intel.com>
762
763 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
764 * i386-tbl.h: Regenerated.
765
4ee52178
L		 7662008-01-15 H.J. Lu <hongjiu.lu@intel.com>
767
768 * i386-dis.c (Mx): New.
769 (PREFIX_0FC3): Likewise.
770 (PREFIX_0FC7_REG_6): Updated.
771 (dis386_twobyte): Use PREFIX_0FC3.
772 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
773 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
774 movntss.
775
5c07affc
L		 7762008-01-14 H.J. Lu <hongjiu.lu@intel.com>
777
778 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
779 (operand_types): Add Mem.
780
781 * i386-opc.h (IntelSyntax): New.
782 * i386-opc.h (Mem): New.
783 (Byte): Updated.
784 (Opcode_Modifier_Max): Updated.
785 (i386_opcode_modifier): Add intelsyntax.
786 (i386_operand_type): Add mem.
787
788 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
789 instructions.
790
791 * i386-reg.tbl: Add size for accumulator.
792
793 * i386-init.h: Regenerated.
794 * i386-tbl.h: Likewise.
795
0d6a2f58
L		 7962008-01-13 H.J. Lu <hongjiu.lu@intel.com>
797
798 * i386-opc.h (Byte): Fix a typo.
799
7d5e4556
L		 8002008-01-12 H.J. Lu <hongjiu.lu@intel.com>
801
802 PR gas/5534
803 * i386-gen.c (operand_type_init): Add Dword to
804 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
805 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
806 Qword and Xmmword.
807 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
808 Xmmword, Unspecified and Anysize.
809 (set_bitfield): Make Mmword an alias of Qword. Make Oword
810 an alias of Xmmword.
811
812 * i386-opc.h (CheckSize): Removed.
813 (Byte): Updated.
814 (Word): Likewise.
815 (Dword): Likewise.
816 (Qword): Likewise.
817 (Xmmword): Likewise.
818 (FWait): Updated.
819 (OTMax): Likewise.
820 (i386_opcode_modifier): Remove checksize, byte, word, dword,
821 qword and xmmword.
822 (Fword): New.
823 (TBYTE): Likewise.
824 (Unspecified): Likewise.
825 (Anysize): Likewise.
826 (i386_operand_type): Add byte, word, dword, fword, qword,
827 tbyte xmmword, unspecified and anysize.
828
829 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
830 Tbyte, Xmmword, Unspecified and Anysize.
831
832 * i386-reg.tbl: Add size for accumulator.
833
834 * i386-init.h: Regenerated.
835 * i386-tbl.h: Likewise.
836
b5b1fc4f
L		 8372008-01-10 H.J. Lu <hongjiu.lu@intel.com>
838
839 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
840 (REG_0F18): Updated.
841 (reg_table): Updated.
842 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
843 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
844
50e8458f
L		 8452008-01-08 H.J. Lu <hongjiu.lu@intel.com>
846
847 * i386-gen.c (set_bitfield): Use fail () on error.
848
3d4d5afa
L		 8492008-01-08 H.J. Lu <hongjiu.lu@intel.com>
850
851 * i386-gen.c (lineno): New.
852 (filename): Likewise.
853 (set_bitfield): Report filename and line numer on error.
854 (process_i386_opcodes): Set filename and update lineno.
855 (process_i386_registers): Likewise.
856
e1d4d893
L		 8572008-01-05 H.J. Lu <hongjiu.lu@intel.com>
858
859 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
860 ATTSyntax.
861
862 * i386-opc.h (IntelMnemonic): Renamed to ..
863 (ATTSyntax): This
864 (Opcode_Modifier_Max): Updated.
865 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
866 and intelsyntax.
867
8944f3c2 868 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 869 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
870 * i386-tbl.h: Regenerated.
871
6f143e4d
L		 8722008-01-04 H.J. Lu <hongjiu.lu@intel.com>
873
874 * i386-gen.c: Update copyright to 2008.
875 * i386-opc.h: Likewise.
876 * i386-opc.tbl: Likewise.
877
878 * i386-init.h: Regenerated.
879 * i386-tbl.h: Likewise.
880
c6add537
L		 8812008-01-04 H.J. Lu <hongjiu.lu@intel.com>
882
883 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
884 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
885 * i386-tbl.h: Regenerated.
886
3629bb00
L		 8872008-01-03 H.J. Lu <hongjiu.lu@intel.com>
888
889 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
890 CpuSSE4_2_Or_ABM.
891 (cpu_flags): Likewise.
892
893 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
894 (CpuSSE4_2_Or_ABM): Likewise.
895 (CpuLM): Updated.
896 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
897
898 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
899 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
900 and CpuPadLock, respectively.
901 * i386-init.h: Regenerated.
902 * i386-tbl.h: Likewise.
903
24995bd6
L		 9042008-01-03 H.J. Lu <hongjiu.lu@intel.com>
905
906 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
907
908 * i386-opc.h (No_xSuf): Removed.
909 (CheckSize): Updated.
910
911 * i386-tbl.h: Regenerated.
912
e0329a22
L		 9132008-01-02 H.J. Lu <hongjiu.lu@intel.com>
914
915 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
916 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
917 CPU_SSE5_FLAGS.
918 (cpu_flags): Add CpuSSE4_2_Or_ABM.
919
920 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
921 (CpuLM): Updated.
922 (i386_cpu_flags): Add cpusse4_2_or_abm.
923
924 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
925 CpuABM|CpuSSE4_2 on popcnt.
926 * i386-init.h: Regenerated.
927 * i386-tbl.h: Likewise.
928
f2a9c676
L		 9292008-01-02 H.J. Lu <hongjiu.lu@intel.com>
930
931 * i386-opc.h: Update comments.
932
d978b5be
L		 9332008-01-02 H.J. Lu <hongjiu.lu@intel.com>
934
935 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
936 * i386-opc.h: Likewise.
937 * i386-opc.tbl: Likewise.
938
582d5edd
L		 9392008-01-02 H.J. Lu <hongjiu.lu@intel.com>
940
941 PR gas/5534
942 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
943 Byte, Word, Dword, QWord and Xmmword.
944
945 * i386-opc.h (No_xSuf): New.
946 (CheckSize): Likewise.
947 (Byte): Likewise.
948 (Word): Likewise.
949 (Dword): Likewise.
950 (QWord): Likewise.
951 (Xmmword): Likewise.
952 (FWait): Updated.
953 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
954 Dword, QWord and Xmmword.
955
956 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
957 used.
958 * i386-tbl.h: Regenerated.
959
3fe15143
MK		 9602008-01-02 Mark Kettenis <kettenis@gnu.org>
961
962 * m88k-dis.c (instructions): Fix fcvt.* instructions.
963 From Miod Vallat.
964
6c7ac64e 965For older changes see ChangeLog-2007
252b5132
RH		 966\f
967Local Variables:
2f6d2f85
NC		 968mode: change-log
969left-margin: 8
970fill-column: 74
252b5132
RH		 971version-control: never
972End:
GDB Binutils - Deliverables
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