projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* ltmain.sh: Update from GCC.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
37ad9514
SE		 12007-05-24 Steve Ellcey <sje@cup.hp.com>
2
3 * Makefile.in: Regnerate.
4 * configure: Regenerate.
5 * aclocal.m4: Regenerate.
6
65b650b4
AM		 72007-05-18 Alan Modra <amodra@bigpond.net.au>
8
9 * ppc-dis.c (print_insn_powerpc): Don't skip all operands
10 after setting skip_optional.
11
ea192fa3
PB		 122007-05-16 Peter Bergner <bergner@vnet.ibm.com>
13
14 * ppc-dis.c (operand_value_powerpc, skip_optional_operands): New.
15 (print_insn_powerpc): Use the new operand_value_powerpc and
16 skip_optional_operands functions to omit or print all optional
17 operands as a group.
18 * ppc-opc.c (BFF, W, XFL_L, XWRA_MASK): New.
19 (XFL_MASK): Delete L and W bits from the mask.
20 (mtfsfi, mtfsfi.): Replace use of BF with BFF. Relpace use of XRA_MASK
21 with XWRA_MASK. Use W.
22 (mtfsf, mtfsf.): Use XFL_L and W.
23
9beff690
L		 242007-05-14 H.J. Lu <hongjiu.lu@intel.com>
25
26 PR binutils/4502
27 * i386-dis.c (Suffix3DNow): Replace "pfmulhrw" with "pmulhrw".
28
4d67a4d3
L		 292007-05-10 H.J. Lu <hongjiu.lu@intel.com>
30
31 * i386-opc.h (ShortForm): Redefined.
32 (Jump): Likewise.
33 (JumpDword): Likewise.
34 (JumpByte): Likewise.
35 (JumpInterSegment): Likewise.
36 (FloatMF): Likewise.
37 (FloatR): Likewise.
38 (FloatD): Likewise.
39 (Size16): Likewise.
40 (Size32): Likewise.
41 (Size64): Likewise.
42 (IgnoreSize): Likewise.
43 (DefaultSize): Likewise.
44 (No_bSuf): Likewise.
45 (No_wSuf): Likewise.
46 (No_lSuf): Likewise.
47 (No_sSuf): Likewise.
48 (No_qSuf): Likewise.
49 (No_xSuf): Likewise.
50 (FWait): Likewise.
51 (IsString): Likewise.
52 (regKludge): Likewise.
53 (IsPrefix): Likewise.
54 (ImmExt): Likewise.
55 (NoRex64): Likewise.
56 (Rex64): Likewise.
57 (Ugh): Likewise.
58
8de28984
L		 592007-05-07 H.J. Lu <hongjiu.lu@intel.com>
60
61 * i386-dis.c (threebyte_0x38_uses_DATA_prefix): Correct entries
62 for some SSE4 instructions.
63 (threebyte_0x3a_uses_DATA_prefix): Likewise.
64
20592a94
L		 652007-05-03 H.J. Lu <hongjiu.lu@intel.com>
66
67 * i386-dis.c (CRC32_Fixup): Don't print suffix in Intel mode.
68
69 * i386-opc.c (i386_optab): Remove IgnoreSize and correct operand
70 type for crc32.
71
9344ff29
L		 722007-05-01 H.J. Lu <hongjiu.lu@intel.com>
73
74 * i386-dis.c (CRC32_Fixup): Properly handle Intel mode and
75 check data size prefix in 16bit mode.
76
77 * i386-opc.c (i386_optab): Default crc32 to non-8bit and
78 support Intel mode.
79
53289dcd 802007-04-30 Mark Salter <msalter@redhat.com>
65b650b4 81
53289dcd
MS		 82 * frv-desc.c: Regenerate.
83 * frv-desc.h: Regenerate.
65b650b4 84
eb42fac1
AM		 852007-04-30 Alan Modra <amodra@bigpond.net.au>
86
87 PR 4436
88 * ppc-opc.c (powerpc_operands): Correct bitm for second entry of MBE.
89
484c222e
L		 902007-04-27 H.J. Lu <hongjiu.lu@intel.com>
91
92 * i386-dis.c (modrm): Put reg before rm.
93
5d669648
L		 942007-04-26 H.J. Lu <hongjiu.lu@intel.com>
95
96 PR binutils/4430
97 * i386-dis.c (print_displacement): New.
98 (OP_E): Call print_displacement instead of print_operand_value
99 to output displacement when either base or index exist. Print
100 the explicit zero displacement in 16bit mode.
101
185b1163
L		 1022007-04-26 H.J. Lu <hongjiu.lu@intel.com>
103
104 PR binutils/4429
105 * i386-dis.c (print_insn): Also swap the order of op_riprel
106 when swapping op_index. Break when the RIP relative address
107 is printed.
108 (OP_E): Properly handle RIP relative addressing and print the
109 explicit zero displacement for Intel mode.
110
eddc20ad
AM		 1112007-04-27 Alan Modra <amodra@bigpond.net.au>
112
113 * Makefile.am: Run "make dep-am".
114 * Makefile.in: Regenerate.
115 * ns32k-dis.c: Include sysdep.h first.
116
dacc8b01
MS		 1172007-04-24 Andreas Krebbel <krebbel1@de.ibm.com>
118
119 * opcodes/s390-opc.c (MASK_SSF_RRDRD): Fourth nybble belongs to the
120 opcode.
eddc20ad
AM		 121 * opcodes/s390-opc.txt (pfpo, ectg, csst): Add new z9-ec instructions.
122
fbb92301
NC		 1232007-04-24 Nick Clifton <nickc@redhat.com>
124
125 * arm-dis.c (print_insn): Initialise type.
126
4c273957
AM		 1272007-04-24 Alan Modra <amodra@bigpond.net.au>
128
129 * cgen-types.h: Include bfd_stdint.h, not stdint.h.
130 * Makefile.am: Run "make dep-am".
131 * Makefile.in: Regenerate.
132
9a2e615a
NS		 1332007-04-23 Nathan Sidwell <nathan@codesourcery.com>
134
135 * m68k-opc.c: Mark mcfisa_c instructions.
136
37b37b2d
RE		 1372007-04-21 Richard Earnshaw <rearnsha@arm.com>
138
139 * arm-dis.c (arm_opcodes): Disassemble to unified syntax.
140 (thumb_opcodes): Add missing white space in adr.
65b650b4 141 (arm_decode_shift): New parameter, print_shift. Only decode the
37b37b2d
RE		 142 shift parameter if set. Adjust callers.
143 (print_insn_arm): Support for operand type q with no shift decode.
144
717bbdf1
AM		 1452007-04-21 Alan Modra <amodra@bigpond.net.au>
146
db557034
AM		 147 * i386-opc.c (i386_float_regtab, i386_float_regtab_size): Delete.
148 Move contents to..
149 (i386_regtab): ..here.
150 * i386-opc.h (i386_float_regtab, i386_float_regtab_size): Delete.
151
717bbdf1
AM		 152 * ppc-opc.c (powerpc_operands): Delete duplicate entries.
153 (BA_MASK, FXM_MASK, STRM_MASK, VA_MASK, VB_MASK, VC_MASK): Delete.
154 (VD_MASK, WS_MASK, MTMSRD_L, XRT_L): Delete.
155 (powerpc_opcodes): Replace uses of MTMSRD_L and XRT_L.
156
78336706
NS		 1572007-04-20 Nathan Sidwell <nathan@codesourcery.com>
158
159 * m68k-dis.c (print_insn_arg): Show c04 as rambar0 and c05 as
160 rambar1.
161
b84bf58a
AM		 1622007-04-20 Alan Modra <amodra@bigpond.net.au>
163
164 * ppc-dis.c (print_insn_powerpc): Adjust for struct powerpc_operand
165 change.
166 * ppc-opc.c (powerpc_operands): Replace bit count with bit mask
167 in all entries. Add PPC_OPERAND_SIGNED to DE entry. Remove
168 references to following deleted functions.
169 (insert_bd, extract_bd, insert_dq, extract_dq): Delete.
170 (insert_ds, extract_ds, insert_de, extract_de): Delete.
171 (insert_des, extract_des, insert_li, extract_li): Delete.
172 (insert_nb, insert_rsq, insert_rtq, insert_ev2, extract_ev2): Delete.
173 (insert_ev4, extract_ev4, insert_ev8, extract_ev8): Delete.
174 (num_powerpc_operands): New constant.
175 (XSPRG_MASK): Remove entire SPRG field.
176 (powerpc_opcodes <bcctre, bcctrel>): Use XLBB_MASK not XLYBB_MASK.
177
0bbdef92
AM		 1782007-04-20 Alan Modra <amodra@bigpond.net.au>
179
180 * ppc-opc.c (DCM, DGM, TE, RMC, R, SP, S): Correct shift.
181 (Z2_MASK): Define.
182 (powerpc_opcodes): Use Z2_MASK in all insns taking RMC operand.
183
86ad2a13
RE		 1842007-04-20 Richard Earnshaw <rearnsha@arm.com>
185
186 * arm-dis.c (print_insn): Only look for a mapping symbol in the section
187 being disassembled.
188
a33e055d
AM		 1892007-04-19 Alan Modra <amodra@bigpond.net.au>
190
191 * Makefile.am: Run "make dep-am".
192 * Makefile.in: Regenerate.
193 * po/POTFILES.in: Regenerate.
194
360b1600
AM		 1952007-04-19 Alan Modra <amodra@bigpond.net.au>
196
197 * ppc-opc.c (powerpc_opcodes): Add cctpl, cctpm, cctph, db8cyc,
198 db10cyc, db12cyc, db16cyc.
199
b20ae55e
AM		 2002007-04-19 Nathan Froyd <froydnj@codesourcery.com>
201
202 * ppc-opc.c (powerpc_opcodes): Recognize three-operand tlbsxe.
203
381d071f
L		 2042007-04-18 H.J. Lu <hongjiu.lu@intel.com>
205
206 * i386-dis.c (CRC32_Fixup): New.
207 (PREGRP85, PREGRP86, PREGRP87, PREGRP88, PREGRP89, PREGRP90,
208 PREGRP91): New.
209 (threebyte_0x38_uses_DATA_prefix): Updated for SSE4.2.
210 (threebyte_0x3a_uses_DATA_prefix): Likewise.
211 (prefix_user_table): Add PREGRP85, PREGRP86, PREGRP87,
212 PREGRP88, PREGRP89, PREGRP90 and PREGRP91.
213 (three_byte_table): Likewise.
214
215 * i386-opc.c (i386_optab): Add SSE4.2 opcodes.
216
f6fdceb7 217 * i386-opc.h (CpuSSE4_2): New.
381d071f
L		 218 (CpuSSE4): Likewise.
219 (CpuUnknownFlags): Add CpuSSE4_2.
220
42903f7f
L		 2212007-04-18 H.J. Lu <hongjiu.lu@intel.com>
222
223 * i386-dis.c (XMM_Fixup): New.
224 (Edqb): New.
225 (Edqd): New.
226 (XMM0): New.
227 (dqb_mode): New.
228 (dqd_mode): New.
229 (PREGRP39 ... PREGRP85): New.
230 (threebyte_0x38_uses_DATA_prefix): Updated for SSE4.
231 (threebyte_0x3a_uses_DATA_prefix): Likewise.
232 (prefix_user_table): Add PREGRP39 ... PREGRP85.
233 (three_byte_table): Likewise.
234 (putop): Handle 'K'.
235 (intel_operand_size): Handle dqb_mode, dqd_mode):
236 (OP_E): Likewise.
237 (OP_G): Likewise.
238
239 * i386-opc.c (i386_optab): Add SSE4.1 opcodes.
240
241 * i386-opc.h (CpuSSE4_1): New.
242 (CpuUnknownFlags): Add CpuSSE4_1.
243 (regKludge): Update comment.
244
ee5c21a0
DJ		 2452007-04-18 Matthias Klose <doko@ubuntu.com>
246
247 * Makefile.am (libopcodes_la_LDFLAGS): Use bfd soversion.
248 * Makefile.in: Regenerate.
249
b7d19ba6
SE		 2502007-04-14 Steve Ellcey <sje@cup.hp.com>
251
252 * Makefile.am: Add ACLOCAL_AMFLAGS.
253 * Makefile.in: Regenerate.
254
246c51aa
L		 2552007-04-13 H.J. Lu <hongjiu.lu@intel.com>
256
257 * i386-dis.c: Remove trailing white spaces.
6e26e51a
L		 258 * i386-opc.c: Likewise.
259 * i386-opc.h: Likewise.
246c51aa 260
7967e09e
L		 2612007-04-11 H.J. Lu <hongjiu.lu@intel.com>
262
263 PR binutils/4333
264 * i386-dis.c (GRP1a): New.
265 (GRP1b ... GRPPADLCK2): Update index.
266 (dis386): Use GRP1a for entry 0x8f.
267 (mod, rm, reg): Removed. Replaced by ...
268 (modrm): This.
269 (grps): Add GRP1a.
270
56dc1f8a
KH		 2712007-04-09 Kazu Hirata <kazu@codesourcery.com>
272
273 * m68k-dis.c (print_insn_m68k): Restore info->fprintf_func and
274 info->print_address_func if longjmp is called.
275
144f4bc6
DD		 2762007-03-29 DJ Delorie <dj@redhat.com>
277
278 * m32c-desc.c: Regenerate.
279 * m32c-dis.c: Regenerate.
280 * m32c-opc.c: Regenerate.
281
e72cf3ec
L		 2822007-03-28 H.J. Lu <hongjiu.lu@intel.com>
283
284 * i386-opc.c (i386_optab): Change InvMem to RegMem for mov and
285 movq. Remove InvMem from sldt, smsw and str.
286
287 * i386-opc.h (InvMem): Renamed to ...
288 (RegMem): Update comments.
289 (AnyMem): Remove InvMem.
290
831480e9 2912007-03-27 Paul Brook <paul@codesourcery.com>
b74ed8f5 292
b74ed8f5
PB		 293 * arm-dis.c (thumb_opcodes): Add entry for undefined insns (0xbe??).
294
4146fd53
PB		 2952007-03-24 Paul Brook <paul@codesourcery.com>
296
297 * arm-dis.c (coprocessor_opcodes): Remove superfluous 0x.
298 (print_insn_coprocessor): Handle %<bitfield>x.
299
b6702015 3002007-03-24 Paul Brook <paul@codesourcery.com>
e72cf3ec 301 Mark Shinwell <shinwell@codesourcery.com>
b6702015
PB		 302
303 * arm-dis.c (arm_opcodes): Print SRS base register.
304
831480e9 3052007-03-23 H.J. Lu <hongjiu.lu@intel.com>
0003779b
L		 306
307 * i386-dis.c (prefix_name): Replace rex64XYZ with rex.WRXB.
308
309 * i386-opc.c (i386_optab): Add rex.wrxb.
310
831480e9 3112007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 312
313 * i386-dis.c (REX_MODE64): Remove definition.
314 (REX_EXTX): Likewise.
315 (REX_EXTY): Likewise.
316 (REX_EXTZ): Likewise.
317 (USED_REX): Use REX_OPCODE instead of 0x40.
318 Replace REX_MODE64, REX_EXTX, REX_EXTY and REX_EXTZ with REX_W,
319 REX_R, REX_X and REX_B respectively.
320
831480e9 3212007-03-21 H.J. Lu <hongjiu.lu@intel.com>
8b38ad71
L		 322
323 PR binutils/4218
324 * i386-dis.c (PREGRP38): New.
325 (dis386): Use PREGRP38 for 0x90.
326 (prefix_user_table): Add PREGRP38.
327 (print_insn): Set uses_REPZ_prefix to 1 for pause.
328 (NOP_Fixup1): Properly handle REX bits.
329 (NOP_Fixup2): Likewise.
330
331 * i386-opc.c (i386_optab): Allow %eax with xchg in 64bit.
332 Allow register with nop.
333
75b06e7b
DD		 3342007-03-20 DJ Delorie <dj@redhat.com>
335
336 * m32c-asm.c: Regenerate.
337 * m32c-desc.c: Regenerate.
338 * m32c-desc.h: Regenerate.
339 * m32c-dis.h: Regenerate.
340 * m32c-ibld.c: Regenerate.
341 * m32c-opc.c: Regenerate.
342 * m32c-opc.h: Regenerate.
343
c3fe08fa
L		 3442007-03-15 H.J. Lu <hongjiu.lu@intel.com>
345
346 * i386-opc.c: Include "libiberty.h".
347 (i386_regtab): Remove the last entry.
348 (i386_regtab_size): New.
349 (i386_float_regtab_size): Likewise.
350
351 * i386-opc.h (i386_regtab_size): New.
352 (i386_float_regtab_size): Likewise.
353
0b1cf022
L		 3542007-03-15 H.J. Lu <hongjiu.lu@intel.com>
355
356 * Makefile.am (CFILES): Add i386-opc.c.
357 (ALL_MACHINES): Add i386-opc.lo.
358 Run "make dep-am".
359 * Makefile.in: Regenerated.
360
361 * configure.in: Add i386-opc.lo for bfd_i386_arch.
362 * configure: Regenerated.
363
364 * i386-dis.c: Include "opcode/i386.h".
365 (MAXLEN): Renamed to MAX_MNEM_SIZE. Remove definition.
366 (FWAIT_OPCODE): Remove definition.
367 (UNIXWARE_COMPAT): Renamed to SYSV386_COMPAT. Remove definition.
368 (MAX_OPERANDS): Remove definition.
369
370 * i386-opc.c: New file.
371 * i386-opc.h: Likewise.
372
56eced12
L		 3732007-03-15 H.J. Lu <hongjiu.lu@intel.com>
374
375 * Makefile.in: Regenerated.
376
6f74c397
L		 3772007-03-09 H.J. Lu <hongjiu.lu@intel.com>
378
379 * i386-dis.c (OP_Rd): Renamed to ...
380 (OP_R): This.
381 (Rd): Updated.
382 (Rm): Likewise.
383
a6d04ec4
AM		 3842007-03-08 Alan Modra <amodra@bigpond.net.au>
385
1620f33d
AM		 386 * fr30-asm.c: Regenerate.
387 * frv-asm.c: Regenerate.
388 * ip2k-asm.c: Regenerate.
389 * iq2000-asm.c: Regenerate.
390 * m32c-asm.c: Regenerate.
391 * m32r-asm.c: Regenerate.
392 * m32r-dis.c: Regenerate.
393 * mt-asm.c: Regenerate.
394 * mt-ibld.c: Regenerate.
395 * mt-opc.c: Regenerate.
396 * openrisc-asm.c: Regenerate.
397 * xc16x-asm.c: Regenerate.
398 * xstormy16-asm.c: Regenerate.
399
a6d04ec4
AM		 400 * Makefile.am: Run "make dep-am".
401 * Makefile.in: Regenerate.
402 * po/POTFILES.in: Regenerate.
403
b5639b37
MS		 4042007-03-06 Andreas Krebbel <krebbel1@de.ibm.com>
405
406 * opcodes/s390-opc.c (INSTR_RRE_FR, INSTR_RRF_F0FF2, INSTR_RRF_F0FR,
407 INSTR_RRF_UUFF, INSTR_RRF_0UFF, INSTR_RRF_FFFU, INSTR_RRR_F0FF): New
408 instruction formats added.
409 (MASK_RRE_FR, MASK_RRF_F0FF2, MASK_RRF_F0FR, MASK_RRF_UUFF,
410 MASK_RRF_0UFF, MASK_RRF_FFFU, MASK_RRR_F0FF): New instruction format
411 masks added.
412 * opcodes/s390-opc.txt (lpdfr - tgxt): Decimal floating point
413 instructions added.
414 * opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added.
415 (main): z9-ec cpu type option added.
416 * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added.
417
b2e818b7
DD		 4182007-02-22 DJ Delorie <dj@redhat.com>
419
420 * s390-opc.c (INSTR_SS_L2RDRD): New.
421 (MASK_SS_L2RDRD): New.
422 * s390-opc.txt (pka): Use it.
423
8b082fb1
TS		 4242007-02-20 Thiemo Seufer <ths@mips.com>
425 Chao-Ying Fu <fu@mips.com>
426
427 * mips-dis.c (mips_arch_choices): Add DSP R2 support.
428 (print_insn_args): Add support for balign instruction.
429 * mips-opc.c (D33): New shortcut for DSP R2 instructions.
430 (mips_builtin_opcodes): Add DSP R2 instructions.
431
929e4d1a
MS		 4322007-02-19 Andreas Krebbel <krebbel1@de.ibm.com>
433
434 * s390-opc.c (INSTR_RRF_U0FR, MASK_RRF_U0FR): Removed.
435 (INSTR_RRF_U0RF, MASK_RRF_U0RF): Added.
436 * s390-opc.txt (cfxbr, cfdbr, cfebr, cgebr, cgdbr, cgxbr, cger, cgdr,
437 cgxr, cfxr, cfdr, cfer): Instruction type set to INSTR_RRF_U0RF.
438
b8e55848
MS		 4392007-02-19 Andreas Krebbel <krebbel1@de.ibm.com>
440
441 * s390-opc.txt ("efpc", "sfpc"): Set to RRE_RR_OPT instruction type.
442 * s390-opc.c (s390_operands): Add RO_28 as optional gpr.
443 (INSTR_RRE_RR_OPT, MASK_RRE_RR_OPT): New instruction type for efpc
444 and sfpc.
445
af692060
NC		 4462007-02-16 Nick Clifton <nickc@redhat.com>
447
448 PR binutils/4045
449 * avr-dis.c (comment_start): New variable, contains the prefix to
450 use when printing addresses in comments.
451 (print_insn_avr): Set comment_start to an empty space if there is
452 no symbol table available as the generic address printing code
453 will prefix the numeric value of the address with 0x.
454
ce518a5f
L		 4552007-02-13 H.J. Lu <hongjiu.lu@intel.com>
456
457 * i386-dis.c: Updated to use an array of MAX_OPERANDS operands
458 in struct dis386.
459
bd2f2e55 4602007-02-05 Dave Brolley <brolley@redhat.com>
8c9c183d
DB		 461 Richard Sandiford <rsandifo@redhat.com>
462 DJ Delorie <dj@redhat.com>
463 Graydon Hoare <graydon@redhat.com>
464 Frank Ch. Eigler <fche@redhat.com>
465 Ben Elliston <bje@redhat.com>
466
467 * Makefile.am (HFILES): Add mep-desc.h mep-opc.h.
468 (CFILES): Add mep-*.c
469 (ALL_MACHINES): Add mep-*.lo.
470 (CLEANFILES): Add stamp-mep.
471 (CGEN_CPUS): Add mep.
472 (MEP_DEPS): New variable.
473 (mep-*): New targets.
474 * configure.in: Handle bfd_mep_arch.
475 * disassemble.c (ARCH_mep): New macro.
476 (disassembler): Handle bfd_arch_mep.
477 (disassemble_init_for_target): Likewise.
478 * mep-*: New files for Toshiba Media Processor (MeP).
bd2f2e55
DB		 479 * Makefile.in: Regenerated.
480 * configure: Regenerated.
481
eb7834a6 4822007-02-05 H.J. Lu <hongjiu.lu@intel.com>
65ca155d
L		 483
484 * i386-dis.c (OP_J): Undo the last change. Properly handle 64K
485 wrap around within the same segment in 16bit mode.
486
eb7834a6 4872007-02-02 H.J. Lu <hongjiu.lu@intel.com>
206717e8
L		 488
489 * i386-dis.c (OP_J): Mask to 16bit only if there is a data16
490 prefix.
491
c4f5c3d7
L		 4922007-02-02 H.J. Lu <hongjiu.lu@intel.com>
493
494 * avr-dis.c (avr_operand): Correct PR number in comment.
495
fc523535 4962007-02-02 H.J. Lu <hongjiu.lu@intel.com>
f59a29b9
L		 497
498 * disassemble.c (disassembler_usage): Call
499 print_i386_disassembler_options for i386 disassembler.
500
501 * i386-dis.c (print_i386_disassembler_options): New.
502 (print_insn): Support the new addr64 option.
503
64a3a6fc
NC		 5042007-02-02 Hiroki Kaminaga <kaminaga@sm.sony.co.jp>
505
506 * ppc-dis.c (powerpc_dialect): Handle ppc440.
507 * ppc-dis.c (print_ppc_disassembler_options): Note the -M440 can
508 be used.
509
ba4e851b
AM		 5102007-02-02 Alan Modra <amodra@bigpond.net.au>
511
512 * ppc-opc.c (insert_bdm): -Many comment.
513 (valid_bo): Add "extract" param. Accept both powerpc and power4
514 BO fields when disassembling with -Many.
515 (insert_bo, extract_bo, insert_boe, extract_boe): Adjust valid_bo call.
516
3bdcfdf4
KH		 5172007-01-08 Kazu Hirata <kazu@codesourcery.com>
518
519 * m68k-opc.c (m68k_opcodes): Replace cpu32 with
520 cpu32 | fido_a except on tbl instructions.
521
a028a6f5
PB		 5222007-01-04 Paul Brook <paul@codesourcery.com>
523
524 * arm-dis.c (arm_opcodes): Fix cpsie and cpsid entries.
525
baee4c9e
AS		 5262007-01-04 Andreas Schwab <schwab@suse.de>
527
528 * m68k-opc.c: Fix encoding of signed bit in the cpu32 tbls insns.
529
62ac925e
JB		 5302007-01-04 Julian Brown <julian@codesourcery.com>
531
532 * arm-dis.c (neon_opcode): Fix disassembly for vshl, vqshl, vrshl,
533 vqrshl instructions.
534
10a2343e 535For older changes see ChangeLog-2006
252b5132
RH		 536\f
537Local Variables:
2f6d2f85
NC		 538mode: change-log
539left-margin: 8
540fill-column: 74
252b5132
RH		 541version-control: never
542End:
GDB Binutils - Deliverables
This page took 0.594475 seconds and 4 git commands to generate.