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* fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
37ec9240
DE		 12010-02-11 Doug Evans <dje@sebabeach.org>
2
3 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
4 * frv-desc.c, * frv-desc.h, * frv-opc.c,
5 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
6 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
7 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
8 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
9 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
10 * mep-desc.c, * mep-desc.h, * mep-opc.c,
11 * mt-desc.c, * mt-desc.h, * mt-opc.c,
12 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
13 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
14 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
15
c75ef631
L		 162010-02-11 H.J. Lu <hongjiu.lu@intel.com>
17
18 * i386-dis.c: Update copyright.
19 * i386-gen.c: Likewise.
20 * i386-opc.h: Likewise.
21 * i386-opc.tbl: Likewise.
22
a683cc34
SP		 232010-02-10 Quentin Neill <quentin.neill@amd.com>
24 Sebastian Pop <sebastian.pop@amd.com>
25
26 * i386-dis.c (OP_EX_VexImmW): Reintroduced
27 function to handle 5th imm8 operand.
28 (PREFIX_VEX_3A48): Added.
29 (PREFIX_VEX_3A49): Added.
30 (VEX_W_3A48_P_2): Added.
31 (VEX_W_3A49_P_2): Added.
32 (prefix table): Added entries for PREFIX_VEX_3A48
33 and PREFIX_VEX_3A49.
34 (vex table): Added entries for VEX_W_3A48_P_2 and
35 and VEX_W_3A49_P_2.
36 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
37 for Vec_Imm4 operands.
38 * i386-opc.h (enum): Added Vec_Imm4.
39 (i386_operand_type): Added vec_imm4.
40 * i386-opc.tbl: Add entries for vpermilp[ds].
41 * i386-init.h: Regenerated.
42 * i386-tbl.h: Regenerated.
43
cdc51b07
RS		 442010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
45
46 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
47 and "pwr7". Move "a2" into alphabetical order.
48
ce3d2015
AM		 492010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
50
51 * ppc-dis.c (ppc_opts): Add titan entry.
52 * ppc-opc.c (TITAN, MULHW): Define.
53 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
54
68339fdf
SP		 552010-02-03 Quentin Neill <quentin.neill@amd.com>
56
57 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
58 to CPU_BDVER1_FLAGS
59 * i386-init.h: Regenerated.
60
f3d55a94
AG		 612010-02-03 Anthony Green <green@moxielogic.com>
62
63 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
64 0x0f, and make 0x00 an illegal instruction.
65
b0e28b39
DJ		 662010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
67
68 * opcodes/arm-dis.c (struct arm_private_data): New.
69 (print_insn_coprocessor, print_insn_arm): Update to use struct
70 arm_private_data.
71 (is_mapping_symbol, get_map_sym_type): New functions.
72 (get_sym_code_type): Check the symbol's section. Do not check
73 mapping symbols.
74 (print_insn): Default to disassembling ARM mode code. Check
75 for mapping symbols separately from other symbols. Use
76 struct arm_private_data.
77
1c480963
L		 782010-01-28 H.J. Lu <hongjiu.lu@intel.com>
79
80 * i386-dis.c (EXVexWdqScalar): New.
81 (vex_scalar_w_dq_mode): Likewise.
82 (prefix_table): Update entries for PREFIX_VEX_3899,
83 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
84 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
85 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
86 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
87 (intel_operand_size): Handle vex_scalar_w_dq_mode.
88 (OP_EX): Likewise.
89
539f890d
L		 902010-01-27 H.J. Lu <hongjiu.lu@intel.com>
91
92 * i386-dis.c (XMScalar): New.
93 (EXdScalar): Likewise.
94 (EXqScalar): Likewise.
95 (EXqScalarS): Likewise.
96 (VexScalar): Likewise.
97 (EXdVexScalarS): Likewise.
98 (EXqVexScalarS): Likewise.
99 (XMVexScalar): Likewise.
100 (scalar_mode): Likewise.
101 (d_scalar_mode): Likewise.
102 (d_scalar_swap_mode): Likewise.
103 (q_scalar_mode): Likewise.
104 (q_scalar_swap_mode): Likewise.
105 (vex_scalar_mode): Likewise.
106 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
107 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
108 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
109 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
110 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
111 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
112 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
113 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
114 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
115 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
116 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
117 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
118 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
119 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
120 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
121 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
122 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
123 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
124 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
125 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
126 q_scalar_mode, q_scalar_swap_mode.
127 (OP_XMM): Handle scalar_mode.
128 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
129 and q_scalar_swap_mode.
130 (OP_VEX): Handle vex_scalar_mode.
131
208b4d78
L		 1322010-01-24 H.J. Lu <hongjiu.lu@intel.com>
133
134 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
135
448b213a
L		 1362010-01-24 H.J. Lu <hongjiu.lu@intel.com>
137
138 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
139
47cf8fa0
L		 1402010-01-24 H.J. Lu <hongjiu.lu@intel.com>
141
142 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
143
592d1631
L		 1442010-01-24 H.J. Lu <hongjiu.lu@intel.com>
145
146 * i386-dis.c (Bad_Opcode): New.
147 (bad_opcode): Likewise.
148 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
149 (dis386_twobyte): Likewise.
150 (reg_table): Likewise.
151 (prefix_table): Likewise.
152 (x86_64_table): Likewise.
153 (vex_len_table): Likewise.
154 (vex_w_table): Likewise.
155 (mod_table): Likewise.
156 (rm_table): Likewise.
157 (float_reg): Likewise.
158 (reg_table): Remove trailing "(bad)" entries.
159 (prefix_table): Likewise.
160 (x86_64_table): Likewise.
161 (vex_len_table): Likewise.
162 (vex_w_table): Likewise.
163 (mod_table): Likewise.
164 (rm_table): Likewise.
165 (get_valid_dis386): Handle bytemode 0.
166
712366da
L		 1672010-01-23 H.J. Lu <hongjiu.lu@intel.com>
168
169 * i386-opc.h (VEXScalar): New.
170
171 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
172 instructions.
173 * i386-tbl.h: Regenerated.
174
706e8205 1752010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 176
177 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
178
179 * i386-opc.tbl: Add xsave64 and xrstor64.
180 * i386-tbl.h: Regenerated.
181
99ea83aa
NC		 1822010-01-20 Nick Clifton <nickc@redhat.com>
183
184 PR 11170
185 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
186 based post-indexed addressing.
187
a6461c02
SP		 1882010-01-15 Sebastian Pop <sebastian.pop@amd.com>
189
190 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
191 * i386-tbl.h: Regenerated.
192
a2a7d12c
L		 1932010-01-14 H.J. Lu <hongjiu.lu@intel.com>
194
195 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
196 comments.
197
b9733481
L		 1982010-01-14 H.J. Lu <hongjiu.lu@intel.com>
199
200 * i386-dis.c (names_mm): New.
201 (intel_names_mm): Likewise.
202 (att_names_mm): Likewise.
203 (names_xmm): Likewise.
204 (intel_names_xmm): Likewise.
205 (att_names_xmm): Likewise.
206 (names_ymm): Likewise.
207 (intel_names_ymm): Likewise.
208 (att_names_ymm): Likewise.
209 (print_insn): Set names_mm, names_xmm and names_ymm.
210 (OP_MMX): Use names_mm, names_xmm and names_ymm.
211 (OP_XMM): Likewise.
212 (OP_EM): Likewise.
213 (OP_EMC): Likewise.
214 (OP_MXC): Likewise.
215 (OP_EX): Likewise.
216 (XMM_Fixup): Likewise.
217 (OP_VEX): Likewise.
218 (OP_EX_VexReg): Likewise.
219 (OP_Vex_2src): Likewise.
220 (OP_Vex_2src_1): Likewise.
221 (OP_Vex_2src_2): Likewise.
222 (OP_REG_VexI4): Likewise.
223
5e6718e4
L		 2242010-01-13 H.J. Lu <hongjiu.lu@intel.com>
225
226 * i386-dis.c (print_insn): Update comments.
227
d869730d
L		 2282010-01-12 H.J. Lu <hongjiu.lu@intel.com>
229
230 * i386-dis.c (rex_original): Removed.
231 (ckprefix): Remove rex_original.
232 (print_insn): Update comments.
233
3725885a
RW		 2342010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
235
236 * Makefile.in: Regenerate.
237 * configure: Regenerate.
238
b7cd1872
DE		 2392010-01-07 Doug Evans <dje@sebabeach.org>
240
241 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
242 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
243 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
244 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
245 * xstormy16-ibld.c: Regenerate.
246
69dd9865
SP		 2472010-01-06 Quentin Neill <quentin.neill@amd.com>
248
249 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
250 * i386-init.h: Regenerated.
251
e3e535bc
NC		 2522010-01-06 Daniel Gutson <dgutson@codesourcery.com>
253
254 * arm-dis.c (print_insn): Fixed search for next symbol and data
255 dumping condition, and the initial mapping symbol state.
256
fe8afbc4
DE		 2572010-01-05 Doug Evans <dje@sebabeach.org>
258
259 * cgen-ibld.in: #include "cgen/basic-modes.h".
260 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
261 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
262 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
263 * xstormy16-ibld.c: Regenerate.
264
2edcd244
NC		 2652010-01-04 Nick Clifton <nickc@redhat.com>
266
267 PR 11123
268 * arm-dis.c (print_insn_coprocessor): Initialise value.
269
0dc93057
AM		 2702010-01-04 Edmar Wienskoski <edmar@freescale.com>
271
272 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
273
05994f45
DE		 2742010-01-02 Doug Evans <dje@sebabeach.org>
275
276 * cgen-asm.in: Update copyright year.
277 * cgen-dis.in: Update copyright year.
278 * cgen-ibld.in: Update copyright year.
279 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
280 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
281 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
282 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
283 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
284 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
285 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
286 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
287 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
288 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
289 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
290 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
291 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
292 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
293 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
294 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
295 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
296 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
297 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
298 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
299 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 300
43ecc30f 301For older changes see ChangeLog-2009
252b5132
RH		 302\f
303Local Variables:
2f6d2f85
NC		 304mode: change-log
305left-margin: 8
306fill-column: 74
252b5132
RH		 307version-control: never
308End:
GDB Binutils - Deliverables
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