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Backport link test fix from upstream Libtool:
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7df76b80
RE		 12008-12-15 Richard Earnshaw <rearnsha@arm.com>
2
3 * arm-dis.c (coprocessor_opcodes): Disassemble VFP instructions using
4 unified syntax.
5
03547503
L		 62008-12-08 H.J. Lu <hongjiu.lu@intel.com>
7
8 * i386-gen.c (opcode_modifiers): Move VexNDS before VexNDD.
9
efa7dee7
L		 102008-12-08 H.J. Lu <hongjiu.lu@intel.com>
11
12 * i386-dis.c (putop): Remove strayed comments.
13
2f3bb96a
BE		 142008-12-04 Ben Elliston <bje@au.ibm.com>
15
16 * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE
17 for -Mbooke.
18 (print_ppc_disassembler_options): Update usage.
19 * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove.
20 (BOOKE64): Remove.
21 (PPCCHLK64): Likewise.
22 (powerpc_opcodes): Remove all BOOKE64 instructions.
23
3aa3176b
TS		 242008-11-28 Joshua Kinard <kumba@gentoo.org>
25
26 * mips-dis.c (mips_arch_choices): Add r14000, r16000.
27
59b098c9
SR		 282008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
29
30 * cr16-dis.c (match_opcode): Truncate mcode to 32 bit and
31 adjusted the mask for 32-bit branch instruction.
32
e1c93c69
AM		 332008-11-27 Alan Modra <amodra@bigpond.net.au>
34
35 * ppc-opc.c (extract_sprg): Correct operand range check.
36
9f7678f6
AS		 372008-11-26 Andreas Schwab <schwab@suse.de>
38
39 * m68k-dis.c (NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE)
40 (NEXTDOUBLE, NEXTEXTEND, NEXTPACKED): Fix error handling.
41 (save_printer, save_print_address): Remove.
42 (fetch_data): Don't use them.
43 (match_insn_m68k): Always restore printing functions.
44 (print_insn_m68k): Don't save/restore printing functions.
45
62443ade
NC		 462008-11-25 Nick Clifton <nickc@redhat.com>
47
48 * m68k-dis.c: Rewrite to remove use of setjmp/longjmp.
49
8e79c3df
CM		 502008-11-18 Catherine Moore <clm@codesourcery.com>
51
52 * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt
53 instructions.
54 (neon_opcodes): Likewise.
55 (print_insn_coprocessor): Print 't' or 'b' for vcvt
56 instructions.
57
d387240a
TG		 582008-11-14 Tristan Gingold <gingold@adacore.com>
59
60 * makefile.vms (OBJS): Update list of objects.
61 (DEFS): Update
62 (CFLAGS): Update.
63
4dc48ef6
CF		 642008-11-06 Chao-ying Fu <fu@mips.com>
65
66 * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these
67 before sync.
68 (sync): New instruction with 5-bit sync type.
3c6528a8 69 * mips-dis.c (print_insn_args): Add case '1' to print 5-bit values.
4dc48ef6 70
c8941035
NC		 712008-11-06 Nick Clifton <nickc@redhat.com>
72
73 * avr-dis.c: Replace uses of sprintf without a format string with
74 calls to strcpy.
75
a7bea99d
L		 762008-11-03 H.J. Lu <hongjiu.lu@intel.com>
77
78 * i386-opc.tbl: Add cmovpe and cmovpo.
79 * i386-tbl.h: Regenerated.
80
4267b19f
NC		 812008-10-22 Nick Clifton <nickc@redhat.com>
82
83 PR 6937
84 * configure.in (SHARED_LIBADD): Revert previous change.
85 Add a comment explaining why.
86 (SHARED_DEPENDENCIES): Revert previous change.
87 * configure: Regenerate.
88
8a9629d0
NC		 892008-10-10 Nick Clifton <nickc@redhat.com>
90
91 PR 6937
92 * configure.in (SHARED_LIBADD): Add libiberty.a.
93 (SHARED_DEPENDENCIES): Add libiberty.a.
94
c587b3f9
L		 952008-09-30 H.J. Lu <hongjiu.lu@intel.com>
96
97 * i386-gen.c: Include "hashtab.h".
98 (next_field): Take a new argument, last. Check last.
99 (process_i386_cpu_flag): Updated.
100 (process_i386_opcode_modifier): Likewise.
101 (process_i386_operand_type): Likewise.
102 (process_i386_registers): Likewise.
103 (output_i386_opcode): New.
104 (opcode_hash_entry): Likewise.
105 (opcode_hash_table): Likewise.
106 (opcode_hash_hash): Likewise.
107 (opcode_hash_eq): Likewise.
108 (process_i386_opcodes): Use opcode hash table and opcode array.
109
34b23dab
AK		 1102008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
111
112 * s390-opc.txt (stdy, stey): Fix description
113
782e11fd
AM		 1142008-09-30 Alan Modra <amodra@bigpond.net.au>
115
116 * Makefile.am: Run "make dep-am".
117 * Makefile.in: Regenerate.
118
1927a18f
L		 1192008-09-29 H.J. Lu <hongjiu.lu@intel.com>
120
121 * aclocal.m4: Regenerated.
122 * configure: Likewise.
123 * Makefile.in: Likewise.
124
afac680a
NC		 1252008-09-29 Nick Clifton <nickc@redhat.com>
126
127 * po/vi.po: Updated Vietnamese translation.
128 * po/fr.po: Updated French translation.
129
b40d5eb9
AK		 1302008-09-26 Florian Krohm <fkrohm@us.ibm.com>
131
132 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
133 (cfxr, cfdr, cfer, clclu): Add esa flag.
134 (sqd): Instruction added.
135 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
136 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
137
d0411736
AM		 1382008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
139
140 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
141 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
142
3e126784
L		 1432008-09-11 H.J. Lu <hongjiu.lu@intel.com>
144
145 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
146 * i386-tbl.h: Regenerated.
147
ddab3d59
JB		 1482008-08-28 Jan Beulich <jbeulich@novell.com>
149
150 * i386-dis.c (dis386): Adjust far return mnemonics.
151 * i386-opc.tbl: Add retf.
152 * i386-tbl.h: Re-generate.
153
b19d5385
JB		 1542008-08-28 Jan Beulich <jbeulich@novell.com>
155
156 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
157
1ca35711
L		 1582008-08-28 H.J. Lu <hongjiu.lu@intel.com>
159
160 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
161 * ia64-gen.c (lookup_specifier): Likewise.
162
163 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
164 * ia64-raw.tbl: Likewise.
165 * ia64-waw.tbl: Likewise.
166 * ia64-asmtab.c: Regenerated.
167
515c56e7
L		 1682008-08-27 H.J. Lu <hongjiu.lu@intel.com>
169
170 * i386-opc.tbl: Correct fidivr operand size.
171
172 * i386-tbl.h: Regenerated.
173
da594c4a
AM		 1742008-08-24 Alan Modra <amodra@bigpond.net.au>
175
176 * configure.in: Update a number of obsolete autoconf macros.
177 * aclocal.m4: Regenerate.
178
a5ff0eb2
L		 1792008-08-20 H.J. Lu <hongjiu.lu@intel.com>
180
181 AVX Programming Reference (August, 2008)
182 * i386-dis.c (PREFIX_VEX_38DB): New.
183 (PREFIX_VEX_38DC): Likewise.
184 (PREFIX_VEX_38DD): Likewise.
185 (PREFIX_VEX_38DE): Likewise.
186 (PREFIX_VEX_38DF): Likewise.
187 (PREFIX_VEX_3ADF): Likewise.
188 (VEX_LEN_38DB_P_2): Likewise.
189 (VEX_LEN_38DC_P_2): Likewise.
190 (VEX_LEN_38DD_P_2): Likewise.
191 (VEX_LEN_38DE_P_2): Likewise.
192 (VEX_LEN_38DF_P_2): Likewise.
193 (VEX_LEN_3ADF_P_2): Likewise.
194 (PREFIX_VEX_3A04): Updated.
195 (VEX_LEN_3A06_P_2): Likewise.
196 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
197 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
198 (x86_64_table): Likewise.
199 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
200 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
201 VEX_LEN_3ADF_P_2.
202
203 * i386-opc.tbl: Add AES + AVX instructions.
204 * i386-init.h: Regenerated.
205 * i386-tbl.h: Likewise.
206
7dc6076f
AK		 2072008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
208
209 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
210 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
211
7357c5b6
AM		 2122008-08-15 Alan Modra <amodra@bigpond.net.au>
213
214 PR 6526
215 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
216 * Makefile.in: Regenerate.
217 * aclocal.m4: Regenerate.
218 * config.in: Regenerate.
219 * configure: Regenerate.
220
899d85be
AM		 2212008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
222
223 PR 6825
224 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
225
dfb07592
L		 2262008-08-12 H.J. Lu <hongjiu.lu@intel.com>
227
228 * i386-opc.tbl: Add syscall and sysret for Cpu64.
229
230 * i386-tbl.h: Regenerated.
231
323ee3f4
AM		 2322008-08-04 Alan Modra <amodra@bigpond.net.au>
233
234 * Makefile.am (POTFILES.in): Set LC_ALL=C.
235 * Makefile.in: Regenerate.
236 * po/POTFILES.in: Regenerate.
237
9b4e5766
PB		 2382008-08-01 Peter Bergner <bergner@vnet.ibm.com>
239
240 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
241 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
242 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
243 * ppc-opc.c (insert_xt6): New static function.
244 (extract_xt6): Likewise.
245 (insert_xa6): Likewise.
246 (extract_xa6: Likewise.
247 (insert_xb6): Likewise.
248 (extract_xb6): Likewise.
249 (insert_xb6s): Likewise.
250 (extract_xb6s): Likewise.
251 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
252 XX3DM_MASK, PPCVSX): New.
253 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
254 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
255
20fd6e2e
PA		 2562008-08-01 Pedro Alves <pedro@codesourcery.com>
257
258 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
259 * Makefile.in: Regenerate.
260
a656ed5b
L		 2612008-08-01 H.J. Lu <hongjiu.lu@intel.com>
262
263 * i386-reg.tbl: Use Dw2Inval on AVX registers.
264 * i386-tbl.h: Regenerated.
265
081ba1b3
AM		 2662008-07-30 Michael J. Eager <eager@eagercon.com>
267
268 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
269 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
270 (insert_sprg, PPC405): Use PPC_OPCODE_405.
271 (powerpc_opcodes): Add Xilinx APU related opcodes.
272
0af1713e
AM		 2732008-07-30 Alan Modra <amodra@bigpond.net.au>
274
275 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
276
30c09090
RS		 2772008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
278
279 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
280
c27e721e
AN		 2812008-07-07 Adam Nemet <anemet@caviumnetworks.com>
282
283 * mips-opc.c (CP): New macro.
284 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
285 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
286 dmtc2 Octeon instructions.
287
bd2e2557
SS		 2882008-07-07 Stan Shebs <stan@codesourcery.com>
289
290 * dis-init.c (init_disassemble_info): Init endian_code field.
291 * arm-dis.c (print_insn): Disassemble code according to
292 setting of endian_code.
293 (print_insn_big_arm): Detect when BE8 extension flag has been set.
294
6ba2a415
RS		 2952008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
296
297 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
298 for ELF symbols.
299
c8187e15
PB		 3002008-06-25 Peter Bergner <bergner@vnet.ibm.com>
301
302 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
303 (print_ppc_disassembler_options): Likewise.
304 * ppc-opc.c (PPC464): Define.
305 (powerpc_opcodes): Add mfdcrux and mtdcrux.
306
7a283e07
RW		 3072008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
308
309 * configure: Regenerate.
310
fa452fa6
PB		 3112008-06-13 Peter Bergner <bergner@vnet.ibm.com>
312
313 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
314 ppc_cpu_t typedef.
315 (struct dis_private): New.
316 (POWERPC_DIALECT): New define.
317 (powerpc_dialect): Renamed to...
318 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
319 struct dis_private.
320 (print_insn_big_powerpc): Update for using structure in
321 info->private_data.
322 (print_insn_little_powerpc): Likewise.
323 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
324 (skip_optional_operands): Likewise.
325 (print_insn_powerpc): Likewise. Remove initialization of dialect.
326 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
327 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
328 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
329 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
330 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
331 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
332 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
333 param to be of type ppc_cpu_t. Update prototype.
334
bb35fb24
NC		 3352008-06-12 Adam Nemet <anemet@caviumnetworks.com>
336
337 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
338 +s, +S.
339 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
340 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
341 syncw, syncws, vm3mulu, vm0 and vmulu.
342
dd3cbb7e
NC		 343 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
344 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
345 seqi, sne and snei.
346
a5dabbb0
L		 3472008-05-30 H.J. Lu <hongjiu.lu@intel.com>
348
349 * i386-opc.tbl: Add vmovd with 64bit operand.
350 * i386-tbl.h: Regenerated.
351
725a9891
MS		 3522008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
353
354 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
355
cbc80391
L		 3562008-05-22 H.J. Lu <hongjiu.lu@intel.com>
357
358 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
359 * i386-tbl.h: Regenerated.
360
116615c5
L		 3612008-05-22 H.J. Lu <hongjiu.lu@intel.com>
362
363 PR gas/6517
364 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
3c6528a8 365 into 32bit and 64bit. Remove Reg64|Qword and add
116615c5
L		 366 IgnoreSize|No_qSuf on 32bit version.
367 * i386-tbl.h: Regenerated.
368
d9479f2d
L		 3692008-05-21 H.J. Lu <hongjiu.lu@intel.com>
370
371 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
372 * i386-tbl.h: Regenerated.
373
3ce6fddb
NC		 3742008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
375
376 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
377
8944f3c2
AM		 3782008-05-14 Alan Modra <amodra@bigpond.net.au>
379
380 * Makefile.am: Run "make dep-am".
381 * Makefile.in: Regenerate.
382
f1f8f695
L		 3832008-05-02 H.J. Lu <hongjiu.lu@intel.com>
384
385 * i386-dis.c (MOVBE_Fixup): New.
386 (Mo): Likewise.
387 (PREFIX_0F3880): Likewise.
388 (PREFIX_0F3881): Likewise.
389 (PREFIX_0F38F0): Updated.
390 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
391 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
392 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
393
394 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
395 CPU_EPT_FLAGS.
396 (cpu_flags): Add CpuMovbe and CpuEPT.
397
398 * i386-opc.h (CpuMovbe): New.
399 (CpuEPT): Likewise.
400 (CpuLM): Updated.
401 (i386_cpu_flags): Add cpumovbe and cpuept.
402
403 * i386-opc.tbl: Add entries for movbe and EPT instructions.
404 * i386-init.h: Regenerated.
405 * i386-tbl.h: Likewise.
406
89aa3097
AN		 4072008-04-29 Adam Nemet <anemet@caviumnetworks.com>
408
409 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
410 the two drem and the two dremu macros.
411
39c5c168
AN		 4122008-04-28 Adam Nemet <anemet@caviumnetworks.com>
413
414 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
415 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
416 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
417 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
418
f04d18b7
DM		 4192008-04-25 David S. Miller <davem@davemloft.net>
420
421 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
422 instead of %sys_tick_cmpr, as suggested in architecture manuals.
423
6194aaab
L		 4242008-04-23 Paolo Bonzini <bonzini@gnu.org>
425
426 * aclocal.m4: Regenerate.
427 * configure: Regenerate.
428
1a6b486f
DM		 4292008-04-23 David S. Miller <davem@davemloft.net>
430
431 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
432 extended values.
433 (prefetch_table): Add missing values.
434
81f8a913
L		 4352008-04-22 H.J. Lu <hongjiu.lu@intel.com>
436
437 * i386-gen.c (opcode_modifiers): Add NoAVX.
438
439 * i386-opc.h (NoAVX): New.
440 (OldGcc): Updated.
441 (i386_opcode_modifier): Add noavx.
442
443 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
444 instructions which don't have AVX equivalent.
445 * i386-tbl.h: Regenerated.
446
dae39acc
L		 4472008-04-18 H.J. Lu <hongjiu.lu@intel.com>
448
449 * i386-dis.c (OP_VEX_FMA): New.
450 (OP_EX_VexImmW): Likewise.
451 (VexFMA): Likewise.
452 (Vex128FMA): Likewise.
453 (EXVexImmW): Likewise.
454 (get_vex_imm8): Likewise.
455 (OP_EX_VexReg): Likewise.
456 (vex_i4_done): Renamed to ...
457 (vex_w_done): This.
458 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
459 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
460 FMA instructions.
461 (print_insn): Updated.
462 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
463 (OP_REG_VexI4): Check invalid high registers.
464
ce886ab1
DR		 4652008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
466 Michael Meissner <michael.meissner@amd.com>
467
468 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
469 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 470
19a6653c
AM		 4712008-04-14 Edmar Wienskoski <edmar@freescale.com>
472
473 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
474 accept Power E500MC instructions.
475 (print_ppc_disassembler_options): Document -Me500mc.
476 * ppc-opc.c (DUIS, DUI, T): New.
477 (XRT, XRTRA): Likewise.
478 (E500MC): Likewise.
479 (powerpc_opcodes): Add new Power E500MC instructions.
480
112b7c50
AK		 4812008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
482
483 * s390-dis.c (init_disasm): Evaluate disassembler_options.
484 (print_s390_disassembler_options): New function.
485 * disassemble.c (disassembler_usage): Invoke
486 print_s390_disassembler_options.
487
7ff42648
AK		 4882008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
489
490 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
491 of local variables used for mnemonic parsing: prefix, suffix and
492 number.
493
45a5551e
AK		 4942008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
495
496 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
497 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
498 (s390_crb_extensions): New extensions table.
499 (insertExpandedMnemonic): Handle '$' tag.
500 * s390-opc.txt: Remove conditional jump variants which can now
501 be expanded automatically.
502 Replace '*' tag with '$' in the compare and branch instructions.
503
06c8514a
L		 5042008-04-07 H.J. Lu <hongjiu.lu@intel.com>
505
506 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
507 (PREFIX_VEX_3AXX): Likewis.
508
b122c285
L		 5092008-04-07 H.J. Lu <hongjiu.lu@intel.com>
510
511 * i386-opc.tbl: Remove 4 extra blank lines.
512
594ab6a3
L		 5132008-04-04 H.J. Lu <hongjiu.lu@intel.com>
514
515 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
516 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
517 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
518 * i386-opc.tbl: Likewise.
519
520 * i386-opc.h (CpuCLMUL): Renamed to ...
521 (CpuPCLMUL): This.
522 (CpuFMA): Updated.
523 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
524
525 * i386-init.h: Regenerated.
526
c0f3af97
L		 5272008-04-03 H.J. Lu <hongjiu.lu@intel.com>
528
529 * i386-dis.c (OP_E_register): New.
530 (OP_E_memory): Likewise.
531 (OP_VEX): Likewise.
532 (OP_EX_Vex): Likewise.
533 (OP_EX_VexW): Likewise.
534 (OP_XMM_Vex): Likewise.
535 (OP_XMM_VexW): Likewise.
536 (OP_REG_VexI4): Likewise.
537 (PCLMUL_Fixup): Likewise.
538 (VEXI4_Fixup): Likewise.
539 (VZERO_Fixup): Likewise.
540 (VCMP_Fixup): Likewise.
541 (VPERMIL2_Fixup): Likewise.
542 (rex_original): Likewise.
543 (rex_ignored): Likewise.
544 (Mxmm): Likewise.
545 (XMM): Likewise.
546 (EXxmm): Likewise.
547 (EXxmmq): Likewise.
548 (EXymmq): Likewise.
549 (Vex): Likewise.
550 (Vex128): Likewise.
551 (Vex256): Likewise.
552 (VexI4): Likewise.
553 (EXdVex): Likewise.
554 (EXqVex): Likewise.
555 (EXVexW): Likewise.
556 (EXdVexW): Likewise.
557 (EXqVexW): Likewise.
558 (XMVex): Likewise.
559 (XMVexW): Likewise.
560 (XMVexI4): Likewise.
561 (PCLMUL): Likewise.
562 (VZERO): Likewise.
563 (VCMP): Likewise.
564 (VPERMIL2): Likewise.
565 (xmm_mode): Likewise.
566 (xmmq_mode): Likewise.
567 (ymmq_mode): Likewise.
568 (vex_mode): Likewise.
569 (vex128_mode): Likewise.
570 (vex256_mode): Likewise.
571 (USE_VEX_C4_TABLE): Likewise.
572 (USE_VEX_C5_TABLE): Likewise.
573 (USE_VEX_LEN_TABLE): Likewise.
574 (VEX_C4_TABLE): Likewise.
575 (VEX_C5_TABLE): Likewise.
576 (VEX_LEN_TABLE): Likewise.
577 (REG_VEX_XX): Likewise.
578 (MOD_VEX_XXX): Likewise.
579 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
580 (PREFIX_0F3A44): Likewise.
581 (PREFIX_0F3ADF): Likewise.
582 (PREFIX_VEX_XXX): Likewise.
583 (VEX_OF): Likewise.
584 (VEX_OF38): Likewise.
585 (VEX_OF3A): Likewise.
586 (VEX_LEN_XXX): Likewise.
587 (vex): Likewise.
588 (need_vex): Likewise.
589 (need_vex_reg): Likewise.
590 (vex_i4_done): Likewise.
591 (vex_table): Likewise.
592 (vex_len_table): Likewise.
593 (OP_REG_VexI4): Likewise.
594 (vex_cmp_op): Likewise.
595 (pclmul_op): Likewise.
596 (vpermil2_op): Likewise.
597 (m_mode): Updated.
598 (es_reg): Likewise.
599 (PREFIX_0F38F0): Likewise.
600 (PREFIX_0F3A60): Likewise.
601 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
602 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
603 and PREFIX_VEX_XXX entries.
604 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
605 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
606 PREFIX_0F3ADF.
607 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
608 Add MOD_VEX_XXX entries.
609 (ckprefix): Initialize rex_original and rex_ignored. Store the
610 REX byte in rex_original.
611 (get_valid_dis386): Handle the implicit prefix in VEX prefix
612 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
613 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
614 calling get_valid_dis386. Use rex_original and rex_ignored when
615 printing out REX.
616 (putop): Handle "XY".
617 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
618 ymmq_mode.
619 (OP_E_extended): Updated to use OP_E_register and
620 OP_E_memory.
621 (OP_XMM): Handle VEX.
622 (OP_EX): Likewise.
623 (XMM_Fixup): Likewise.
624 (CMP_Fixup): Use ARRAY_SIZE.
625
626 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
627 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
628 (operand_type_init): Add OPERAND_TYPE_REGYMM and
629 OPERAND_TYPE_VEX_IMM4.
630 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
631 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
632 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
633 VexImmExt and SSE2AVX.
634 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
635
636 * i386-opc.h (CpuAVX): New.
637 (CpuAES): Likewise.
638 (CpuCLMUL): Likewise.
639 (CpuFMA): Likewise.
640 (Vex): Likewise.
641 (Vex256): Likewise.
642 (VexNDS): Likewise.
643 (VexNDD): Likewise.
644 (VexW0): Likewise.
645 (VexW1): Likewise.
646 (Vex0F): Likewise.
647 (Vex0F38): Likewise.
648 (Vex0F3A): Likewise.
649 (Vex3Sources): Likewise.
650 (VexImmExt): Likewise.
651 (SSE2AVX): Likewise.
652 (RegYMM): Likewise.
653 (Ymmword): Likewise.
654 (Vex_Imm4): Likewise.
655 (Implicit1stXmm0): Likewise.
656 (CpuXsave): Updated.
657 (CpuLM): Likewise.
658 (ByteOkIntel): Likewise.
659 (OldGcc): Likewise.
660 (Control): Likewise.
661 (Unspecified): Likewise.
662 (OTMax): Likewise.
663 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
664 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
665 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
666 vex3sources, veximmext and sse2avx.
667 (i386_operand_type): Add regymm, ymmword and vex_imm4.
668
669 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
670
671 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
672
673 * i386-init.h: Regenerated.
674 * i386-tbl.h: Likewise.
675
b21c9cb4
BS		 6762008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
677
678 From Robin Getz <robin.getz@analog.com>
679 * bfin-dis.c (bu32): Typedef.
680 (enum const_forms_t): Add c_uimm32 and c_huimm32.
681 (constant_formats[]): Add uimm32 and huimm16.
682 (fmtconst_val): New.
683 (uimm32): Define.
684 (huimm32): Define.
685 (imm16_val): Define.
686 (luimm16_val): Define.
687 (struct saved_state): Define.
688 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
689 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
690 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
691 (get_allreg): New.
692 (decode_LDIMMhalf_0): Print out the whole register value.
693
ee171c8f
BS		 694 From Jie Zhang <jie.zhang@analog.com>
695 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
696 multiply and multiply-accumulate to data register instruction.
697
086134ec
BS		 698 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
699 c_imm32, c_huimm32e): Define.
700 (constant_formats): Add flags for printing decimal, leading spaces, and
701 exact symbols.
702 (comment, parallel): Add global flags in all disassembly.
703 (fmtconst): Take advantage of new flags, and print default in hex.
704 (fmtconst_val): Likewise.
705 (decode_macfunc): Be consistant with spaces, tabs, comments,
706 capitalization in disassembly, fix minor coding style issues.
707 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
708 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
709 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
710 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
711 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
712 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
713 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
714 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
715 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
716 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
717 _print_insn_bfin, print_insn_bfin): Likewise.
718
58c85be7
RW		 7192008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
720
721 * aclocal.m4: Regenerate.
722 * configure: Likewise.
723 * Makefile.in: Likewise.
724
50e7d84b
AM		 7252008-03-13 Alan Modra <amodra@bigpond.net.au>
726
727 * Makefile.am: Run "make dep-am".
728 * Makefile.in: Regenerate.
729 * configure: Regenerate.
730
de866fcc
AM		 7312008-03-07 Alan Modra <amodra@bigpond.net.au>
732
733 * ppc-opc.c (powerpc_opcodes): Order and format.
734
28dbc079
L		 7352008-03-01 H.J. Lu <hongjiu.lu@intel.com>
736
737 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
738 * i386-tbl.h: Regenerated.
739
849830bd
L		 7402008-02-23 H.J. Lu <hongjiu.lu@intel.com>
741
742 * i386-opc.tbl: Disallow 16-bit near indirect branches for
743 x86-64.
744 * i386-tbl.h: Regenerated.
745
743ddb6b
JB		 7462008-02-21 Jan Beulich <jbeulich@novell.com>
747
748 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
749 and Fword for far indirect jmp. Allow Reg16 and Word for near
750 indirect jmp on x86-64. Disallow Fword for lcall.
751 * i386-tbl.h: Re-generate.
752
796d5313
NC		 7532008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
754
755 * cr16-opc.c (cr16_num_optab): Defined
756
65da13b5
L		 7572008-02-16 H.J. Lu <hongjiu.lu@intel.com>
758
759 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
760 * i386-init.h: Regenerated.
761
0e336180
NC		 7622008-02-14 Nick Clifton <nickc@redhat.com>
763
764 PR binutils/5524
765 * configure.in (SHARED_LIBADD): Select the correct host specific
766 file extension for shared libraries.
767 * configure: Regenerate.
768
b7240065
JB		 7692008-02-13 Jan Beulich <jbeulich@novell.com>
770
771 * i386-opc.h (RegFlat): New.
772 * i386-reg.tbl (flat): Add.
773 * i386-tbl.h: Re-generate.
774
34b772a6
JB		 7752008-02-13 Jan Beulich <jbeulich@novell.com>
776
777 * i386-dis.c (a_mode): New.
778 (cond_jump_mode): Adjust.
779 (Ma): Change to a_mode.
780 (intel_operand_size): Handle a_mode.
781 * i386-opc.tbl: Allow Dword and Qword for bound.
782 * i386-tbl.h: Re-generate.
783
a60de03c
JB		 7842008-02-13 Jan Beulich <jbeulich@novell.com>
785
786 * i386-gen.c (process_i386_registers): Process new fields.
787 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
788 unsigned char. Add dw2_regnum and Dw2Inval.
789 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
790 register names.
791 * i386-tbl.h: Re-generate.
792
f03fe4c1
L		 7932008-02-11 H.J. Lu <hongjiu.lu@intel.com>
794
4b6bc8eb 795 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 796 * i386-init.h: Updated.
797
475a2301
L		 7982008-02-11 H.J. Lu <hongjiu.lu@intel.com>
799
800 * i386-gen.c (cpu_flags): Add CpuXsave.
801
802 * i386-opc.h (CpuXsave): New.
4b6bc8eb 803 (CpuLM): Updated.
475a2301
L		 804 (i386_cpu_flags): Add cpuxsave.
805
806 * i386-dis.c (MOD_0FAE_REG_4): New.
807 (RM_0F01_REG_2): Likewise.
808 (MOD_0FAE_REG_5): Updated.
809 (RM_0F01_REG_3): Likewise.
810 (reg_table): Use MOD_0FAE_REG_4.
811 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
812 for xrstor.
813 (rm_table): Add RM_0F01_REG_2.
814
815 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
816 * i386-init.h: Regenerated.
817 * i386-tbl.h: Likewise.
818
595785c6 8192008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 820
595785c6
JB		 821 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
822 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
823 * i386-tbl.h: Re-generate.
824
bb8541b9
L		 8252008-02-04 H.J. Lu <hongjiu.lu@intel.com>
826
827 PR 5715
828 * configure: Regenerated.
829
57b592a3
AN		 8302008-02-04 Adam Nemet <anemet@caviumnetworks.com>
831
832 * mips-dis.c: Update copyright.
833 (mips_arch_choices): Add Octeon.
834 * mips-opc.c: Update copyright.
835 (IOCT): New macro.
836 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
837
930bb4cf
AM		 8382008-01-29 Alan Modra <amodra@bigpond.net.au>
839
840 * ppc-opc.c: Support optional L form mtmsr.
841
82c18208
L		 8422008-01-24 H.J. Lu <hongjiu.lu@intel.com>
843
844 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
845
599121aa
L		 8462008-01-23 H.J. Lu <hongjiu.lu@intel.com>
847
848 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
849 * i386-init.h: Regenerated.
850
80098f51
TG		 8512008-01-23 Tristan Gingold <gingold@adacore.com>
852
853 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
854 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
855
115c7c25
L		 8562008-01-22 H.J. Lu <hongjiu.lu@intel.com>
857
858 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
859 (cpu_flags): Likewise.
860
861 * i386-opc.h (CpuMMX2): Removed.
862 (CpuSSE): Updated.
863
864 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
865 * i386-init.h: Regenerated.
866 * i386-tbl.h: Likewise.
867
6305a203
L		 8682008-01-22 H.J. Lu <hongjiu.lu@intel.com>
869
870 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
871 CPU_SMX_FLAGS.
872 * i386-init.h: Regenerated.
873
fd07a1c8
L		 8742008-01-15 H.J. Lu <hongjiu.lu@intel.com>
875
876 * i386-opc.tbl: Use Qword on movddup.
877 * i386-tbl.h: Regenerated.
878
321fd21e
L		 8792008-01-15 H.J. Lu <hongjiu.lu@intel.com>
880
881 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
882 * i386-tbl.h: Regenerated.
883
4ee52178
L		 8842008-01-15 H.J. Lu <hongjiu.lu@intel.com>
885
886 * i386-dis.c (Mx): New.
887 (PREFIX_0FC3): Likewise.
888 (PREFIX_0FC7_REG_6): Updated.
889 (dis386_twobyte): Use PREFIX_0FC3.
890 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
891 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
892 movntss.
893
5c07affc
L		 8942008-01-14 H.J. Lu <hongjiu.lu@intel.com>
895
896 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
897 (operand_types): Add Mem.
898
899 * i386-opc.h (IntelSyntax): New.
900 * i386-opc.h (Mem): New.
901 (Byte): Updated.
902 (Opcode_Modifier_Max): Updated.
903 (i386_opcode_modifier): Add intelsyntax.
904 (i386_operand_type): Add mem.
905
906 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
907 instructions.
908
909 * i386-reg.tbl: Add size for accumulator.
910
911 * i386-init.h: Regenerated.
912 * i386-tbl.h: Likewise.
913
0d6a2f58
L		 9142008-01-13 H.J. Lu <hongjiu.lu@intel.com>
915
916 * i386-opc.h (Byte): Fix a typo.
917
7d5e4556
L		 9182008-01-12 H.J. Lu <hongjiu.lu@intel.com>
919
920 PR gas/5534
921 * i386-gen.c (operand_type_init): Add Dword to
922 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
923 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
924 Qword and Xmmword.
925 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
926 Xmmword, Unspecified and Anysize.
927 (set_bitfield): Make Mmword an alias of Qword. Make Oword
928 an alias of Xmmword.
929
930 * i386-opc.h (CheckSize): Removed.
931 (Byte): Updated.
932 (Word): Likewise.
933 (Dword): Likewise.
934 (Qword): Likewise.
935 (Xmmword): Likewise.
936 (FWait): Updated.
937 (OTMax): Likewise.
938 (i386_opcode_modifier): Remove checksize, byte, word, dword,
939 qword and xmmword.
940 (Fword): New.
941 (TBYTE): Likewise.
942 (Unspecified): Likewise.
943 (Anysize): Likewise.
944 (i386_operand_type): Add byte, word, dword, fword, qword,
945 tbyte xmmword, unspecified and anysize.
946
947 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
948 Tbyte, Xmmword, Unspecified and Anysize.
949
950 * i386-reg.tbl: Add size for accumulator.
951
952 * i386-init.h: Regenerated.
953 * i386-tbl.h: Likewise.
954
b5b1fc4f
L		 9552008-01-10 H.J. Lu <hongjiu.lu@intel.com>
956
957 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
958 (REG_0F18): Updated.
959 (reg_table): Updated.
960 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
961 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
962
50e8458f
L		 9632008-01-08 H.J. Lu <hongjiu.lu@intel.com>
964
965 * i386-gen.c (set_bitfield): Use fail () on error.
966
3d4d5afa
L		 9672008-01-08 H.J. Lu <hongjiu.lu@intel.com>
968
969 * i386-gen.c (lineno): New.
970 (filename): Likewise.
971 (set_bitfield): Report filename and line numer on error.
972 (process_i386_opcodes): Set filename and update lineno.
973 (process_i386_registers): Likewise.
974
e1d4d893
L		 9752008-01-05 H.J. Lu <hongjiu.lu@intel.com>
976
977 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
978 ATTSyntax.
979
980 * i386-opc.h (IntelMnemonic): Renamed to ..
981 (ATTSyntax): This
982 (Opcode_Modifier_Max): Updated.
983 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
984 and intelsyntax.
985
8944f3c2 986 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 987 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
988 * i386-tbl.h: Regenerated.
989
6f143e4d
L		 9902008-01-04 H.J. Lu <hongjiu.lu@intel.com>
991
992 * i386-gen.c: Update copyright to 2008.
993 * i386-opc.h: Likewise.
994 * i386-opc.tbl: Likewise.
995
996 * i386-init.h: Regenerated.
997 * i386-tbl.h: Likewise.
998
c6add537
L		 9992008-01-04 H.J. Lu <hongjiu.lu@intel.com>
1000
1001 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
1002 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
1003 * i386-tbl.h: Regenerated.
1004
3629bb00
L		 10052008-01-03 H.J. Lu <hongjiu.lu@intel.com>
1006
1007 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
1008 CpuSSE4_2_Or_ABM.
1009 (cpu_flags): Likewise.
1010
1011 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
1012 (CpuSSE4_2_Or_ABM): Likewise.
1013 (CpuLM): Updated.
1014 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
1015
1016 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
1017 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
1018 and CpuPadLock, respectively.
1019 * i386-init.h: Regenerated.
1020 * i386-tbl.h: Likewise.
1021
24995bd6
L		 10222008-01-03 H.J. Lu <hongjiu.lu@intel.com>
1023
1024 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
1025
1026 * i386-opc.h (No_xSuf): Removed.
1027 (CheckSize): Updated.
1028
1029 * i386-tbl.h: Regenerated.
1030
e0329a22
L		 10312008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1032
1033 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
1034 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
1035 CPU_SSE5_FLAGS.
1036 (cpu_flags): Add CpuSSE4_2_Or_ABM.
1037
1038 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
1039 (CpuLM): Updated.
1040 (i386_cpu_flags): Add cpusse4_2_or_abm.
1041
1042 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
1043 CpuABM|CpuSSE4_2 on popcnt.
1044 * i386-init.h: Regenerated.
1045 * i386-tbl.h: Likewise.
1046
f2a9c676
L		 10472008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1048
1049 * i386-opc.h: Update comments.
1050
d978b5be
L		 10512008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1052
1053 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
1054 * i386-opc.h: Likewise.
1055 * i386-opc.tbl: Likewise.
1056
582d5edd
L		 10572008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1058
1059 PR gas/5534
1060 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
1061 Byte, Word, Dword, QWord and Xmmword.
1062
1063 * i386-opc.h (No_xSuf): New.
1064 (CheckSize): Likewise.
1065 (Byte): Likewise.
1066 (Word): Likewise.
1067 (Dword): Likewise.
1068 (QWord): Likewise.
1069 (Xmmword): Likewise.
1070 (FWait): Updated.
1071 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
1072 Dword, QWord and Xmmword.
1073
1074 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
1075 used.
1076 * i386-tbl.h: Regenerated.
1077
3fe15143
MK		 10782008-01-02 Mark Kettenis <kettenis@gnu.org>
1079
1080 * m88k-dis.c (instructions): Fix fcvt.* instructions.
1081 From Miod Vallat.
1082
6c7ac64e 1083For older changes see ChangeLog-2007
252b5132
RH		 1084\f
1085Local Variables:
2f6d2f85
NC		 1086mode: change-log
1087left-margin: 8
1088fill-column: 74
252b5132
RH		 1089version-control: never
1090End:
GDB Binutils - Deliverables
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