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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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b5b098c2
JB		 12020-07-06 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
4 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
5 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
6 VEX_W_0FXOP_09_83): New enumerators.
7 (xop_table): Reference the above.
8 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
9 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
10 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
11 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
12
21a3faeb
JB		 132020-07-06 Jan Beulich <jbeulich@suse.com>
14
15 * i386-dis.c (EVEX_W_0F3838_P_1,
16 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
17 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
18 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
19 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
20 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
21 (putop): Centralize management of last[]. Delete SAVE_LAST.
22 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
23 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
24 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
25 * i386-dis-evex-prefix.h: here.
26
bc152a17
JB		 272020-07-06 Jan Beulich <jbeulich@suse.com>
28
29 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
30 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
31 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
32 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
33 enumerators.
34 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
35 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
36 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
37 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
38 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
39 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
40 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
41 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
42 these, respectively.
43 * i386-dis-evex-len.h: Adjust comments.
44 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
45 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
46 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
47 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
48 MOD_EVEX_0F385B_P_2_W_1 table entries.
49 * i386-dis-evex-w.h: Reference mod_table[] for
50 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
51 EVEX_W_0F385B_P_2.
52
c82a99a0
JB		 532020-07-06 Jan Beulich <jbeulich@suse.com>
54
55 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
56 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
57 EXymm.
58 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
59 Likewise. Mark 256-bit entries invalid.
60
fedfb81e
JB		 612020-07-06 Jan Beulich <jbeulich@suse.com>
62
63 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
64 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
65 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
66 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
67 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
68 PREFIX_EVEX_0F382B): Delete.
69 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
70 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
71 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
72 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
73 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
74 to ...
75 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
76 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
77 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
78 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
79 respectively.
80 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
81 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
82 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
83 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
84 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
85 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
86 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
87 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
88 PREFIX_EVEX_0F382B): Remove table entries.
89 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
90 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
91 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
92
3a57774c
JB		 932020-07-06 Jan Beulich <jbeulich@suse.com>
94
95 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
96 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
97 enumerators.
98 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
99 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
100 EVEX_LEN_0F3A01_P_2_W_1 table entries.
101 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
102 entries.
103
e74d9fa9
JB		 1042020-07-06 Jan Beulich <jbeulich@suse.com>
105
106 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
107 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
108 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
109 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
110 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
111 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
112 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
113 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
114 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
115 entries.
116
6431c801
JB		 1172020-07-06 Jan Beulich <jbeulich@suse.com>
118
119 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
120 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
121 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
122 respectively.
123 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
124 entries.
125 * i386-dis-evex.h (evex_table): Reference VEX table entry for
126 opcode 0F3A1D.
127 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
128 entry.
129 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
130
6df22cf6
JB		 1312020-07-06 Jan Beulich <jbeulich@suse.com>
132
133 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
134 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
135 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
136 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
137 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
138 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
139 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
140 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
141 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
142 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
143 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
144 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
145 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
146 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
147 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
148 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
149 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
150 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
151 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
152 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
153 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
154 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
155 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
156 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
157 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
158 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
159 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
160 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
161 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
162 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
163 (prefix_table): Add EXxEVexR to FMA table entries.
164 (OP_Rounding): Move abort() invocation.
165 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
166 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
167 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
168 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
169 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
170 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
171 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
172 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
173 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
174 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
175 0F3ACE, 0F3ACF.
176 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
177 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
178 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
179 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
180 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
181 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
182 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
183 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
184 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
185 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
186 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
187 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
188 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
189 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
190 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
191 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
192 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
193 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
194 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
195 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
196 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
197 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
198 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
199 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
200 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
201 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
202 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
203 Delete table entries.
204 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
205 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
206 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
207 Likewise.
208
39e0f456
JB		 2092020-07-06 Jan Beulich <jbeulich@suse.com>
210
211 * i386-dis.c (EXqScalarS): Delete.
212 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
213 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
214
5b872f7d
JB		 2152020-07-06 Jan Beulich <jbeulich@suse.com>
216
217 * i386-dis.c (safe-ctype.h): Include.
218 (EXdScalar, EXqScalar): Delete.
219 (d_scalar_mode, q_scalar_mode): Delete.
220 (prefix_table, vex_len_table): Use EXxmm_md in place of
221 EXdScalar and EXxmm_mq in place of EXqScalar.
222 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
223 d_scalar_mode and q_scalar_mode.
224 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
225 (vmovsd): Use EXxmm_mq.
226
ddc73fa9
NC		 2272020-07-06 Yuri Chornoivan <yurchor@ukr.net>
228
229 PR 26204
230 * arc-dis.c: Fix spelling mistake.
231 * po/opcodes.pot: Regenerate.
232
17550be7
NC		 2332020-07-06 Nick Clifton <nickc@redhat.com>
234
235 * po/pt_BR.po: Updated Brazilian Portugugese translation.
236 * po/uk.po: Updated Ukranian translation.
237
b19d852d
NC		 2382020-07-04 Nick Clifton <nickc@redhat.com>
239
240 * configure: Regenerate.
241 * po/opcodes.pot: Regenerate.
242
b115b9fd
NC		 2432020-07-04 Nick Clifton <nickc@redhat.com>
244
245 Binutils 2.35 branch created.
246
c2ecccb3
L		 2472020-07-02 H.J. Lu <hongjiu.lu@intel.com>
248
249 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
250 * i386-opc.h (VexSwapSources): New.
251 (i386_opcode_modifier): Add vexswapsources.
252 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
253 with two source operands swapped.
254 * i386-tbl.h: Regenerated.
255
08ccfccf
NC		 2562020-06-30 Nelson Chu <nelson.chu@sifive.com>
257
258 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
259 unprivileged CSR can also be initialized.
260
279edac5
AM		 2612020-06-29 Alan Modra <amodra@gmail.com>
262
263 * arm-dis.c: Use C style comments.
264 * cr16-opc.c: Likewise.
265 * ft32-dis.c: Likewise.
266 * moxie-opc.c: Likewise.
267 * tic54x-dis.c: Likewise.
268 * s12z-opc.c: Remove useless comment.
269 * xgate-dis.c: Likewise.
270
e978ad62
L		 2712020-06-26 H.J. Lu <hongjiu.lu@intel.com>
272
273 * i386-opc.tbl: Add a blank line.
274
63112cd6
L		 2752020-06-26 H.J. Lu <hongjiu.lu@intel.com>
276
277 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
278 (VecSIB128): Renamed to ...
279 (VECSIB128): This.
280 (VecSIB256): Renamed to ...
281 (VECSIB256): This.
282 (VecSIB512): Renamed to ...
283 (VECSIB512): This.
284 (VecSIB): Renamed to ...
285 (SIB): This.
286 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 287 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 288 (VecSIB256): Likewise.
289 (VecSIB512): Likewise.
79b32e73 290 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 291 and VecSIB512, respectively.
292
d1c36125
JB		 2932020-06-26 Jan Beulich <jbeulich@suse.com>
294
295 * i386-dis.c: Adjust description of I macro.
296 (x86_64_table): Drop use of I.
297 (float_mem): Replace use of I.
298 (putop): Remove handling of I. Adjust setting/clearing of "alt".
299
2a1bb84c
JB		 3002020-06-26 Jan Beulich <jbeulich@suse.com>
301
302 * i386-dis.c: (print_insn): Avoid straight assignment to
303 priv.orig_sizeflag when processing -M sub-options.
304
8f570d62
JB		 3052020-06-25 Jan Beulich <jbeulich@suse.com>
306
307 * i386-dis.c: Adjust description of J macro.
308 (dis386, x86_64_table, mod_table): Replace J.
309 (putop): Remove handling of J.
310
464dc4af
JB		 3112020-06-25 Jan Beulich <jbeulich@suse.com>
312
313 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
314
589958d6
JB		 3152020-06-25 Jan Beulich <jbeulich@suse.com>
316
317 * i386-dis.c: Adjust description of "LQ" macro.
318 (dis386_twobyte): Use LQ for sysret.
319 (putop): Adjust handling of LQ.
320
39ff0b81
NC		 3212020-06-22 Nelson Chu <nelson.chu@sifive.com>
322
323 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
324 * riscv-dis.c: Include elfxx-riscv.h.
325
d27c357a
JB		 3262020-06-18 H.J. Lu <hongjiu.lu@intel.com>
327
328 * i386-dis.c (prefix_table): Revert the last vmgexit change.
329
6fde587f
CL		 3302020-06-17 Lili Cui <lili.cui@intel.com>
331
332 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
333
efe30057
L		 3342020-06-14 H.J. Lu <hongjiu.lu@intel.com>
335
336 PR gas/26115
337 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
338 * i386-opc.tbl: Likewise.
339 * i386-tbl.h: Regenerated.
340
d8af286f
NC		 3412020-06-12 Nelson Chu <nelson.chu@sifive.com>
342
343 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
344
14962256
AC		 3452020-06-11 Alex Coplan <alex.coplan@arm.com>
346
347 * aarch64-opc.c (SYSREG): New macro for describing system registers.
348 (SR_CORE): Likewise.
349 (SR_FEAT): Likewise.
350 (SR_RNG): Likewise.
351 (SR_V8_1): Likewise.
352 (SR_V8_2): Likewise.
353 (SR_V8_3): Likewise.
354 (SR_V8_4): Likewise.
355 (SR_PAN): Likewise.
356 (SR_RAS): Likewise.
357 (SR_SSBS): Likewise.
358 (SR_SVE): Likewise.
359 (SR_ID_PFR2): Likewise.
360 (SR_PROFILE): Likewise.
361 (SR_MEMTAG): Likewise.
362 (SR_SCXTNUM): Likewise.
363 (aarch64_sys_regs): Refactor to store feature information in the table.
364 (aarch64_sys_reg_supported_p): Collapse logic for system registers
365 that now describe their own features.
366 (aarch64_pstatefield_supported_p): Likewise.
367
f9630fa6
L		 3682020-06-09 H.J. Lu <hongjiu.lu@intel.com>
369
370 * i386-dis.c (prefix_table): Fix a typo in comments.
371
73239888
JB		 3722020-06-09 Jan Beulich <jbeulich@suse.com>
373
374 * i386-dis.c (rex_ignored): Delete.
375 (ckprefix): Drop rex_ignored initialization.
376 (get_valid_dis386): Drop setting of rex_ignored.
377 (print_insn): Drop checking of rex_ignored. Don't record data
378 size prefix as used with VEX-and-alike encodings.
379
18897deb
JB		 3802020-06-09 Jan Beulich <jbeulich@suse.com>
381
382 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
383 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
384 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
385 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
386 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
387 VEX_0F12, and VEX_0F16.
388 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
389 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
390 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
391 from movlps and movhlps. New MOD_0F12_PREFIX_2,
392 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
393 MOD_VEX_0F16_PREFIX_2 entries.
394
97e6786a
JB		 3952020-06-09 Jan Beulich <jbeulich@suse.com>
396
397 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
398 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
399 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
400 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
401 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
402 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
403 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
404 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
405 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
406 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
407 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
408 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
409 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
410 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
411 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
412 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
413 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
414 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
415 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
416 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
417 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
418 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
419 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
420 EVEX_W_0FC6_P_2): Delete.
421 (print_insn): Add EVEX.W vs embedded prefix consistency check
422 to prefix validation.
423 * i386-dis-evex.h (evex_table): Don't further descend for
424 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
425 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
426 and 0F2B.
427 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
428 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
429 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
430 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
431 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
432 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
433 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
434 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
435 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
436 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
437 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
438 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
439 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
440 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
441 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
442 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
443 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
444 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
445 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
446 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
447 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
448 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
449 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
450 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
451 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
452 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
453 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
454
bf926894
JB		 4552020-06-09 Jan Beulich <jbeulich@suse.com>
456
457 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
458 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
459 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
460 vmovmskpX.
461 (print_insn): Drop pointless check against bad_opcode. Split
462 prefix validation into legacy and VEX-and-alike parts.
463 (putop): Re-work 'X' macro handling.
464
a5aaedb9
JB		 4652020-06-09 Jan Beulich <jbeulich@suse.com>
466
467 * i386-dis.c (MOD_0F51): Rename to ...
468 (MOD_0F50): ... this.
469
26417f19
AC		 4702020-06-08 Alex Coplan <alex.coplan@arm.com>
471
472 * arm-dis.c (arm_opcodes): Add dfb.
473 (thumb32_opcodes): Add dfb.
474
8a6fb3f9
JB		 4752020-06-08 Jan Beulich <jbeulich@suse.com>
476
477 * i386-opc.h (reg_entry): Const-qualify reg_name field.
478
1424c35d
AM		 4792020-06-06 Alan Modra <amodra@gmail.com>
480
481 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
482
d3d1cc7b
AM		 4832020-06-05 Alan Modra <amodra@gmail.com>
484
485 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
486 size is large enough.
487
d8740be1
JM		 4882020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
489
490 * disassemble.c (disassemble_init_for_target): Set endian_code for
491 bpf targets.
492 * bpf-desc.c: Regenerate.
493 * bpf-opc.c: Likewise.
494 * bpf-dis.c: Likewise.
495
e9bffec9
JM		 4962020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
497
498 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
499 (cgen_put_insn_value): Likewise.
500 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
501 * cgen-dis.in (print_insn): Likewise.
502 * cgen-ibld.in (insert_1): Likewise.
503 (insert_1): Likewise.
504 (insert_insn_normal): Likewise.
505 (extract_1): Likewise.
506 * bpf-dis.c: Regenerate.
507 * bpf-ibld.c: Likewise.
508 * bpf-ibld.c: Likewise.
509 * cgen-dis.in: Likewise.
510 * cgen-ibld.in: Likewise.
511 * cgen-opc.c: Likewise.
512 * epiphany-dis.c: Likewise.
513 * epiphany-ibld.c: Likewise.
514 * fr30-dis.c: Likewise.
515 * fr30-ibld.c: Likewise.
516 * frv-dis.c: Likewise.
517 * frv-ibld.c: Likewise.
518 * ip2k-dis.c: Likewise.
519 * ip2k-ibld.c: Likewise.
520 * iq2000-dis.c: Likewise.
521 * iq2000-ibld.c: Likewise.
522 * lm32-dis.c: Likewise.
523 * lm32-ibld.c: Likewise.
524 * m32c-dis.c: Likewise.
525 * m32c-ibld.c: Likewise.
526 * m32r-dis.c: Likewise.
527 * m32r-ibld.c: Likewise.
528 * mep-dis.c: Likewise.
529 * mep-ibld.c: Likewise.
530 * mt-dis.c: Likewise.
531 * mt-ibld.c: Likewise.
532 * or1k-dis.c: Likewise.
533 * or1k-ibld.c: Likewise.
534 * xc16x-dis.c: Likewise.
535 * xc16x-ibld.c: Likewise.
536 * xstormy16-dis.c: Likewise.
537 * xstormy16-ibld.c: Likewise.
538
b3db6d07
JM		 5392020-06-04 Jose E. Marchesi <jemarch@gnu.org>
540
541 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
542 (print_insn_): Handle instruction endian.
543 * bpf-dis.c: Regenerate.
544 * bpf-desc.c: Regenerate.
545 * epiphany-dis.c: Likewise.
546 * epiphany-desc.c: Likewise.
547 * fr30-dis.c: Likewise.
548 * fr30-desc.c: Likewise.
549 * frv-dis.c: Likewise.
550 * frv-desc.c: Likewise.
551 * ip2k-dis.c: Likewise.
552 * ip2k-desc.c: Likewise.
553 * iq2000-dis.c: Likewise.
554 * iq2000-desc.c: Likewise.
555 * lm32-dis.c: Likewise.
556 * lm32-desc.c: Likewise.
557 * m32c-dis.c: Likewise.
558 * m32c-desc.c: Likewise.
559 * m32r-dis.c: Likewise.
560 * m32r-desc.c: Likewise.
561 * mep-dis.c: Likewise.
562 * mep-desc.c: Likewise.
563 * mt-dis.c: Likewise.
564 * mt-desc.c: Likewise.
565 * or1k-dis.c: Likewise.
566 * or1k-desc.c: Likewise.
567 * xc16x-dis.c: Likewise.
568 * xc16x-desc.c: Likewise.
569 * xstormy16-dis.c: Likewise.
570 * xstormy16-desc.c: Likewise.
571
4ee4189f
NC		 5722020-06-03 Nick Clifton <nickc@redhat.com>
573
574 * po/sr.po: Updated Serbian translation.
575
44730156
NC		 5762020-06-03 Nelson Chu <nelson.chu@sifive.com>
577
578 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
579 (riscv_get_priv_spec_class): Likewise.
580
3c3d0376
AM		 5812020-06-01 Alan Modra <amodra@gmail.com>
582
583 * bpf-desc.c: Regenerate.
584
78c1c354
JM		 5852020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
586 David Faust <david.faust@oracle.com>
587
588 * bpf-desc.c: Regenerate.
589 * bpf-opc.h: Likewise.
590 * bpf-opc.c: Likewise.
591 * bpf-dis.c: Likewise.
592
efcf5fb5
AM		 5932020-05-28 Alan Modra <amodra@gmail.com>
594
595 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
596 values.
597
ab382d64
AM		 5982020-05-28 Alan Modra <amodra@gmail.com>
599
600 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
601 immediates.
602 (print_insn_ns32k): Revert last change.
603
151f5de4
NC		 6042020-05-28 Nick Clifton <nickc@redhat.com>
605
606 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
607 static.
608
25e1eca8
SL		 6092020-05-26 Sandra Loosemore <sandra@codesourcery.com>
610
611 Fix extraction of signed constants in nios2 disassembler (again).
612
613 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
614 extractions of signed fields.
615
57b17940
SSF		 6162020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
617
618 * s390-opc.txt: Relocate vector load/store instructions with
619 additional alignment parameter and change architecture level
620 constraint from z14 to z13.
621
d96bf37b
AM		 6222020-05-21 Alan Modra <amodra@gmail.com>
623
624 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
625 * sparc-dis.c: Likewise.
626 * tic4x-dis.c: Likewise.
627 * xtensa-dis.c: Likewise.
628 * bpf-desc.c: Regenerate.
629 * epiphany-desc.c: Regenerate.
630 * fr30-desc.c: Regenerate.
631 * frv-desc.c: Regenerate.
632 * ip2k-desc.c: Regenerate.
633 * iq2000-desc.c: Regenerate.
634 * lm32-desc.c: Regenerate.
635 * m32c-desc.c: Regenerate.
636 * m32r-desc.c: Regenerate.
637 * mep-asm.c: Regenerate.
638 * mep-desc.c: Regenerate.
639 * mt-desc.c: Regenerate.
640 * or1k-desc.c: Regenerate.
641 * xc16x-desc.c: Regenerate.
642 * xstormy16-desc.c: Regenerate.
643
8f595e9b
NC		 6442020-05-20 Nelson Chu <nelson.chu@sifive.com>
645
646 * riscv-opc.c (riscv_ext_version_table): The table used to store
647 all information about the supported spec and the corresponding ISA
648 versions. Currently, only Zicsr is supported to verify the
649 correctness of Z sub extension settings. Others will be supported
650 in the future patches.
651 (struct isa_spec_t, isa_specs): List for all supported ISA spec
652 classes and the corresponding strings.
653 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
654 spec class by giving a ISA spec string.
655 * riscv-opc.c (struct priv_spec_t): New structure.
656 (struct priv_spec_t priv_specs): List for all supported privilege spec
657 classes and the corresponding strings.
658 (riscv_get_priv_spec_class): New function. Get the corresponding
659 privilege spec class by giving a spec string.
660 (riscv_get_priv_spec_name): New function. Get the corresponding
661 privilege spec string by giving a CSR version class.
662 * riscv-dis.c: Updated since DECLARE_CSR is changed.
663 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
664 according to the chosen version. Build a hash table riscv_csr_hash to
665 store the valid CSR for the chosen pirv verison. Dump the direct
666 CSR address rather than it's name if it is invalid.
667 (parse_riscv_dis_option_without_args): New function. Parse the options
668 without arguments.
669 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
670 parse the options without arguments first, and then handle the options
671 with arguments. Add the new option -Mpriv-spec, which has argument.
672 * riscv-dis.c (print_riscv_disassembler_options): Add description
673 about the new OBJDUMP option.
674
3d205eb4
PB		 6752020-05-19 Peter Bergner <bergner@linux.ibm.com>
676
677 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
678 WC values on POWER10 sync, dcbf and wait instructions.
679 (insert_pl, extract_pl): New functions.
680 (L2OPT, LS, WC): Use insert_ls and extract_ls.
681 (LS3): New , 3-bit L for sync.
682 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
683 (SC2, PL): New, 2-bit SC and PL for sync and wait.
684 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
685 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
686 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
687 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
688 <wait>: Enable PL operand on POWER10.
689 <dcbf>: Enable L3OPT operand on POWER10.
690 <sync>: Enable SC2 operand on POWER10.
691
a501eb44
SH		 6922020-05-19 Stafford Horne <shorne@gmail.com>
693
694 PR 25184
695 * or1k-asm.c: Regenerate.
696 * or1k-desc.c: Regenerate.
697 * or1k-desc.h: Regenerate.
698 * or1k-dis.c: Regenerate.
699 * or1k-ibld.c: Regenerate.
700 * or1k-opc.c: Regenerate.
701 * or1k-opc.h: Regenerate.
702 * or1k-opinst.c: Regenerate.
703
3b646889
AM		 7042020-05-11 Alan Modra <amodra@gmail.com>
705
706 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
707 xsmaxcqp, xsmincqp.
708
9cc4ce88
AM		 7092020-05-11 Alan Modra <amodra@gmail.com>
710
711 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
712 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
713
5d57bc3f
AM		 7142020-05-11 Alan Modra <amodra@gmail.com>
715
716 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
717
66ef5847
AM		 7182020-05-11 Alan Modra <amodra@gmail.com>
719
720 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
721 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
722
4f3e9537
PB		 7232020-05-11 Peter Bergner <bergner@linux.ibm.com>
724
725 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
726 mnemonics.
727
ec40e91c
AM		 7282020-05-11 Alan Modra <amodra@gmail.com>
729
730 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
731 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
732 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
733 (prefix_opcodes): Add xxeval.
734
d7e97a76
AM		 7352020-05-11 Alan Modra <amodra@gmail.com>
736
737 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
738 xxgenpcvwm, xxgenpcvdm.
739
fdefed7c
AM		 7402020-05-11 Alan Modra <amodra@gmail.com>
741
742 * ppc-opc.c (MP, VXVAM_MASK): Define.
743 (VXVAPS_MASK): Use VXVA_MASK.
744 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
745 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
746 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
747 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
748
aa3c112f
AM		 7492020-05-11 Alan Modra <amodra@gmail.com>
750 Peter Bergner <bergner@linux.ibm.com>
751
752 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
753 New functions.
754 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
755 YMSK2, XA6a, XA6ap, XB6a entries.
756 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
757 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
758 (PPCVSX4): Define.
759 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
760 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
761 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
762 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
763 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
764 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
765 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
766 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
767 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
768 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
769 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
770 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
771 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
772 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
773
6edbfd3b
AM		 7742020-05-11 Alan Modra <amodra@gmail.com>
775
776 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
777 (insert_xts, extract_xts): New functions.
778 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
779 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
780 (VXRC_MASK, VXSH_MASK): Define.
781 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
782 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
783 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
784 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
785 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
786 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
787 xxblendvh, xxblendvw, xxblendvd, xxpermx.
788
c7d7aea2
AM		 7892020-05-11 Alan Modra <amodra@gmail.com>
790
791 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
792 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
793 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
794 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
795 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
796
94ba9882
AM		 7972020-05-11 Alan Modra <amodra@gmail.com>
798
799 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
800 (XTP, DQXP, DQXP_MASK): Define.
801 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
802 (prefix_opcodes): Add plxvp and pstxvp.
803
f4791f1a
AM		 8042020-05-11 Alan Modra <amodra@gmail.com>
805
806 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
807 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
808 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
809
3ff0a5ba
PB		 8102020-05-11 Peter Bergner <bergner@linux.ibm.com>
811
812 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
813
afef4fe9
PB		 8142020-05-11 Peter Bergner <bergner@linux.ibm.com>
815
816 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
817 (L1OPT): Define.
818 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
819
1224c05d
PB		 8202020-05-11 Peter Bergner <bergner@linux.ibm.com>
821
822 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
823
6bbb0c05
AM		 8242020-05-11 Alan Modra <amodra@gmail.com>
825
826 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
827
7c1f4227
AM		 8282020-05-11 Alan Modra <amodra@gmail.com>
829
830 * ppc-dis.c (ppc_opts): Add "power10" entry.
831 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
832 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
833
73199c2b
NC		 8342020-05-11 Nick Clifton <nickc@redhat.com>
835
836 * po/fr.po: Updated French translation.
837
09c1e68a
AC		 8382020-04-30 Alex Coplan <alex.coplan@arm.com>
839
840 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
841 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
842 (operand_general_constraint_met_p): validate
843 AARCH64_OPND_UNDEFINED.
844 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
845 for FLD_imm16_2.
846 * aarch64-asm-2.c: Regenerated.
847 * aarch64-dis-2.c: Regenerated.
848 * aarch64-opc-2.c: Regenerated.
849
9654d51a
NC		 8502020-04-29 Nick Clifton <nickc@redhat.com>
851
852 PR 22699
853 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
854 and SETRC insns.
855
c2e71e57
NC		 8562020-04-29 Nick Clifton <nickc@redhat.com>
857
858 * po/sv.po: Updated Swedish translation.
859
5c936ef5
NC		 8602020-04-29 Nick Clifton <nickc@redhat.com>
861
862 PR 22699
863 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
864 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
865 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
866 IMM0_8U case.
867
bb2a1453
AS		 8682020-04-21 Andreas Schwab <schwab@linux-m68k.org>
869
870 PR 25848
871 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
872 cmpi only on m68020up and cpu32.
873
c2e5c986
SD		 8742020-04-20 Sudakshina Das <sudi.das@arm.com>
875
876 * aarch64-asm.c (aarch64_ins_none): New.
877 * aarch64-asm.h (ins_none): New declaration.
878 * aarch64-dis.c (aarch64_ext_none): New.
879 * aarch64-dis.h (ext_none): New declaration.
880 * aarch64-opc.c (aarch64_print_operand): Update case for
881 AARCH64_OPND_BARRIER_PSB.
882 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
883 (AARCH64_OPERANDS): Update inserter/extracter for
884 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
885 * aarch64-asm-2.c: Regenerated.
886 * aarch64-dis-2.c: Regenerated.
887 * aarch64-opc-2.c: Regenerated.
888
8a6e1d1d
SD		 8892020-04-20 Sudakshina Das <sudi.das@arm.com>
890
891 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
892 (aarch64_feature_ras, RAS): Likewise.
893 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
894 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
895 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
896 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
897 * aarch64-asm-2.c: Regenerated.
898 * aarch64-dis-2.c: Regenerated.
899 * aarch64-opc-2.c: Regenerated.
900
e409955d
FS		 9012020-04-17 Fredrik Strupe <fredrik@strupe.net>
902
903 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
904 (print_insn_neon): Support disassembly of conditional
905 instructions.
906
c54a9b56
DF		 9072020-02-16 David Faust <david.faust@oracle.com>
908
909 * bpf-desc.c: Regenerate.
910 * bpf-desc.h: Likewise.
911 * bpf-opc.c: Regenerate.
912 * bpf-opc.h: Likewise.
913
bb651e8b
CL		 9142020-04-07 Lili Cui <lili.cui@intel.com>
915
916 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
917 (prefix_table): New instructions (see prefixes above).
918 (rm_table): Likewise
919 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
920 CPU_ANY_TSXLDTRK_FLAGS.
921 (cpu_flags): Add CpuTSXLDTRK.
922 * i386-opc.h (enum): Add CpuTSXLDTRK.
923 (i386_cpu_flags): Add cputsxldtrk.
924 * i386-opc.tbl: Add XSUSPLDTRK insns.
925 * i386-init.h: Regenerate.
926 * i386-tbl.h: Likewise.
927
4b27d27c
L		 9282020-04-02 Lili Cui <lili.cui@intel.com>
929
930 * i386-dis.c (prefix_table): New instructions serialize.
931 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
932 CPU_ANY_SERIALIZE_FLAGS.
933 (cpu_flags): Add CpuSERIALIZE.
934 * i386-opc.h (enum): Add CpuSERIALIZE.
935 (i386_cpu_flags): Add cpuserialize.
936 * i386-opc.tbl: Add SERIALIZE insns.
937 * i386-init.h: Regenerate.
938 * i386-tbl.h: Likewise.
939
832a5807
AM		 9402020-03-26 Alan Modra <amodra@gmail.com>
941
942 * disassemble.h (opcodes_assert): Declare.
943 (OPCODES_ASSERT): Define.
944 * disassemble.c: Don't include assert.h. Include opintl.h.
945 (opcodes_assert): New function.
946 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
947 (bfd_h8_disassemble): Reduce size of data array. Correctly
948 calculate maxlen. Omit insn decoding when insn length exceeds
949 maxlen. Exit from nibble loop when looking for E, before
950 accessing next data byte. Move processing of E outside loop.
951 Replace tests of maxlen in loop with assertions.
952
4c4addbe
AM		 9532020-03-26 Alan Modra <amodra@gmail.com>
954
955 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
956
a18cd0ca
AM		 9572020-03-25 Alan Modra <amodra@gmail.com>
958
959 * z80-dis.c (suffix): Init mybuf.
960
57cb32b3
AM		 9612020-03-22 Alan Modra <amodra@gmail.com>
962
963 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
964 successflly read from section.
965
beea5cc1
AM		 9662020-03-22 Alan Modra <amodra@gmail.com>
967
968 * arc-dis.c (find_format): Use ISO C string concatenation rather
969 than line continuation within a string. Don't access needs_limm
970 before testing opcode != NULL.
971
03704c77
AM		 9722020-03-22 Alan Modra <amodra@gmail.com>
973
974 * ns32k-dis.c (print_insn_arg): Update comment.
975 (print_insn_ns32k): Reduce size of index_offset array, and
976 initialize, passing -1 to print_insn_arg for args that are not
977 an index. Don't exit arg loop early. Abort on bad arg number.
978
d1023b5d
AM		 9792020-03-22 Alan Modra <amodra@gmail.com>
980
981 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
982 * s12z-opc.c: Formatting.
983 (operands_f): Return an int.
984 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
985 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
986 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
987 (exg_sex_discrim): Likewise.
988 (create_immediate_operand, create_bitfield_operand),
989 (create_register_operand_with_size, create_register_all_operand),
990 (create_register_all16_operand, create_simple_memory_operand),
991 (create_memory_operand, create_memory_auto_operand): Don't
992 segfault on malloc failure.
993 (z_ext24_decode): Return an int status, negative on fail, zero
994 on success.
995 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
996 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
997 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
998 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
999 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1000 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1001 (loop_primitive_decode, shift_decode, psh_pul_decode),
1002 (bit_field_decode): Similarly.
1003 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1004 to return value, update callers.
1005 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1006 Don't segfault on NULL operand.
1007 (decode_operation): Return OP_INVALID on first fail.
1008 (decode_s12z): Check all reads, returning -1 on fail.
1009
340f3ac8
AM		 10102020-03-20 Alan Modra <amodra@gmail.com>
1011
1012 * metag-dis.c (print_insn_metag): Don't ignore status from
1013 read_memory_func.
1014
fe90ae8a
AM		 10152020-03-20 Alan Modra <amodra@gmail.com>
1016
1017 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1018 Initialize parts of buffer not written when handling a possible
1019 2-byte insn at end of section. Don't attempt decoding of such
1020 an insn by the 4-byte machinery.
1021
833d919c
AM		 10222020-03-20 Alan Modra <amodra@gmail.com>
1023
1024 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1025 partially filled buffer. Prevent lookup of 4-byte insns when
1026 only VLE 2-byte insns are possible due to section size. Print
1027 ".word" rather than ".long" for 2-byte leftovers.
1028
327ef784
NC		 10292020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1030
1031 PR 25641
1032 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1033
1673df32
JB		 10342020-03-13 Jan Beulich <jbeulich@suse.com>
1035
1036 * i386-dis.c (X86_64_0D): Rename to ...
1037 (X86_64_0E): ... this.
1038
384f3689
L		 10392020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1040
1041 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1042 * Makefile.in: Regenerated.
1043
865e2027
JB		 10442020-03-09 Jan Beulich <jbeulich@suse.com>
1045
1046 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1047 3-operand pseudos.
1048 * i386-tbl.h: Re-generate.
1049
2f13234b
JB		 10502020-03-09 Jan Beulich <jbeulich@suse.com>
1051
1052 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1053 vprot*, vpsha*, and vpshl*.
1054 * i386-tbl.h: Re-generate.
1055
3fabc179
JB		 10562020-03-09 Jan Beulich <jbeulich@suse.com>
1057
1058 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1059 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1060 * i386-tbl.h: Re-generate.
1061
3677e4c1
JB		 10622020-03-09 Jan Beulich <jbeulich@suse.com>
1063
1064 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1065 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1066 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1067 * i386-tbl.h: Re-generate.
1068
4c4898e8
JB		 10692020-03-09 Jan Beulich <jbeulich@suse.com>
1070
1071 * i386-gen.c (struct template_arg, struct template_instance,
1072 struct template_param, struct template, templates,
1073 parse_template, expand_templates): New.
1074 (process_i386_opcodes): Various local variables moved to
1075 expand_templates. Call parse_template and expand_templates.
1076 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1077 * i386-tbl.h: Re-generate.
1078
bc49bfd8
JB		 10792020-03-06 Jan Beulich <jbeulich@suse.com>
1080
1081 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1082 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1083 register and memory source templates. Replace VexW= by VexW*
1084 where applicable.
1085 * i386-tbl.h: Re-generate.
1086
4873e243
JB		 10872020-03-06 Jan Beulich <jbeulich@suse.com>
1088
1089 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1090 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1091 * i386-tbl.h: Re-generate.
1092
672a349b
JB		 10932020-03-06 Jan Beulich <jbeulich@suse.com>
1094
1095 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1096 * i386-tbl.h: Re-generate.
1097
4ed21b58
JB		 10982020-03-06 Jan Beulich <jbeulich@suse.com>
1099
1100 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1101 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1102 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1103 VexW0 on SSE2AVX variants.
1104 (vmovq): Drop NoRex64 from XMM/XMM variants.
1105 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1106 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1107 applicable use VexW0.
1108 * i386-tbl.h: Re-generate.
1109
643bb870
JB		 11102020-03-06 Jan Beulich <jbeulich@suse.com>
1111
1112 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1113 * i386-opc.h (Rex64): Delete.
1114 (struct i386_opcode_modifier): Remove rex64 field.
1115 * i386-opc.tbl (crc32): Drop Rex64.
1116 Replace Rex64 with Size64 everywhere else.
1117 * i386-tbl.h: Re-generate.
1118
a23b33b3
JB		 11192020-03-06 Jan Beulich <jbeulich@suse.com>
1120
1121 * i386-dis.c (OP_E_memory): Exclude recording of used address
1122 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1123 addressed memory operands for MPX insns.
1124
a0497384
JB		 11252020-03-06 Jan Beulich <jbeulich@suse.com>
1126
1127 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1128 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1129 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1130 (ptwrite): Split into non-64-bit and 64-bit forms.
1131 * i386-tbl.h: Re-generate.
1132
b630c145
JB		 11332020-03-06 Jan Beulich <jbeulich@suse.com>
1134
1135 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1136 template.
1137 * i386-tbl.h: Re-generate.
1138
a847e322
JB		 11392020-03-04 Jan Beulich <jbeulich@suse.com>
1140
1141 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1142 (prefix_table): Move vmmcall here. Add vmgexit.
1143 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1144 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1145 (cpu_flags): Add CpuSEV_ES entry.
1146 * i386-opc.h (CpuSEV_ES): New.
1147 (union i386_cpu_flags): Add cpusev_es field.
1148 * i386-opc.tbl (vmgexit): New.
1149 * i386-init.h, i386-tbl.h: Re-generate.
1150
3cd7f3e3
L		 11512020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1152
1153 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1154 with MnemonicSize.
1155 * i386-opc.h (IGNORESIZE): New.
1156 (DEFAULTSIZE): Likewise.
1157 (IgnoreSize): Removed.
1158 (DefaultSize): Likewise.
1159 (MnemonicSize): New.
1160 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1161 mnemonicsize.
1162 * i386-opc.tbl (IgnoreSize): New.
1163 (DefaultSize): Likewise.
1164 * i386-tbl.h: Regenerated.
1165
b8ba1385
SB		 11662020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1167
1168 PR 25627
1169 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1170 instructions.
1171
10d97a0f
L		 11722020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1173
1174 PR gas/25622
1175 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1176 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1177 * i386-tbl.h: Regenerated.
1178
dc1e8a47
AM		 11792020-02-26 Alan Modra <amodra@gmail.com>
1180
1181 * aarch64-asm.c: Indent labels correctly.
1182 * aarch64-dis.c: Likewise.
1183 * aarch64-gen.c: Likewise.
1184 * aarch64-opc.c: Likewise.
1185 * alpha-dis.c: Likewise.
1186 * i386-dis.c: Likewise.
1187 * nds32-asm.c: Likewise.
1188 * nfp-dis.c: Likewise.
1189 * visium-dis.c: Likewise.
1190
265b4673
CZ		 11912020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1192
1193 * arc-regs.h (int_vector_base): Make it available for all ARC
1194 CPUs.
1195
bd0cf5a6
NC		 11962020-02-20 Nelson Chu <nelson.chu@sifive.com>
1197
1198 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1199 changed.
1200
fa164239
JW		 12012020-02-19 Nelson Chu <nelson.chu@sifive.com>
1202
1203 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1204 c.mv/c.li if rs1 is zero.
1205
272a84b1
L		 12062020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1207
1208 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1209 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1210 CPU_POPCNT_FLAGS.
1211 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1212 * i386-opc.h (CpuABM): Removed.
1213 (CpuPOPCNT): New.
1214 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1215 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1216 popcnt. Remove CpuABM from lzcnt.
1217 * i386-init.h: Regenerated.
1218 * i386-tbl.h: Likewise.
1219
1f730c46
JB		 12202020-02-17 Jan Beulich <jbeulich@suse.com>
1221
1222 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1223 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1224 VexW1 instead of open-coding them.
1225 * i386-tbl.h: Re-generate.
1226
c8f8eebc
JB		 12272020-02-17 Jan Beulich <jbeulich@suse.com>
1228
1229 * i386-opc.tbl (AddrPrefixOpReg): Define.
1230 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1231 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1232 templates. Drop NoRex64.
1233 * i386-tbl.h: Re-generate.
1234
b9915cbc
JB		 12352020-02-17 Jan Beulich <jbeulich@suse.com>
1236
1237 PR gas/6518
1238 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1239 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1240 into Intel syntax instance (with Unpsecified) and AT&T one
1241 (without).
1242 (vcvtneps2bf16): Likewise, along with folding the two so far
1243 separate ones.
1244 * i386-tbl.h: Re-generate.
1245
ce504911
L		 12462020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1247
1248 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1249 CPU_ANY_SSE4A_FLAGS.
1250
dabec65d
AM		 12512020-02-17 Alan Modra <amodra@gmail.com>
1252
1253 * i386-gen.c (cpu_flag_init): Correct last change.
1254
af5c13b0
L		 12552020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1256
1257 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1258 CPU_ANY_SSE4_FLAGS.
1259
6867aac0
L		 12602020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1261
1262 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1263 (movzx): Likewise.
1264
65fca059
JB		 12652020-02-14 Jan Beulich <jbeulich@suse.com>
1266
1267 PR gas/25438
1268 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1269 destination for Cpu64-only variant.
1270 (movzx): Fold patterns.
1271 * i386-tbl.h: Re-generate.
1272
7deea9aa
JB		 12732020-02-13 Jan Beulich <jbeulich@suse.com>
1274
1275 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1276 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1277 CPU_ANY_SSE4_FLAGS entry.
1278 * i386-init.h: Re-generate.
1279
6c0946d0
JB		 12802020-02-12 Jan Beulich <jbeulich@suse.com>
1281
1282 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1283 with Unspecified, making the present one AT&T syntax only.
1284 * i386-tbl.h: Re-generate.
1285
ddb56fe6
JB		 12862020-02-12 Jan Beulich <jbeulich@suse.com>
1287
1288 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1289 * i386-tbl.h: Re-generate.
1290
5990e377
JB		 12912020-02-12 Jan Beulich <jbeulich@suse.com>
1292
1293 PR gas/24546
1294 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1295 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1296 Amd64 and Intel64 templates.
1297 (call, jmp): Likewise for far indirect variants. Dro
1298 Unspecified.
1299 * i386-tbl.h: Re-generate.
1300
50128d0c
JB		 13012020-02-11 Jan Beulich <jbeulich@suse.com>
1302
1303 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1304 * i386-opc.h (ShortForm): Delete.
1305 (struct i386_opcode_modifier): Remove shortform field.
1306 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1307 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1308 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1309 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1310 Drop ShortForm.
1311 * i386-tbl.h: Re-generate.
1312
1e05b5c4
JB		 13132020-02-11 Jan Beulich <jbeulich@suse.com>
1314
1315 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1316 fucompi): Drop ShortForm from operand-less templates.
1317 * i386-tbl.h: Re-generate.
1318
2f5dd314
AM		 13192020-02-11 Alan Modra <amodra@gmail.com>
1320
1321 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1322 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1323 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1324 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1325 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1326
5aae9ae9
MM		 13272020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1328
1329 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1330 (cde_opcodes): Add VCX* instructions.
1331
4934a27c
MM		 13322020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1333 Matthew Malcomson <matthew.malcomson@arm.com>
1334
1335 * arm-dis.c (struct cdeopcode32): New.
1336 (CDE_OPCODE): New macro.
1337 (cde_opcodes): New disassembly table.
1338 (regnames): New option to table.
1339 (cde_coprocs): New global variable.
1340 (print_insn_cde): New
1341 (print_insn_thumb32): Use print_insn_cde.
1342 (parse_arm_disassembler_options): Parse coprocN args.
1343
4b5aaf5f
L		 13442020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1345
1346 PR gas/25516
1347 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1348 with ISA64.
1349 * i386-opc.h (AMD64): Removed.
1350 (Intel64): Likewose.
1351 (AMD64): New.
1352 (INTEL64): Likewise.
1353 (INTEL64ONLY): Likewise.
1354 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1355 * i386-opc.tbl (Amd64): New.
1356 (Intel64): Likewise.
1357 (Intel64Only): Likewise.
1358 Replace AMD64 with Amd64. Update sysenter/sysenter with
1359 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1360 * i386-tbl.h: Regenerated.
1361
9fc0b501
SB		 13622020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1363
1364 PR 25469
1365 * z80-dis.c: Add support for GBZ80 opcodes.
1366
c5d7be0c
AM		 13672020-02-04 Alan Modra <amodra@gmail.com>
1368
1369 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1370
44e4546f
AM		 13712020-02-03 Alan Modra <amodra@gmail.com>
1372
1373 * m32c-ibld.c: Regenerate.
1374
b2b1453a
AM		 13752020-02-01 Alan Modra <amodra@gmail.com>
1376
1377 * frv-ibld.c: Regenerate.
1378
4102be5c
JB		 13792020-01-31 Jan Beulich <jbeulich@suse.com>
1380
1381 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1382 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1383 (OP_E_memory): Replace xmm_mdq_mode case label by
1384 vex_scalar_w_dq_mode one.
1385 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1386
825bd36c
JB		 13872020-01-31 Jan Beulich <jbeulich@suse.com>
1388
1389 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1390 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1391 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1392 (intel_operand_size): Drop vex_w_dq_mode case label.
1393
c3036ed0
RS		 13942020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1395
1396 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1397 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1398
0c115f84
AM		 13992020-01-30 Alan Modra <amodra@gmail.com>
1400
1401 * m32c-ibld.c: Regenerate.
1402
bd434cc4
JM		 14032020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1404
1405 * bpf-opc.c: Regenerate.
1406
aeab2b26
JB		 14072020-01-30 Jan Beulich <jbeulich@suse.com>
1408
1409 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1410 (dis386): Use them to replace C2/C3 table entries.
1411 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1412 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1413 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1414 * i386-tbl.h: Re-generate.
1415
62b3f548
JB		 14162020-01-30 Jan Beulich <jbeulich@suse.com>
1417
1418 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1419 forms.
1420 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1421 DefaultSize.
1422 * i386-tbl.h: Re-generate.
1423
1bd8ae10
AM		 14242020-01-30 Alan Modra <amodra@gmail.com>
1425
1426 * tic4x-dis.c (tic4x_dp): Make unsigned.
1427
bc31405e
L		 14282020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1429 Jan Beulich <jbeulich@suse.com>
1430
1431 PR binutils/25445
1432 * i386-dis.c (MOVSXD_Fixup): New function.
1433 (movsxd_mode): New enum.
1434 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1435 (intel_operand_size): Handle movsxd_mode.
1436 (OP_E_register): Likewise.
1437 (OP_G): Likewise.
1438 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1439 register on movsxd. Add movsxd with 16-bit destination register
1440 for AMD64 and Intel64 ISAs.
1441 * i386-tbl.h: Regenerated.
1442
7568c93b
TC		 14432020-01-27 Tamar Christina <tamar.christina@arm.com>
1444
1445 PR 25403
1446 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1447 * aarch64-asm-2.c: Regenerate
1448 * aarch64-dis-2.c: Likewise.
1449 * aarch64-opc-2.c: Likewise.
1450
c006a730
JB		 14512020-01-21 Jan Beulich <jbeulich@suse.com>
1452
1453 * i386-opc.tbl (sysret): Drop DefaultSize.
1454 * i386-tbl.h: Re-generate.
1455
c906a69a
JB		 14562020-01-21 Jan Beulich <jbeulich@suse.com>
1457
1458 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1459 Dword.
1460 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1461 * i386-tbl.h: Re-generate.
1462
26916852
NC		 14632020-01-20 Nick Clifton <nickc@redhat.com>
1464
1465 * po/de.po: Updated German translation.
1466 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1467 * po/uk.po: Updated Ukranian translation.
1468
4d6cbb64
AM		 14692020-01-20 Alan Modra <amodra@gmail.com>
1470
1471 * hppa-dis.c (fput_const): Remove useless cast.
1472
2bddb71a
AM		 14732020-01-20 Alan Modra <amodra@gmail.com>
1474
1475 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1476
1b1bb2c6
NC		 14772020-01-18 Nick Clifton <nickc@redhat.com>
1478
1479 * configure: Regenerate.
1480 * po/opcodes.pot: Regenerate.
1481
ae774686
NC		 14822020-01-18 Nick Clifton <nickc@redhat.com>
1483
1484 Binutils 2.34 branch created.
1485
07f1f3aa
CB		 14862020-01-17 Christian Biesinger <cbiesinger@google.com>
1487
1488 * opintl.h: Fix spelling error (seperate).
1489
42e04b36
L		 14902020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1491
1492 * i386-opc.tbl: Add {vex} pseudo prefix.
1493 * i386-tbl.h: Regenerated.
1494
2da2eaf4
AV		 14952020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1496
1497 PR 25376
1498 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1499 (neon_opcodes): Likewise.
1500 (select_arm_features): Make sure we enable MVE bits when selecting
1501 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1502 any architecture.
1503
d0849eed
JB		 15042020-01-16 Jan Beulich <jbeulich@suse.com>
1505
1506 * i386-opc.tbl: Drop stale comment from XOP section.
1507
9cf70a44
JB		 15082020-01-16 Jan Beulich <jbeulich@suse.com>
1509
1510 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1511 (extractps): Add VexWIG to SSE2AVX forms.
1512 * i386-tbl.h: Re-generate.
1513
4814632e
JB		 15142020-01-16 Jan Beulich <jbeulich@suse.com>
1515
1516 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1517 Size64 from and use VexW1 on SSE2AVX forms.
1518 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1519 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1520 * i386-tbl.h: Re-generate.
1521
aad09917
AM		 15222020-01-15 Alan Modra <amodra@gmail.com>
1523
1524 * tic4x-dis.c (tic4x_version): Make unsigned long.
1525 (optab, optab_special, registernames): New file scope vars.
1526 (tic4x_print_register): Set up registernames rather than
1527 malloc'd registertable.
1528 (tic4x_disassemble): Delete optable and optable_special. Use
1529 optab and optab_special instead. Throw away old optab,
1530 optab_special and registernames when info->mach changes.
1531
7a6bf3be
SB		 15322020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1533
1534 PR 25377
1535 * z80-dis.c (suffix): Use .db instruction to generate double
1536 prefix.
1537
ca1eaac0
AM		 15382020-01-14 Alan Modra <amodra@gmail.com>
1539
1540 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1541 values to unsigned before shifting.
1542
1d67fe3b
TT		 15432020-01-13 Thomas Troeger <tstroege@gmx.de>
1544
1545 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1546 flow instructions.
1547 (print_insn_thumb16, print_insn_thumb32): Likewise.
1548 (print_insn): Initialize the insn info.
1549 * i386-dis.c (print_insn): Initialize the insn info fields, and
1550 detect jumps.
1551
5e4f7e05
CZ		 15522012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1553
1554 * arc-opc.c (C_NE): Make it required.
1555
b9fe6b8a
CZ		 15562012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1557
1558 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1559 reserved register name.
1560
90dee485
AM		 15612020-01-13 Alan Modra <amodra@gmail.com>
1562
1563 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1564 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1565
febda64f
AM		 15662020-01-13 Alan Modra <amodra@gmail.com>
1567
1568 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1569 result of wasm_read_leb128 in a uint64_t and check that bits
1570 are not lost when copying to other locals. Use uint32_t for
1571 most locals. Use PRId64 when printing int64_t.
1572
df08b588
AM		 15732020-01-13 Alan Modra <amodra@gmail.com>
1574
1575 * score-dis.c: Formatting.
1576 * score7-dis.c: Formatting.
1577
b2c759ce
AM		 15782020-01-13 Alan Modra <amodra@gmail.com>
1579
1580 * score-dis.c (print_insn_score48): Use unsigned variables for
1581 unsigned values. Don't left shift negative values.
1582 (print_insn_score32): Likewise.
1583 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1584
5496abe1
AM		 15852020-01-13 Alan Modra <amodra@gmail.com>
1586
1587 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1588
202e762b
AM		 15892020-01-13 Alan Modra <amodra@gmail.com>
1590
1591 * fr30-ibld.c: Regenerate.
1592
7ef412cf
AM		 15932020-01-13 Alan Modra <amodra@gmail.com>
1594
1595 * xgate-dis.c (print_insn): Don't left shift signed value.
1596 (ripBits): Formatting, use 1u.
1597
7f578b95
AM		 15982020-01-10 Alan Modra <amodra@gmail.com>
1599
1600 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1601 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1602
441af85b
AM		 16032020-01-10 Alan Modra <amodra@gmail.com>
1604
1605 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1606 and XRREG value earlier to avoid a shift with negative exponent.
1607 * m10200-dis.c (disassemble): Similarly.
1608
bce58db4
NC		 16092020-01-09 Nick Clifton <nickc@redhat.com>
1610
1611 PR 25224
1612 * z80-dis.c (ld_ii_ii): Use correct cast.
1613
40c75bc8
SB		 16142020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1615
1616 PR 25224
1617 * z80-dis.c (ld_ii_ii): Use character constant when checking
1618 opcode byte value.
1619
d835a58b
JB		 16202020-01-09 Jan Beulich <jbeulich@suse.com>
1621
1622 * i386-dis.c (SEP_Fixup): New.
1623 (SEP): Define.
1624 (dis386_twobyte): Use it for sysenter/sysexit.
1625 (enum x86_64_isa): Change amd64 enumerator to value 1.
1626 (OP_J): Compare isa64 against intel64 instead of amd64.
1627 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1628 forms.
1629 * i386-tbl.h: Re-generate.
1630
030a2e78
AM		 16312020-01-08 Alan Modra <amodra@gmail.com>
1632
1633 * z8k-dis.c: Include libiberty.h
1634 (instr_data_s): Make max_fetched unsigned.
1635 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1636 Don't exceed byte_info bounds.
1637 (output_instr): Make num_bytes unsigned.
1638 (unpack_instr): Likewise for nibl_count and loop.
1639 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1640 idx unsigned.
1641 * z8k-opc.h: Regenerate.
1642
bb82aefe
SV		 16432020-01-07 Shahab Vahedi <shahab@synopsys.com>
1644
1645 * arc-tbl.h (llock): Use 'LLOCK' as class.
1646 (llockd): Likewise.
1647 (scond): Use 'SCOND' as class.
1648 (scondd): Likewise.
1649 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1650 (scondd): Likewise.
1651
cc6aa1a6
AM		 16522020-01-06 Alan Modra <amodra@gmail.com>
1653
1654 * m32c-ibld.c: Regenerate.
1655
660e62b1
AM		 16562020-01-06 Alan Modra <amodra@gmail.com>
1657
1658 PR 25344
1659 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1660 Peek at next byte to prevent recursion on repeated prefix bytes.
1661 Ensure uninitialised "mybuf" is not accessed.
1662 (print_insn_z80): Don't zero n_fetch and n_used here,..
1663 (print_insn_z80_buf): ..do it here instead.
1664
c9ae58fe
AM		 16652020-01-04 Alan Modra <amodra@gmail.com>
1666
1667 * m32r-ibld.c: Regenerate.
1668
5f57d4ec
AM		 16692020-01-04 Alan Modra <amodra@gmail.com>
1670
1671 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1672
2c5c1196
AM		 16732020-01-04 Alan Modra <amodra@gmail.com>
1674
1675 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1676
2e98c6c5
AM		 16772020-01-04 Alan Modra <amodra@gmail.com>
1678
1679 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1680
567dfba2
JB		 16812020-01-03 Jan Beulich <jbeulich@suse.com>
1682
5437a02a
JB		 1683 * aarch64-tbl.h (aarch64_opcode_table): Use
1684 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1685
16862020-01-03 Jan Beulich <jbeulich@suse.com>
1687
1688 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1689 forms of SUDOT and USDOT.
1690
8c45011a
JB		 16912020-01-03 Jan Beulich <jbeulich@suse.com>
1692
5437a02a 1693 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1694 uzip{1,2}.
1695 * opcodes/aarch64-dis-2.c: Re-generate.
1696
f4950f76
JB		 16972020-01-03 Jan Beulich <jbeulich@suse.com>
1698
5437a02a 1699 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1700 FMMLA encoding.
1701 * opcodes/aarch64-dis-2.c: Re-generate.
1702
6655dba2
SB		 17032020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1704
1705 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1706
b14ce8bf
AM		 17072020-01-01 Alan Modra <amodra@gmail.com>
1708
1709 Update year range in copyright notice of all files.
1710
0b114740 1711For older changes see ChangeLog-2019
3499769a 1712\f
0b114740 1713Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1714
1715Copying and distribution of this file, with or without modification,
1716are permitted in any medium without royalty provided the copyright
1717notice and this notice are preserved.
1718
1719Local Variables:
1720mode: change-log
1721left-margin: 8
1722fill-column: 74
1723version-control: never
1724End:
GDB Binutils - Deliverables
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