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x86: various XOP insns lack L and/or W bit decoding
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
467bbef0
JB		 12020-07-08 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
4 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
5 Rename to ...
6 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
7 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
8 respectively.
9 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
10 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
11 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
12 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
13 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
14 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
15 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
16 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
17 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
18 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
19 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
20 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
21 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
22 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
23 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
24 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
25 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
26 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
27 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
28 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
29 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
30 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
31 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
32 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
33 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
34 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
35 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
36 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
37 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
38 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
39 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
40 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
41 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
42 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
43 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
44 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
45 (reg_table): Re-order XOP entries. Adjust their operands.
46 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
47 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
48 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
49 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
50 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
51 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
52 entries by references ...
53 (vex_len_table): ... to resepctive new entries here. For several
54 new and existing entries reference ...
55 (vex_w_table): ... new entries here.
56 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
57
6384fd9e
JB		 582020-07-08 Jan Beulich <jbeulich@suse.com>
59
60 * i386-dis.c (XMVexScalarI4): Define.
61 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
62 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
63 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
64 (vex_len_table): Move scalar FMA4 entries ...
65 (prefix_table): ... here.
66 (OP_REG_VexI4): Handle scalar_mode.
67 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
68 * i386-tbl.h: Re-generate.
69
e6123d0c
JB		 702020-07-08 Jan Beulich <jbeulich@suse.com>
71
72 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
73 Vex_2src_2): Delete.
74 (OP_VexW, VexW): New.
75 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
76 for shifts and rotates by register.
77
93abb146
JB		 782020-07-08 Jan Beulich <jbeulich@suse.com>
79
80 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
81 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
82 OP_EX_VexReg): Delete.
83 (OP_VexI4, VexI4): New.
84 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
85 (prefix_table): ... here.
86 (print_insn): Drop setting of vex_w_done.
87
b13b1bc0
JB		 882020-07-08 Jan Beulich <jbeulich@suse.com>
89
90 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
91 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
92 (xop_table): Replace operands of 4-operand insns.
93 (OP_REG_VexI4): Move VEX.W based operand swaping here.
94
f337259f
CZ		 952020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
96
97 * arc-opc.c (insert_rbd): New function.
98 (RBD): Define.
99 (RBDdup): Likewise.
100 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
101 instructions.
102
931452b6
JB		 1032020-07-07 Jan Beulich <jbeulich@suse.com>
104
105 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
106 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
107 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
108 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
109 Delete.
110 (putop): Handle "BW".
111 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
112 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
113 and 0F3A3F ...
114 * i386-dis-evex-prefix.h: ... here.
115
b5b098c2
JB		 1162020-07-06 Jan Beulich <jbeulich@suse.com>
117
118 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
119 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
120 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
121 VEX_W_0FXOP_09_83): New enumerators.
122 (xop_table): Reference the above.
123 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
124 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
125 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
126 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
127
21a3faeb
JB		 1282020-07-06 Jan Beulich <jbeulich@suse.com>
129
130 * i386-dis.c (EVEX_W_0F3838_P_1,
131 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
132 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
133 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
134 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
135 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
136 (putop): Centralize management of last[]. Delete SAVE_LAST.
137 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
138 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
139 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
140 * i386-dis-evex-prefix.h: here.
141
bc152a17
JB		 1422020-07-06 Jan Beulich <jbeulich@suse.com>
143
144 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
145 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
146 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
147 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
148 enumerators.
149 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
150 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
151 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
152 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
153 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
154 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
155 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
156 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
157 these, respectively.
158 * i386-dis-evex-len.h: Adjust comments.
159 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
160 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
161 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
162 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
163 MOD_EVEX_0F385B_P_2_W_1 table entries.
164 * i386-dis-evex-w.h: Reference mod_table[] for
165 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
166 EVEX_W_0F385B_P_2.
167
c82a99a0
JB		 1682020-07-06 Jan Beulich <jbeulich@suse.com>
169
170 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
171 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
172 EXymm.
173 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
174 Likewise. Mark 256-bit entries invalid.
175
fedfb81e
JB		 1762020-07-06 Jan Beulich <jbeulich@suse.com>
177
178 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
179 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
180 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
181 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
182 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
183 PREFIX_EVEX_0F382B): Delete.
184 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
185 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
186 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
187 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
188 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
189 to ...
190 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
191 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
192 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
193 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
194 respectively.
195 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
196 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
197 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
198 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
199 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
200 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
201 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
202 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
203 PREFIX_EVEX_0F382B): Remove table entries.
204 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
205 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
206 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
207
3a57774c
JB		 2082020-07-06 Jan Beulich <jbeulich@suse.com>
209
210 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
211 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
212 enumerators.
213 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
214 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
215 EVEX_LEN_0F3A01_P_2_W_1 table entries.
216 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
217 entries.
218
e74d9fa9
JB		 2192020-07-06 Jan Beulich <jbeulich@suse.com>
220
221 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
222 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
223 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
224 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
225 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
226 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
227 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
228 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
229 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
230 entries.
231
6431c801
JB		 2322020-07-06 Jan Beulich <jbeulich@suse.com>
233
234 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
235 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
236 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
237 respectively.
238 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
239 entries.
240 * i386-dis-evex.h (evex_table): Reference VEX table entry for
241 opcode 0F3A1D.
242 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
243 entry.
244 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
245
6df22cf6
JB		 2462020-07-06 Jan Beulich <jbeulich@suse.com>
247
248 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
249 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
250 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
251 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
252 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
253 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
254 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
255 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
256 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
257 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
258 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
259 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
260 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
261 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
262 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
263 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
264 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
265 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
266 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
267 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
268 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
269 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
270 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
271 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
272 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
273 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
274 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
275 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
276 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
277 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
278 (prefix_table): Add EXxEVexR to FMA table entries.
279 (OP_Rounding): Move abort() invocation.
280 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
281 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
282 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
283 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
284 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
285 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
286 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
287 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
288 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
289 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
290 0F3ACE, 0F3ACF.
291 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
292 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
293 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
294 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
295 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
296 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
297 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
298 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
299 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
300 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
301 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
302 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
303 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
304 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
305 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
306 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
307 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
308 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
309 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
310 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
311 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
312 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
313 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
314 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
315 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
316 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
317 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
318 Delete table entries.
319 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
320 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
321 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
322 Likewise.
323
39e0f456
JB		 3242020-07-06 Jan Beulich <jbeulich@suse.com>
325
326 * i386-dis.c (EXqScalarS): Delete.
327 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
328 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
329
5b872f7d
JB		 3302020-07-06 Jan Beulich <jbeulich@suse.com>
331
332 * i386-dis.c (safe-ctype.h): Include.
333 (EXdScalar, EXqScalar): Delete.
334 (d_scalar_mode, q_scalar_mode): Delete.
335 (prefix_table, vex_len_table): Use EXxmm_md in place of
336 EXdScalar and EXxmm_mq in place of EXqScalar.
337 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
338 d_scalar_mode and q_scalar_mode.
339 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
340 (vmovsd): Use EXxmm_mq.
341
ddc73fa9
NC		 3422020-07-06 Yuri Chornoivan <yurchor@ukr.net>
343
344 PR 26204
345 * arc-dis.c: Fix spelling mistake.
346 * po/opcodes.pot: Regenerate.
347
17550be7
NC		 3482020-07-06 Nick Clifton <nickc@redhat.com>
349
350 * po/pt_BR.po: Updated Brazilian Portugugese translation.
351 * po/uk.po: Updated Ukranian translation.
352
b19d852d
NC		 3532020-07-04 Nick Clifton <nickc@redhat.com>
354
355 * configure: Regenerate.
356 * po/opcodes.pot: Regenerate.
357
b115b9fd
NC		 3582020-07-04 Nick Clifton <nickc@redhat.com>
359
360 Binutils 2.35 branch created.
361
c2ecccb3
L		 3622020-07-02 H.J. Lu <hongjiu.lu@intel.com>
363
364 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
365 * i386-opc.h (VexSwapSources): New.
366 (i386_opcode_modifier): Add vexswapsources.
367 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
368 with two source operands swapped.
369 * i386-tbl.h: Regenerated.
370
08ccfccf
NC		 3712020-06-30 Nelson Chu <nelson.chu@sifive.com>
372
373 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
374 unprivileged CSR can also be initialized.
375
279edac5
AM		 3762020-06-29 Alan Modra <amodra@gmail.com>
377
378 * arm-dis.c: Use C style comments.
379 * cr16-opc.c: Likewise.
380 * ft32-dis.c: Likewise.
381 * moxie-opc.c: Likewise.
382 * tic54x-dis.c: Likewise.
383 * s12z-opc.c: Remove useless comment.
384 * xgate-dis.c: Likewise.
385
e978ad62
L		 3862020-06-26 H.J. Lu <hongjiu.lu@intel.com>
387
388 * i386-opc.tbl: Add a blank line.
389
63112cd6
L		 3902020-06-26 H.J. Lu <hongjiu.lu@intel.com>
391
392 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
393 (VecSIB128): Renamed to ...
394 (VECSIB128): This.
395 (VecSIB256): Renamed to ...
396 (VECSIB256): This.
397 (VecSIB512): Renamed to ...
398 (VECSIB512): This.
399 (VecSIB): Renamed to ...
400 (SIB): This.
401 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 402 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 403 (VecSIB256): Likewise.
404 (VecSIB512): Likewise.
79b32e73 405 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 406 and VecSIB512, respectively.
407
d1c36125
JB		 4082020-06-26 Jan Beulich <jbeulich@suse.com>
409
410 * i386-dis.c: Adjust description of I macro.
411 (x86_64_table): Drop use of I.
412 (float_mem): Replace use of I.
413 (putop): Remove handling of I. Adjust setting/clearing of "alt".
414
2a1bb84c
JB		 4152020-06-26 Jan Beulich <jbeulich@suse.com>
416
417 * i386-dis.c: (print_insn): Avoid straight assignment to
418 priv.orig_sizeflag when processing -M sub-options.
419
8f570d62
JB		 4202020-06-25 Jan Beulich <jbeulich@suse.com>
421
422 * i386-dis.c: Adjust description of J macro.
423 (dis386, x86_64_table, mod_table): Replace J.
424 (putop): Remove handling of J.
425
464dc4af
JB		 4262020-06-25 Jan Beulich <jbeulich@suse.com>
427
428 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
429
589958d6
JB		 4302020-06-25 Jan Beulich <jbeulich@suse.com>
431
432 * i386-dis.c: Adjust description of "LQ" macro.
433 (dis386_twobyte): Use LQ for sysret.
434 (putop): Adjust handling of LQ.
435
39ff0b81
NC		 4362020-06-22 Nelson Chu <nelson.chu@sifive.com>
437
438 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
439 * riscv-dis.c: Include elfxx-riscv.h.
440
d27c357a
JB		 4412020-06-18 H.J. Lu <hongjiu.lu@intel.com>
442
443 * i386-dis.c (prefix_table): Revert the last vmgexit change.
444
6fde587f
CL		 4452020-06-17 Lili Cui <lili.cui@intel.com>
446
447 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
448
efe30057
L		 4492020-06-14 H.J. Lu <hongjiu.lu@intel.com>
450
451 PR gas/26115
452 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
453 * i386-opc.tbl: Likewise.
454 * i386-tbl.h: Regenerated.
455
d8af286f
NC		 4562020-06-12 Nelson Chu <nelson.chu@sifive.com>
457
458 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
459
14962256
AC		 4602020-06-11 Alex Coplan <alex.coplan@arm.com>
461
462 * aarch64-opc.c (SYSREG): New macro for describing system registers.
463 (SR_CORE): Likewise.
464 (SR_FEAT): Likewise.
465 (SR_RNG): Likewise.
466 (SR_V8_1): Likewise.
467 (SR_V8_2): Likewise.
468 (SR_V8_3): Likewise.
469 (SR_V8_4): Likewise.
470 (SR_PAN): Likewise.
471 (SR_RAS): Likewise.
472 (SR_SSBS): Likewise.
473 (SR_SVE): Likewise.
474 (SR_ID_PFR2): Likewise.
475 (SR_PROFILE): Likewise.
476 (SR_MEMTAG): Likewise.
477 (SR_SCXTNUM): Likewise.
478 (aarch64_sys_regs): Refactor to store feature information in the table.
479 (aarch64_sys_reg_supported_p): Collapse logic for system registers
480 that now describe their own features.
481 (aarch64_pstatefield_supported_p): Likewise.
482
f9630fa6
L		 4832020-06-09 H.J. Lu <hongjiu.lu@intel.com>
484
485 * i386-dis.c (prefix_table): Fix a typo in comments.
486
73239888
JB		 4872020-06-09 Jan Beulich <jbeulich@suse.com>
488
489 * i386-dis.c (rex_ignored): Delete.
490 (ckprefix): Drop rex_ignored initialization.
491 (get_valid_dis386): Drop setting of rex_ignored.
492 (print_insn): Drop checking of rex_ignored. Don't record data
493 size prefix as used with VEX-and-alike encodings.
494
18897deb
JB		 4952020-06-09 Jan Beulich <jbeulich@suse.com>
496
497 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
498 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
499 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
500 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
501 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
502 VEX_0F12, and VEX_0F16.
503 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
504 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
505 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
506 from movlps and movhlps. New MOD_0F12_PREFIX_2,
507 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
508 MOD_VEX_0F16_PREFIX_2 entries.
509
97e6786a
JB		 5102020-06-09 Jan Beulich <jbeulich@suse.com>
511
512 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
513 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
514 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
515 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
516 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
517 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
518 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
519 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
520 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
521 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
522 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
523 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
524 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
525 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
526 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
527 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
528 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
529 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
530 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
531 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
532 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
533 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
534 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
535 EVEX_W_0FC6_P_2): Delete.
536 (print_insn): Add EVEX.W vs embedded prefix consistency check
537 to prefix validation.
538 * i386-dis-evex.h (evex_table): Don't further descend for
539 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
540 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
541 and 0F2B.
542 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
543 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
544 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
545 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
546 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
547 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
548 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
549 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
550 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
551 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
552 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
553 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
554 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
555 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
556 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
557 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
558 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
559 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
560 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
561 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
562 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
563 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
564 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
565 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
566 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
567 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
568 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
569
bf926894
JB		 5702020-06-09 Jan Beulich <jbeulich@suse.com>
571
572 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
573 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
574 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
575 vmovmskpX.
576 (print_insn): Drop pointless check against bad_opcode. Split
577 prefix validation into legacy and VEX-and-alike parts.
578 (putop): Re-work 'X' macro handling.
579
a5aaedb9
JB		 5802020-06-09 Jan Beulich <jbeulich@suse.com>
581
582 * i386-dis.c (MOD_0F51): Rename to ...
583 (MOD_0F50): ... this.
584
26417f19
AC		 5852020-06-08 Alex Coplan <alex.coplan@arm.com>
586
587 * arm-dis.c (arm_opcodes): Add dfb.
588 (thumb32_opcodes): Add dfb.
589
8a6fb3f9
JB		 5902020-06-08 Jan Beulich <jbeulich@suse.com>
591
592 * i386-opc.h (reg_entry): Const-qualify reg_name field.
593
1424c35d
AM		 5942020-06-06 Alan Modra <amodra@gmail.com>
595
596 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
597
d3d1cc7b
AM		 5982020-06-05 Alan Modra <amodra@gmail.com>
599
600 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
601 size is large enough.
602
d8740be1
JM		 6032020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
604
605 * disassemble.c (disassemble_init_for_target): Set endian_code for
606 bpf targets.
607 * bpf-desc.c: Regenerate.
608 * bpf-opc.c: Likewise.
609 * bpf-dis.c: Likewise.
610
e9bffec9
JM		 6112020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
612
613 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
614 (cgen_put_insn_value): Likewise.
615 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
616 * cgen-dis.in (print_insn): Likewise.
617 * cgen-ibld.in (insert_1): Likewise.
618 (insert_1): Likewise.
619 (insert_insn_normal): Likewise.
620 (extract_1): Likewise.
621 * bpf-dis.c: Regenerate.
622 * bpf-ibld.c: Likewise.
623 * bpf-ibld.c: Likewise.
624 * cgen-dis.in: Likewise.
625 * cgen-ibld.in: Likewise.
626 * cgen-opc.c: Likewise.
627 * epiphany-dis.c: Likewise.
628 * epiphany-ibld.c: Likewise.
629 * fr30-dis.c: Likewise.
630 * fr30-ibld.c: Likewise.
631 * frv-dis.c: Likewise.
632 * frv-ibld.c: Likewise.
633 * ip2k-dis.c: Likewise.
634 * ip2k-ibld.c: Likewise.
635 * iq2000-dis.c: Likewise.
636 * iq2000-ibld.c: Likewise.
637 * lm32-dis.c: Likewise.
638 * lm32-ibld.c: Likewise.
639 * m32c-dis.c: Likewise.
640 * m32c-ibld.c: Likewise.
641 * m32r-dis.c: Likewise.
642 * m32r-ibld.c: Likewise.
643 * mep-dis.c: Likewise.
644 * mep-ibld.c: Likewise.
645 * mt-dis.c: Likewise.
646 * mt-ibld.c: Likewise.
647 * or1k-dis.c: Likewise.
648 * or1k-ibld.c: Likewise.
649 * xc16x-dis.c: Likewise.
650 * xc16x-ibld.c: Likewise.
651 * xstormy16-dis.c: Likewise.
652 * xstormy16-ibld.c: Likewise.
653
b3db6d07
JM		 6542020-06-04 Jose E. Marchesi <jemarch@gnu.org>
655
656 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
657 (print_insn_): Handle instruction endian.
658 * bpf-dis.c: Regenerate.
659 * bpf-desc.c: Regenerate.
660 * epiphany-dis.c: Likewise.
661 * epiphany-desc.c: Likewise.
662 * fr30-dis.c: Likewise.
663 * fr30-desc.c: Likewise.
664 * frv-dis.c: Likewise.
665 * frv-desc.c: Likewise.
666 * ip2k-dis.c: Likewise.
667 * ip2k-desc.c: Likewise.
668 * iq2000-dis.c: Likewise.
669 * iq2000-desc.c: Likewise.
670 * lm32-dis.c: Likewise.
671 * lm32-desc.c: Likewise.
672 * m32c-dis.c: Likewise.
673 * m32c-desc.c: Likewise.
674 * m32r-dis.c: Likewise.
675 * m32r-desc.c: Likewise.
676 * mep-dis.c: Likewise.
677 * mep-desc.c: Likewise.
678 * mt-dis.c: Likewise.
679 * mt-desc.c: Likewise.
680 * or1k-dis.c: Likewise.
681 * or1k-desc.c: Likewise.
682 * xc16x-dis.c: Likewise.
683 * xc16x-desc.c: Likewise.
684 * xstormy16-dis.c: Likewise.
685 * xstormy16-desc.c: Likewise.
686
4ee4189f
NC		 6872020-06-03 Nick Clifton <nickc@redhat.com>
688
689 * po/sr.po: Updated Serbian translation.
690
44730156
NC		 6912020-06-03 Nelson Chu <nelson.chu@sifive.com>
692
693 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
694 (riscv_get_priv_spec_class): Likewise.
695
3c3d0376
AM		 6962020-06-01 Alan Modra <amodra@gmail.com>
697
698 * bpf-desc.c: Regenerate.
699
78c1c354
JM		 7002020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
701 David Faust <david.faust@oracle.com>
702
703 * bpf-desc.c: Regenerate.
704 * bpf-opc.h: Likewise.
705 * bpf-opc.c: Likewise.
706 * bpf-dis.c: Likewise.
707
efcf5fb5
AM		 7082020-05-28 Alan Modra <amodra@gmail.com>
709
710 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
711 values.
712
ab382d64
AM		 7132020-05-28 Alan Modra <amodra@gmail.com>
714
715 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
716 immediates.
717 (print_insn_ns32k): Revert last change.
718
151f5de4
NC		 7192020-05-28 Nick Clifton <nickc@redhat.com>
720
721 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
722 static.
723
25e1eca8
SL		 7242020-05-26 Sandra Loosemore <sandra@codesourcery.com>
725
726 Fix extraction of signed constants in nios2 disassembler (again).
727
728 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
729 extractions of signed fields.
730
57b17940
SSF		 7312020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
732
733 * s390-opc.txt: Relocate vector load/store instructions with
734 additional alignment parameter and change architecture level
735 constraint from z14 to z13.
736
d96bf37b
AM		 7372020-05-21 Alan Modra <amodra@gmail.com>
738
739 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
740 * sparc-dis.c: Likewise.
741 * tic4x-dis.c: Likewise.
742 * xtensa-dis.c: Likewise.
743 * bpf-desc.c: Regenerate.
744 * epiphany-desc.c: Regenerate.
745 * fr30-desc.c: Regenerate.
746 * frv-desc.c: Regenerate.
747 * ip2k-desc.c: Regenerate.
748 * iq2000-desc.c: Regenerate.
749 * lm32-desc.c: Regenerate.
750 * m32c-desc.c: Regenerate.
751 * m32r-desc.c: Regenerate.
752 * mep-asm.c: Regenerate.
753 * mep-desc.c: Regenerate.
754 * mt-desc.c: Regenerate.
755 * or1k-desc.c: Regenerate.
756 * xc16x-desc.c: Regenerate.
757 * xstormy16-desc.c: Regenerate.
758
8f595e9b
NC		 7592020-05-20 Nelson Chu <nelson.chu@sifive.com>
760
761 * riscv-opc.c (riscv_ext_version_table): The table used to store
762 all information about the supported spec and the corresponding ISA
763 versions. Currently, only Zicsr is supported to verify the
764 correctness of Z sub extension settings. Others will be supported
765 in the future patches.
766 (struct isa_spec_t, isa_specs): List for all supported ISA spec
767 classes and the corresponding strings.
768 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
769 spec class by giving a ISA spec string.
770 * riscv-opc.c (struct priv_spec_t): New structure.
771 (struct priv_spec_t priv_specs): List for all supported privilege spec
772 classes and the corresponding strings.
773 (riscv_get_priv_spec_class): New function. Get the corresponding
774 privilege spec class by giving a spec string.
775 (riscv_get_priv_spec_name): New function. Get the corresponding
776 privilege spec string by giving a CSR version class.
777 * riscv-dis.c: Updated since DECLARE_CSR is changed.
778 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
779 according to the chosen version. Build a hash table riscv_csr_hash to
780 store the valid CSR for the chosen pirv verison. Dump the direct
781 CSR address rather than it's name if it is invalid.
782 (parse_riscv_dis_option_without_args): New function. Parse the options
783 without arguments.
784 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
785 parse the options without arguments first, and then handle the options
786 with arguments. Add the new option -Mpriv-spec, which has argument.
787 * riscv-dis.c (print_riscv_disassembler_options): Add description
788 about the new OBJDUMP option.
789
3d205eb4
PB		 7902020-05-19 Peter Bergner <bergner@linux.ibm.com>
791
792 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
793 WC values on POWER10 sync, dcbf and wait instructions.
794 (insert_pl, extract_pl): New functions.
795 (L2OPT, LS, WC): Use insert_ls and extract_ls.
796 (LS3): New , 3-bit L for sync.
797 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
798 (SC2, PL): New, 2-bit SC and PL for sync and wait.
799 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
800 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
801 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
802 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
803 <wait>: Enable PL operand on POWER10.
804 <dcbf>: Enable L3OPT operand on POWER10.
805 <sync>: Enable SC2 operand on POWER10.
806
a501eb44
SH		 8072020-05-19 Stafford Horne <shorne@gmail.com>
808
809 PR 25184
810 * or1k-asm.c: Regenerate.
811 * or1k-desc.c: Regenerate.
812 * or1k-desc.h: Regenerate.
813 * or1k-dis.c: Regenerate.
814 * or1k-ibld.c: Regenerate.
815 * or1k-opc.c: Regenerate.
816 * or1k-opc.h: Regenerate.
817 * or1k-opinst.c: Regenerate.
818
3b646889
AM		 8192020-05-11 Alan Modra <amodra@gmail.com>
820
821 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
822 xsmaxcqp, xsmincqp.
823
9cc4ce88
AM		 8242020-05-11 Alan Modra <amodra@gmail.com>
825
826 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
827 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
828
5d57bc3f
AM		 8292020-05-11 Alan Modra <amodra@gmail.com>
830
831 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
832
66ef5847
AM		 8332020-05-11 Alan Modra <amodra@gmail.com>
834
835 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
836 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
837
4f3e9537
PB		 8382020-05-11 Peter Bergner <bergner@linux.ibm.com>
839
840 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
841 mnemonics.
842
ec40e91c
AM		 8432020-05-11 Alan Modra <amodra@gmail.com>
844
845 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
846 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
847 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
848 (prefix_opcodes): Add xxeval.
849
d7e97a76
AM		 8502020-05-11 Alan Modra <amodra@gmail.com>
851
852 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
853 xxgenpcvwm, xxgenpcvdm.
854
fdefed7c
AM		 8552020-05-11 Alan Modra <amodra@gmail.com>
856
857 * ppc-opc.c (MP, VXVAM_MASK): Define.
858 (VXVAPS_MASK): Use VXVA_MASK.
859 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
860 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
861 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
862 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
863
aa3c112f
AM		 8642020-05-11 Alan Modra <amodra@gmail.com>
865 Peter Bergner <bergner@linux.ibm.com>
866
867 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
868 New functions.
869 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
870 YMSK2, XA6a, XA6ap, XB6a entries.
871 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
872 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
873 (PPCVSX4): Define.
874 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
875 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
876 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
877 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
878 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
879 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
880 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
881 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
882 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
883 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
884 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
885 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
886 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
887 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
888
6edbfd3b
AM		 8892020-05-11 Alan Modra <amodra@gmail.com>
890
891 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
892 (insert_xts, extract_xts): New functions.
893 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
894 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
895 (VXRC_MASK, VXSH_MASK): Define.
896 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
897 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
898 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
899 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
900 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
901 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
902 xxblendvh, xxblendvw, xxblendvd, xxpermx.
903
c7d7aea2
AM		 9042020-05-11 Alan Modra <amodra@gmail.com>
905
906 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
907 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
908 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
909 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
910 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
911
94ba9882
AM		 9122020-05-11 Alan Modra <amodra@gmail.com>
913
914 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
915 (XTP, DQXP, DQXP_MASK): Define.
916 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
917 (prefix_opcodes): Add plxvp and pstxvp.
918
f4791f1a
AM		 9192020-05-11 Alan Modra <amodra@gmail.com>
920
921 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
922 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
923 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
924
3ff0a5ba
PB		 9252020-05-11 Peter Bergner <bergner@linux.ibm.com>
926
927 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
928
afef4fe9
PB		 9292020-05-11 Peter Bergner <bergner@linux.ibm.com>
930
931 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
932 (L1OPT): Define.
933 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
934
1224c05d
PB		 9352020-05-11 Peter Bergner <bergner@linux.ibm.com>
936
937 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
938
6bbb0c05
AM		 9392020-05-11 Alan Modra <amodra@gmail.com>
940
941 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
942
7c1f4227
AM		 9432020-05-11 Alan Modra <amodra@gmail.com>
944
945 * ppc-dis.c (ppc_opts): Add "power10" entry.
946 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
947 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
948
73199c2b
NC		 9492020-05-11 Nick Clifton <nickc@redhat.com>
950
951 * po/fr.po: Updated French translation.
952
09c1e68a
AC		 9532020-04-30 Alex Coplan <alex.coplan@arm.com>
954
955 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
956 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
957 (operand_general_constraint_met_p): validate
958 AARCH64_OPND_UNDEFINED.
959 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
960 for FLD_imm16_2.
961 * aarch64-asm-2.c: Regenerated.
962 * aarch64-dis-2.c: Regenerated.
963 * aarch64-opc-2.c: Regenerated.
964
9654d51a
NC		 9652020-04-29 Nick Clifton <nickc@redhat.com>
966
967 PR 22699
968 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
969 and SETRC insns.
970
c2e71e57
NC		 9712020-04-29 Nick Clifton <nickc@redhat.com>
972
973 * po/sv.po: Updated Swedish translation.
974
5c936ef5
NC		 9752020-04-29 Nick Clifton <nickc@redhat.com>
976
977 PR 22699
978 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
979 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
980 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
981 IMM0_8U case.
982
bb2a1453
AS		 9832020-04-21 Andreas Schwab <schwab@linux-m68k.org>
984
985 PR 25848
986 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
987 cmpi only on m68020up and cpu32.
988
c2e5c986
SD		 9892020-04-20 Sudakshina Das <sudi.das@arm.com>
990
991 * aarch64-asm.c (aarch64_ins_none): New.
992 * aarch64-asm.h (ins_none): New declaration.
993 * aarch64-dis.c (aarch64_ext_none): New.
994 * aarch64-dis.h (ext_none): New declaration.
995 * aarch64-opc.c (aarch64_print_operand): Update case for
996 AARCH64_OPND_BARRIER_PSB.
997 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
998 (AARCH64_OPERANDS): Update inserter/extracter for
999 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1000 * aarch64-asm-2.c: Regenerated.
1001 * aarch64-dis-2.c: Regenerated.
1002 * aarch64-opc-2.c: Regenerated.
1003
8a6e1d1d
SD		 10042020-04-20 Sudakshina Das <sudi.das@arm.com>
1005
1006 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1007 (aarch64_feature_ras, RAS): Likewise.
1008 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1009 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1010 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1011 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1012 * aarch64-asm-2.c: Regenerated.
1013 * aarch64-dis-2.c: Regenerated.
1014 * aarch64-opc-2.c: Regenerated.
1015
e409955d
FS		 10162020-04-17 Fredrik Strupe <fredrik@strupe.net>
1017
1018 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1019 (print_insn_neon): Support disassembly of conditional
1020 instructions.
1021
c54a9b56
DF		 10222020-02-16 David Faust <david.faust@oracle.com>
1023
1024 * bpf-desc.c: Regenerate.
1025 * bpf-desc.h: Likewise.
1026 * bpf-opc.c: Regenerate.
1027 * bpf-opc.h: Likewise.
1028
bb651e8b
CL		 10292020-04-07 Lili Cui <lili.cui@intel.com>
1030
1031 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1032 (prefix_table): New instructions (see prefixes above).
1033 (rm_table): Likewise
1034 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1035 CPU_ANY_TSXLDTRK_FLAGS.
1036 (cpu_flags): Add CpuTSXLDTRK.
1037 * i386-opc.h (enum): Add CpuTSXLDTRK.
1038 (i386_cpu_flags): Add cputsxldtrk.
1039 * i386-opc.tbl: Add XSUSPLDTRK insns.
1040 * i386-init.h: Regenerate.
1041 * i386-tbl.h: Likewise.
1042
4b27d27c
L		 10432020-04-02 Lili Cui <lili.cui@intel.com>
1044
1045 * i386-dis.c (prefix_table): New instructions serialize.
1046 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1047 CPU_ANY_SERIALIZE_FLAGS.
1048 (cpu_flags): Add CpuSERIALIZE.
1049 * i386-opc.h (enum): Add CpuSERIALIZE.
1050 (i386_cpu_flags): Add cpuserialize.
1051 * i386-opc.tbl: Add SERIALIZE insns.
1052 * i386-init.h: Regenerate.
1053 * i386-tbl.h: Likewise.
1054
832a5807
AM		 10552020-03-26 Alan Modra <amodra@gmail.com>
1056
1057 * disassemble.h (opcodes_assert): Declare.
1058 (OPCODES_ASSERT): Define.
1059 * disassemble.c: Don't include assert.h. Include opintl.h.
1060 (opcodes_assert): New function.
1061 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1062 (bfd_h8_disassemble): Reduce size of data array. Correctly
1063 calculate maxlen. Omit insn decoding when insn length exceeds
1064 maxlen. Exit from nibble loop when looking for E, before
1065 accessing next data byte. Move processing of E outside loop.
1066 Replace tests of maxlen in loop with assertions.
1067
4c4addbe
AM		 10682020-03-26 Alan Modra <amodra@gmail.com>
1069
1070 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1071
a18cd0ca
AM		 10722020-03-25 Alan Modra <amodra@gmail.com>
1073
1074 * z80-dis.c (suffix): Init mybuf.
1075
57cb32b3
AM		 10762020-03-22 Alan Modra <amodra@gmail.com>
1077
1078 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1079 successflly read from section.
1080
beea5cc1
AM		 10812020-03-22 Alan Modra <amodra@gmail.com>
1082
1083 * arc-dis.c (find_format): Use ISO C string concatenation rather
1084 than line continuation within a string. Don't access needs_limm
1085 before testing opcode != NULL.
1086
03704c77
AM		 10872020-03-22 Alan Modra <amodra@gmail.com>
1088
1089 * ns32k-dis.c (print_insn_arg): Update comment.
1090 (print_insn_ns32k): Reduce size of index_offset array, and
1091 initialize, passing -1 to print_insn_arg for args that are not
1092 an index. Don't exit arg loop early. Abort on bad arg number.
1093
d1023b5d
AM		 10942020-03-22 Alan Modra <amodra@gmail.com>
1095
1096 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1097 * s12z-opc.c: Formatting.
1098 (operands_f): Return an int.
1099 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1100 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1101 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1102 (exg_sex_discrim): Likewise.
1103 (create_immediate_operand, create_bitfield_operand),
1104 (create_register_operand_with_size, create_register_all_operand),
1105 (create_register_all16_operand, create_simple_memory_operand),
1106 (create_memory_operand, create_memory_auto_operand): Don't
1107 segfault on malloc failure.
1108 (z_ext24_decode): Return an int status, negative on fail, zero
1109 on success.
1110 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1111 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1112 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1113 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1114 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1115 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1116 (loop_primitive_decode, shift_decode, psh_pul_decode),
1117 (bit_field_decode): Similarly.
1118 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1119 to return value, update callers.
1120 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1121 Don't segfault on NULL operand.
1122 (decode_operation): Return OP_INVALID on first fail.
1123 (decode_s12z): Check all reads, returning -1 on fail.
1124
340f3ac8
AM		 11252020-03-20 Alan Modra <amodra@gmail.com>
1126
1127 * metag-dis.c (print_insn_metag): Don't ignore status from
1128 read_memory_func.
1129
fe90ae8a
AM		 11302020-03-20 Alan Modra <amodra@gmail.com>
1131
1132 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1133 Initialize parts of buffer not written when handling a possible
1134 2-byte insn at end of section. Don't attempt decoding of such
1135 an insn by the 4-byte machinery.
1136
833d919c
AM		 11372020-03-20 Alan Modra <amodra@gmail.com>
1138
1139 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1140 partially filled buffer. Prevent lookup of 4-byte insns when
1141 only VLE 2-byte insns are possible due to section size. Print
1142 ".word" rather than ".long" for 2-byte leftovers.
1143
327ef784
NC		 11442020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1145
1146 PR 25641
1147 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1148
1673df32
JB		 11492020-03-13 Jan Beulich <jbeulich@suse.com>
1150
1151 * i386-dis.c (X86_64_0D): Rename to ...
1152 (X86_64_0E): ... this.
1153
384f3689
L		 11542020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1155
1156 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1157 * Makefile.in: Regenerated.
1158
865e2027
JB		 11592020-03-09 Jan Beulich <jbeulich@suse.com>
1160
1161 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1162 3-operand pseudos.
1163 * i386-tbl.h: Re-generate.
1164
2f13234b
JB		 11652020-03-09 Jan Beulich <jbeulich@suse.com>
1166
1167 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1168 vprot*, vpsha*, and vpshl*.
1169 * i386-tbl.h: Re-generate.
1170
3fabc179
JB		 11712020-03-09 Jan Beulich <jbeulich@suse.com>
1172
1173 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1174 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1175 * i386-tbl.h: Re-generate.
1176
3677e4c1
JB		 11772020-03-09 Jan Beulich <jbeulich@suse.com>
1178
1179 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1180 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1181 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1182 * i386-tbl.h: Re-generate.
1183
4c4898e8
JB		 11842020-03-09 Jan Beulich <jbeulich@suse.com>
1185
1186 * i386-gen.c (struct template_arg, struct template_instance,
1187 struct template_param, struct template, templates,
1188 parse_template, expand_templates): New.
1189 (process_i386_opcodes): Various local variables moved to
1190 expand_templates. Call parse_template and expand_templates.
1191 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1192 * i386-tbl.h: Re-generate.
1193
bc49bfd8
JB		 11942020-03-06 Jan Beulich <jbeulich@suse.com>
1195
1196 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1197 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1198 register and memory source templates. Replace VexW= by VexW*
1199 where applicable.
1200 * i386-tbl.h: Re-generate.
1201
4873e243
JB		 12022020-03-06 Jan Beulich <jbeulich@suse.com>
1203
1204 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1205 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1206 * i386-tbl.h: Re-generate.
1207
672a349b
JB		 12082020-03-06 Jan Beulich <jbeulich@suse.com>
1209
1210 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1211 * i386-tbl.h: Re-generate.
1212
4ed21b58
JB		 12132020-03-06 Jan Beulich <jbeulich@suse.com>
1214
1215 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1216 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1217 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1218 VexW0 on SSE2AVX variants.
1219 (vmovq): Drop NoRex64 from XMM/XMM variants.
1220 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1221 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1222 applicable use VexW0.
1223 * i386-tbl.h: Re-generate.
1224
643bb870
JB		 12252020-03-06 Jan Beulich <jbeulich@suse.com>
1226
1227 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1228 * i386-opc.h (Rex64): Delete.
1229 (struct i386_opcode_modifier): Remove rex64 field.
1230 * i386-opc.tbl (crc32): Drop Rex64.
1231 Replace Rex64 with Size64 everywhere else.
1232 * i386-tbl.h: Re-generate.
1233
a23b33b3
JB		 12342020-03-06 Jan Beulich <jbeulich@suse.com>
1235
1236 * i386-dis.c (OP_E_memory): Exclude recording of used address
1237 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1238 addressed memory operands for MPX insns.
1239
a0497384
JB		 12402020-03-06 Jan Beulich <jbeulich@suse.com>
1241
1242 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1243 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1244 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1245 (ptwrite): Split into non-64-bit and 64-bit forms.
1246 * i386-tbl.h: Re-generate.
1247
b630c145
JB		 12482020-03-06 Jan Beulich <jbeulich@suse.com>
1249
1250 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1251 template.
1252 * i386-tbl.h: Re-generate.
1253
a847e322
JB		 12542020-03-04 Jan Beulich <jbeulich@suse.com>
1255
1256 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1257 (prefix_table): Move vmmcall here. Add vmgexit.
1258 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1259 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1260 (cpu_flags): Add CpuSEV_ES entry.
1261 * i386-opc.h (CpuSEV_ES): New.
1262 (union i386_cpu_flags): Add cpusev_es field.
1263 * i386-opc.tbl (vmgexit): New.
1264 * i386-init.h, i386-tbl.h: Re-generate.
1265
3cd7f3e3
L		 12662020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1267
1268 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1269 with MnemonicSize.
1270 * i386-opc.h (IGNORESIZE): New.
1271 (DEFAULTSIZE): Likewise.
1272 (IgnoreSize): Removed.
1273 (DefaultSize): Likewise.
1274 (MnemonicSize): New.
1275 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1276 mnemonicsize.
1277 * i386-opc.tbl (IgnoreSize): New.
1278 (DefaultSize): Likewise.
1279 * i386-tbl.h: Regenerated.
1280
b8ba1385
SB		 12812020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1282
1283 PR 25627
1284 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1285 instructions.
1286
10d97a0f
L		 12872020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1288
1289 PR gas/25622
1290 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1291 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1292 * i386-tbl.h: Regenerated.
1293
dc1e8a47
AM		 12942020-02-26 Alan Modra <amodra@gmail.com>
1295
1296 * aarch64-asm.c: Indent labels correctly.
1297 * aarch64-dis.c: Likewise.
1298 * aarch64-gen.c: Likewise.
1299 * aarch64-opc.c: Likewise.
1300 * alpha-dis.c: Likewise.
1301 * i386-dis.c: Likewise.
1302 * nds32-asm.c: Likewise.
1303 * nfp-dis.c: Likewise.
1304 * visium-dis.c: Likewise.
1305
265b4673
CZ		 13062020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1307
1308 * arc-regs.h (int_vector_base): Make it available for all ARC
1309 CPUs.
1310
bd0cf5a6
NC		 13112020-02-20 Nelson Chu <nelson.chu@sifive.com>
1312
1313 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1314 changed.
1315
fa164239
JW		 13162020-02-19 Nelson Chu <nelson.chu@sifive.com>
1317
1318 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1319 c.mv/c.li if rs1 is zero.
1320
272a84b1
L		 13212020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1322
1323 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1324 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1325 CPU_POPCNT_FLAGS.
1326 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1327 * i386-opc.h (CpuABM): Removed.
1328 (CpuPOPCNT): New.
1329 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1330 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1331 popcnt. Remove CpuABM from lzcnt.
1332 * i386-init.h: Regenerated.
1333 * i386-tbl.h: Likewise.
1334
1f730c46
JB		 13352020-02-17 Jan Beulich <jbeulich@suse.com>
1336
1337 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1338 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1339 VexW1 instead of open-coding them.
1340 * i386-tbl.h: Re-generate.
1341
c8f8eebc
JB		 13422020-02-17 Jan Beulich <jbeulich@suse.com>
1343
1344 * i386-opc.tbl (AddrPrefixOpReg): Define.
1345 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1346 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1347 templates. Drop NoRex64.
1348 * i386-tbl.h: Re-generate.
1349
b9915cbc
JB		 13502020-02-17 Jan Beulich <jbeulich@suse.com>
1351
1352 PR gas/6518
1353 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1354 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1355 into Intel syntax instance (with Unpsecified) and AT&T one
1356 (without).
1357 (vcvtneps2bf16): Likewise, along with folding the two so far
1358 separate ones.
1359 * i386-tbl.h: Re-generate.
1360
ce504911
L		 13612020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1362
1363 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1364 CPU_ANY_SSE4A_FLAGS.
1365
dabec65d
AM		 13662020-02-17 Alan Modra <amodra@gmail.com>
1367
1368 * i386-gen.c (cpu_flag_init): Correct last change.
1369
af5c13b0
L		 13702020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1371
1372 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1373 CPU_ANY_SSE4_FLAGS.
1374
6867aac0
L		 13752020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1376
1377 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1378 (movzx): Likewise.
1379
65fca059
JB		 13802020-02-14 Jan Beulich <jbeulich@suse.com>
1381
1382 PR gas/25438
1383 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1384 destination for Cpu64-only variant.
1385 (movzx): Fold patterns.
1386 * i386-tbl.h: Re-generate.
1387
7deea9aa
JB		 13882020-02-13 Jan Beulich <jbeulich@suse.com>
1389
1390 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1391 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1392 CPU_ANY_SSE4_FLAGS entry.
1393 * i386-init.h: Re-generate.
1394
6c0946d0
JB		 13952020-02-12 Jan Beulich <jbeulich@suse.com>
1396
1397 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1398 with Unspecified, making the present one AT&T syntax only.
1399 * i386-tbl.h: Re-generate.
1400
ddb56fe6
JB		 14012020-02-12 Jan Beulich <jbeulich@suse.com>
1402
1403 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1404 * i386-tbl.h: Re-generate.
1405
5990e377
JB		 14062020-02-12 Jan Beulich <jbeulich@suse.com>
1407
1408 PR gas/24546
1409 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1410 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1411 Amd64 and Intel64 templates.
1412 (call, jmp): Likewise for far indirect variants. Dro
1413 Unspecified.
1414 * i386-tbl.h: Re-generate.
1415
50128d0c
JB		 14162020-02-11 Jan Beulich <jbeulich@suse.com>
1417
1418 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1419 * i386-opc.h (ShortForm): Delete.
1420 (struct i386_opcode_modifier): Remove shortform field.
1421 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1422 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1423 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1424 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1425 Drop ShortForm.
1426 * i386-tbl.h: Re-generate.
1427
1e05b5c4
JB		 14282020-02-11 Jan Beulich <jbeulich@suse.com>
1429
1430 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1431 fucompi): Drop ShortForm from operand-less templates.
1432 * i386-tbl.h: Re-generate.
1433
2f5dd314
AM		 14342020-02-11 Alan Modra <amodra@gmail.com>
1435
1436 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1437 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1438 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1439 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1440 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1441
5aae9ae9
MM		 14422020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1443
1444 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1445 (cde_opcodes): Add VCX* instructions.
1446
4934a27c
MM		 14472020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1448 Matthew Malcomson <matthew.malcomson@arm.com>
1449
1450 * arm-dis.c (struct cdeopcode32): New.
1451 (CDE_OPCODE): New macro.
1452 (cde_opcodes): New disassembly table.
1453 (regnames): New option to table.
1454 (cde_coprocs): New global variable.
1455 (print_insn_cde): New
1456 (print_insn_thumb32): Use print_insn_cde.
1457 (parse_arm_disassembler_options): Parse coprocN args.
1458
4b5aaf5f
L		 14592020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1460
1461 PR gas/25516
1462 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1463 with ISA64.
1464 * i386-opc.h (AMD64): Removed.
1465 (Intel64): Likewose.
1466 (AMD64): New.
1467 (INTEL64): Likewise.
1468 (INTEL64ONLY): Likewise.
1469 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1470 * i386-opc.tbl (Amd64): New.
1471 (Intel64): Likewise.
1472 (Intel64Only): Likewise.
1473 Replace AMD64 with Amd64. Update sysenter/sysenter with
1474 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1475 * i386-tbl.h: Regenerated.
1476
9fc0b501
SB		 14772020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1478
1479 PR 25469
1480 * z80-dis.c: Add support for GBZ80 opcodes.
1481
c5d7be0c
AM		 14822020-02-04 Alan Modra <amodra@gmail.com>
1483
1484 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1485
44e4546f
AM		 14862020-02-03 Alan Modra <amodra@gmail.com>
1487
1488 * m32c-ibld.c: Regenerate.
1489
b2b1453a
AM		 14902020-02-01 Alan Modra <amodra@gmail.com>
1491
1492 * frv-ibld.c: Regenerate.
1493
4102be5c
JB		 14942020-01-31 Jan Beulich <jbeulich@suse.com>
1495
1496 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1497 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1498 (OP_E_memory): Replace xmm_mdq_mode case label by
1499 vex_scalar_w_dq_mode one.
1500 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1501
825bd36c
JB		 15022020-01-31 Jan Beulich <jbeulich@suse.com>
1503
1504 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1505 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1506 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1507 (intel_operand_size): Drop vex_w_dq_mode case label.
1508
c3036ed0
RS		 15092020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1510
1511 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1512 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1513
0c115f84
AM		 15142020-01-30 Alan Modra <amodra@gmail.com>
1515
1516 * m32c-ibld.c: Regenerate.
1517
bd434cc4
JM		 15182020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1519
1520 * bpf-opc.c: Regenerate.
1521
aeab2b26
JB		 15222020-01-30 Jan Beulich <jbeulich@suse.com>
1523
1524 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1525 (dis386): Use them to replace C2/C3 table entries.
1526 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1527 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1528 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1529 * i386-tbl.h: Re-generate.
1530
62b3f548
JB		 15312020-01-30 Jan Beulich <jbeulich@suse.com>
1532
1533 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1534 forms.
1535 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1536 DefaultSize.
1537 * i386-tbl.h: Re-generate.
1538
1bd8ae10
AM		 15392020-01-30 Alan Modra <amodra@gmail.com>
1540
1541 * tic4x-dis.c (tic4x_dp): Make unsigned.
1542
bc31405e
L		 15432020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1544 Jan Beulich <jbeulich@suse.com>
1545
1546 PR binutils/25445
1547 * i386-dis.c (MOVSXD_Fixup): New function.
1548 (movsxd_mode): New enum.
1549 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1550 (intel_operand_size): Handle movsxd_mode.
1551 (OP_E_register): Likewise.
1552 (OP_G): Likewise.
1553 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1554 register on movsxd. Add movsxd with 16-bit destination register
1555 for AMD64 and Intel64 ISAs.
1556 * i386-tbl.h: Regenerated.
1557
7568c93b
TC		 15582020-01-27 Tamar Christina <tamar.christina@arm.com>
1559
1560 PR 25403
1561 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1562 * aarch64-asm-2.c: Regenerate
1563 * aarch64-dis-2.c: Likewise.
1564 * aarch64-opc-2.c: Likewise.
1565
c006a730
JB		 15662020-01-21 Jan Beulich <jbeulich@suse.com>
1567
1568 * i386-opc.tbl (sysret): Drop DefaultSize.
1569 * i386-tbl.h: Re-generate.
1570
c906a69a
JB		 15712020-01-21 Jan Beulich <jbeulich@suse.com>
1572
1573 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1574 Dword.
1575 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1576 * i386-tbl.h: Re-generate.
1577
26916852
NC		 15782020-01-20 Nick Clifton <nickc@redhat.com>
1579
1580 * po/de.po: Updated German translation.
1581 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1582 * po/uk.po: Updated Ukranian translation.
1583
4d6cbb64
AM		 15842020-01-20 Alan Modra <amodra@gmail.com>
1585
1586 * hppa-dis.c (fput_const): Remove useless cast.
1587
2bddb71a
AM		 15882020-01-20 Alan Modra <amodra@gmail.com>
1589
1590 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1591
1b1bb2c6
NC		 15922020-01-18 Nick Clifton <nickc@redhat.com>
1593
1594 * configure: Regenerate.
1595 * po/opcodes.pot: Regenerate.
1596
ae774686
NC		 15972020-01-18 Nick Clifton <nickc@redhat.com>
1598
1599 Binutils 2.34 branch created.
1600
07f1f3aa
CB		 16012020-01-17 Christian Biesinger <cbiesinger@google.com>
1602
1603 * opintl.h: Fix spelling error (seperate).
1604
42e04b36
L		 16052020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1606
1607 * i386-opc.tbl: Add {vex} pseudo prefix.
1608 * i386-tbl.h: Regenerated.
1609
2da2eaf4
AV		 16102020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1611
1612 PR 25376
1613 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1614 (neon_opcodes): Likewise.
1615 (select_arm_features): Make sure we enable MVE bits when selecting
1616 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1617 any architecture.
1618
d0849eed
JB		 16192020-01-16 Jan Beulich <jbeulich@suse.com>
1620
1621 * i386-opc.tbl: Drop stale comment from XOP section.
1622
9cf70a44
JB		 16232020-01-16 Jan Beulich <jbeulich@suse.com>
1624
1625 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1626 (extractps): Add VexWIG to SSE2AVX forms.
1627 * i386-tbl.h: Re-generate.
1628
4814632e
JB		 16292020-01-16 Jan Beulich <jbeulich@suse.com>
1630
1631 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1632 Size64 from and use VexW1 on SSE2AVX forms.
1633 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1634 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1635 * i386-tbl.h: Re-generate.
1636
aad09917
AM		 16372020-01-15 Alan Modra <amodra@gmail.com>
1638
1639 * tic4x-dis.c (tic4x_version): Make unsigned long.
1640 (optab, optab_special, registernames): New file scope vars.
1641 (tic4x_print_register): Set up registernames rather than
1642 malloc'd registertable.
1643 (tic4x_disassemble): Delete optable and optable_special. Use
1644 optab and optab_special instead. Throw away old optab,
1645 optab_special and registernames when info->mach changes.
1646
7a6bf3be
SB		 16472020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1648
1649 PR 25377
1650 * z80-dis.c (suffix): Use .db instruction to generate double
1651 prefix.
1652
ca1eaac0
AM		 16532020-01-14 Alan Modra <amodra@gmail.com>
1654
1655 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1656 values to unsigned before shifting.
1657
1d67fe3b
TT		 16582020-01-13 Thomas Troeger <tstroege@gmx.de>
1659
1660 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1661 flow instructions.
1662 (print_insn_thumb16, print_insn_thumb32): Likewise.
1663 (print_insn): Initialize the insn info.
1664 * i386-dis.c (print_insn): Initialize the insn info fields, and
1665 detect jumps.
1666
5e4f7e05
CZ		 16672012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1668
1669 * arc-opc.c (C_NE): Make it required.
1670
b9fe6b8a
CZ		 16712012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1672
1673 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1674 reserved register name.
1675
90dee485
AM		 16762020-01-13 Alan Modra <amodra@gmail.com>
1677
1678 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1679 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1680
febda64f
AM		 16812020-01-13 Alan Modra <amodra@gmail.com>
1682
1683 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1684 result of wasm_read_leb128 in a uint64_t and check that bits
1685 are not lost when copying to other locals. Use uint32_t for
1686 most locals. Use PRId64 when printing int64_t.
1687
df08b588
AM		 16882020-01-13 Alan Modra <amodra@gmail.com>
1689
1690 * score-dis.c: Formatting.
1691 * score7-dis.c: Formatting.
1692
b2c759ce
AM		 16932020-01-13 Alan Modra <amodra@gmail.com>
1694
1695 * score-dis.c (print_insn_score48): Use unsigned variables for
1696 unsigned values. Don't left shift negative values.
1697 (print_insn_score32): Likewise.
1698 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1699
5496abe1
AM		 17002020-01-13 Alan Modra <amodra@gmail.com>
1701
1702 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1703
202e762b
AM		 17042020-01-13 Alan Modra <amodra@gmail.com>
1705
1706 * fr30-ibld.c: Regenerate.
1707
7ef412cf
AM		 17082020-01-13 Alan Modra <amodra@gmail.com>
1709
1710 * xgate-dis.c (print_insn): Don't left shift signed value.
1711 (ripBits): Formatting, use 1u.
1712
7f578b95
AM		 17132020-01-10 Alan Modra <amodra@gmail.com>
1714
1715 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1716 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1717
441af85b
AM		 17182020-01-10 Alan Modra <amodra@gmail.com>
1719
1720 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1721 and XRREG value earlier to avoid a shift with negative exponent.
1722 * m10200-dis.c (disassemble): Similarly.
1723
bce58db4
NC		 17242020-01-09 Nick Clifton <nickc@redhat.com>
1725
1726 PR 25224
1727 * z80-dis.c (ld_ii_ii): Use correct cast.
1728
40c75bc8
SB		 17292020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1730
1731 PR 25224
1732 * z80-dis.c (ld_ii_ii): Use character constant when checking
1733 opcode byte value.
1734
d835a58b
JB		 17352020-01-09 Jan Beulich <jbeulich@suse.com>
1736
1737 * i386-dis.c (SEP_Fixup): New.
1738 (SEP): Define.
1739 (dis386_twobyte): Use it for sysenter/sysexit.
1740 (enum x86_64_isa): Change amd64 enumerator to value 1.
1741 (OP_J): Compare isa64 against intel64 instead of amd64.
1742 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1743 forms.
1744 * i386-tbl.h: Re-generate.
1745
030a2e78
AM		 17462020-01-08 Alan Modra <amodra@gmail.com>
1747
1748 * z8k-dis.c: Include libiberty.h
1749 (instr_data_s): Make max_fetched unsigned.
1750 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1751 Don't exceed byte_info bounds.
1752 (output_instr): Make num_bytes unsigned.
1753 (unpack_instr): Likewise for nibl_count and loop.
1754 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1755 idx unsigned.
1756 * z8k-opc.h: Regenerate.
1757
bb82aefe
SV		 17582020-01-07 Shahab Vahedi <shahab@synopsys.com>
1759
1760 * arc-tbl.h (llock): Use 'LLOCK' as class.
1761 (llockd): Likewise.
1762 (scond): Use 'SCOND' as class.
1763 (scondd): Likewise.
1764 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1765 (scondd): Likewise.
1766
cc6aa1a6
AM		 17672020-01-06 Alan Modra <amodra@gmail.com>
1768
1769 * m32c-ibld.c: Regenerate.
1770
660e62b1
AM		 17712020-01-06 Alan Modra <amodra@gmail.com>
1772
1773 PR 25344
1774 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1775 Peek at next byte to prevent recursion on repeated prefix bytes.
1776 Ensure uninitialised "mybuf" is not accessed.
1777 (print_insn_z80): Don't zero n_fetch and n_used here,..
1778 (print_insn_z80_buf): ..do it here instead.
1779
c9ae58fe
AM		 17802020-01-04 Alan Modra <amodra@gmail.com>
1781
1782 * m32r-ibld.c: Regenerate.
1783
5f57d4ec
AM		 17842020-01-04 Alan Modra <amodra@gmail.com>
1785
1786 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1787
2c5c1196
AM		 17882020-01-04 Alan Modra <amodra@gmail.com>
1789
1790 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1791
2e98c6c5
AM		 17922020-01-04 Alan Modra <amodra@gmail.com>
1793
1794 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1795
567dfba2
JB		 17962020-01-03 Jan Beulich <jbeulich@suse.com>
1797
5437a02a
JB		 1798 * aarch64-tbl.h (aarch64_opcode_table): Use
1799 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1800
18012020-01-03 Jan Beulich <jbeulich@suse.com>
1802
1803 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1804 forms of SUDOT and USDOT.
1805
8c45011a
JB		 18062020-01-03 Jan Beulich <jbeulich@suse.com>
1807
5437a02a 1808 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1809 uzip{1,2}.
1810 * opcodes/aarch64-dis-2.c: Re-generate.
1811
f4950f76
JB		 18122020-01-03 Jan Beulich <jbeulich@suse.com>
1813
5437a02a 1814 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1815 FMMLA encoding.
1816 * opcodes/aarch64-dis-2.c: Re-generate.
1817
6655dba2
SB		 18182020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1819
1820 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1821
b14ce8bf
AM		 18222020-01-01 Alan Modra <amodra@gmail.com>
1823
1824 Update year range in copyright notice of all files.
1825
0b114740 1826For older changes see ChangeLog-2019
3499769a 1827\f
0b114740 1828Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1829
1830Copying and distribution of this file, with or without modification,
1831are permitted in any medium without royalty provided the copyright
1832notice and this notice are preserved.
1833
1834Local Variables:
1835mode: change-log
1836left-margin: 8
1837fill-column: 74
1838version-control: never
1839End:
GDB Binutils - Deliverables
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