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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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622b9eb1
MW		 12015-11-27 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-dis-2.c: Regenerate.
5 * aarch64-opc-2.c: Regenerate.
6 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
7 (QL_INT2FP_H, QL_FP2INT_H): New.
8 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
9 (QL_DST_H): New.
10 (QL_FCCMP_H): New.
11 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
12 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
13 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
14 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
15 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
16 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
17 fcsel.
18
cf86120b
MW		 192015-11-27 Matthew Wahab <matthew.wahab@arm.com>
20
21 * aarch64-opc.c (half_conv_t): New.
22 (expand_fp_imm): Replace is_dp flag with the parameter size to
23 specify the number of bytes for the required expansion. Treat
24 a 16-bit expansion like a 32-bit expansion. Add check for an
25 unsupported size request. Update comment.
26 (aarch64_print_operand): Update to support 16-bit floating point
27 values. Update for changes to expand_fp_imm.
28
3bd894a7
MW		 292015-11-27 Matthew Wahab <matthew.wahab@arm.com>
30
31 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
32 (FP_F16): New.
33
64357d2e
MW		 342015-11-27 Matthew Wahab <matthew.wahab@arm.com>
35
36 * aarch64-asm-2.c: Regenerate.
37 * aarch64-dis-2.c: Regenerate.
38 * aarch64-opc-2.c: Regenerate.
39 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
40 "rev64".
41
d685192a
MW		 422015-11-27 Matthew Wahab <matthew.wahab@arm.com>
43
44 * aarch64-asm-2.c: Regenerate.
45 * aarch64-asm.c (convert_bfc_to_bfm): New.
46 (convert_to_real): Add case for OP_BFC.
47 * aarch64-dis-2.c: Regenerate.
48 * aarch64-dis.c: (convert_bfm_to_bfc): New.
49 (convert_to_alias): Add case for OP_BFC.
50 * aarch64-opc-2.c: Regenerate.
51 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
52 to allow width operand in three-operand instructions.
53 * aarch64-tbl.h (QL_BF1): New.
54 (aarch64_feature_v8_2): New.
55 (ARMV8_2): New.
56 (aarch64_opcode_table): Add "bfc".
57
35822b38
MW		 582015-11-27 Matthew Wahab <matthew.wahab@arm.com>
59
60 * aarch64-asm-2.c: Regenerate.
61 * aarch64-dis-2.c: Regenerate.
62 * aarch64-dis.c: Weaken assert.
63 * aarch64-gen.c: Include the instruction in the list of its
64 possible aliases.
65
1a04d1a7
MW		 662015-11-27 Matthew Wahab <matthew.wahab@arm.com>
67
68 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
69 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
70 feature test.
71
e49d43ff
TG		 722015-11-23 Tristan Gingold <gingold@adacore.com>
73
74 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
75
250aafa4
MW		 762015-11-20 Matthew Wahab <matthew.wahab@arm.com>
77
78 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
79 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
80 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
81 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
82 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
83 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
84 cnthv_ctl_el2, cnthv_cval_el2.
85 (aarch64_sys_reg_supported_p): Update for the new system
86 registers.
87
a915c10f
NC		 882015-11-20 Nick Clifton <nickc@redhat.com>
89
90 PR binutils/19224
91 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
92
f8c2a965
NC		 932015-11-20 Nick Clifton <nickc@redhat.com>
94
95 * po/zh_CN.po: Updated simplified Chinese translation.
96
c2825638
MW		 972015-11-19 Matthew Wahab <matthew.wahab@arm.com>
98
99 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
100 of MSR PAN immediate operand.
101
e7286c56
NC		 1022015-11-16 Nick Clifton <nickc@redhat.com>
103
104 * rx-dis.c (condition_names): Replace always and never with
105 invalid, since the always/never conditions can never be legal.
106
d8bd95ef
TG		 1072015-11-13 Tristan Gingold <gingold@adacore.com>
108
109 * configure: Regenerate.
110
a680de9a
PB		 1112015-11-11 Alan Modra <amodra@gmail.com>
112 Peter Bergner <bergner@vnet.ibm.com>
113
114 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
115 Add PPC_OPCODE_VSX3 to the vsx entry.
116 (powerpc_init_dialect): Set default dialect to power9.
117 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
118 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
119 extract_l1 insert_xtq6, extract_xtq6): New static functions.
120 (insert_esync): Test for illegal L operand value.
121 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
122 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
123 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
124 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
125 PPCVSX3): New defines.
126 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
127 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
128 <mcrxr>: Use XBFRARB_MASK.
129 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
130 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
131 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
132 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
133 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
134 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
135 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
136 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
137 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
138 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
139 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
140 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
141 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
142 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
143 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
144 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
145 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
146 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
147 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
148 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
149 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
150 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
151 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
152 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
153 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
154 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
155 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
156 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
157 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
158 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
159 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
160 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
161
854eb72b
NC		 1622015-11-02 Nick Clifton <nickc@redhat.com>
163
164 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
165 instructions.
166 * rx-decode.c: Regenerate.
167
e292aa7a
NC		 1682015-11-02 Nick Clifton <nickc@redhat.com>
169
170 * rx-decode.opc (rx_disp): If the displacement is zero, set the
171 type to RX_Operand_Zero_Indirect.
172 * rx-decode.c: Regenerate.
173 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
174
43cdf5ae
YQ		 1752015-10-28 Yao Qi <yao.qi@linaro.org>
176
177 * aarch64-dis.c (aarch64_decode_insn): Add one argument
178 noaliases_p. Update comments. Pass noaliases_p rather than
179 no_aliases to aarch64_opcode_decode.
180 (print_insn_aarch64_word): Pass no_aliases to
181 aarch64_decode_insn.
182
c2f28758
VK		 1832015-10-27 Vinay <Vinay.G@kpit.com>
184
185 PR binutils/19159
186 * rl78-decode.opc (MOV): Added offset to DE register in index
187 addressing mode.
188 * rl78-decode.c: Regenerate.
189
46662804
VK		 1902015-10-27 Vinay Kumar <vinay.g@kpit.com>
191
192 PR binutils/19158
193 * rl78-decode.opc: Add 's' print operator to instructions that
194 access system registers.
195 * rl78-decode.c: Regenerate.
196 * rl78-dis.c (print_insn_rl78_common): Decode all system
197 registers.
198
02f12cd4
VK		 1992015-10-27 Vinay Kumar <vinay.g@kpit.com>
200
201 PR binutils/19157
202 * rl78-decode.opc: Add 'a' print operator to mov instructions
203 using stack pointer plus index addressing.
204 * rl78-decode.c: Regenerate.
205
485f23cf
AK		 2062015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
207
208 * s390-opc.c: Fix comment.
209 * s390-opc.txt: Change instruction type for troo, trot, trto, and
210 trtt to RRF_U0RER since the second parameter does not need to be a
211 register pair.
212
3f94e60d
NC		 2132015-10-08 Nick Clifton <nickc@redhat.com>
214
215 * arc-dis.c (print_insn_arc): Initiallise insn array.
216
875880c6
YQ		 2172015-10-07 Yao Qi <yao.qi@linaro.org>
218
219 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
220 'name' rather than 'template'.
221 * aarch64-opc.c (aarch64_print_operand): Likewise.
222
886a2506
NC		 2232015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
224
225 * arc-dis.c: Revamped file for ARC support
226 * arc-dis.h: Likewise.
227 * arc-ext.c: Likewise.
228 * arc-ext.h: Likewise.
229 * arc-opc.c: Likewise.
230 * arc-fxi.h: New file.
231 * arc-regs.h: Likewise.
232 * arc-tbl.h: Likewise.
233
36f4aab1
YQ		 2342015-10-02 Yao Qi <yao.qi@linaro.org>
235
236 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
237 argument insn type to aarch64_insn. Rename to ...
238 (aarch64_decode_insn): ... it.
239 (print_insn_aarch64_word): Caller updated.
240
7232d389
YQ		 2412015-10-02 Yao Qi <yao.qi@linaro.org>
242
243 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
244 (print_insn_aarch64_word): Caller updated.
245
7ecc513a
DV		 2462015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
247
248 * s390-mkopc.c (main): Parse htm and vx flag.
249 * s390-opc.txt: Mark instructions from the hardware transactional
250 memory and vector facilities with the "htm"/"vx" flag.
251
b08b78e7
NC		 2522015-09-28 Nick Clifton <nickc@redhat.com>
253
254 * po/de.po: Updated German translation.
255
36f7a941
TR		 2562015-09-28 Tom Rix <tom@bumblecow.com>
257
258 * ppc-opc.c (PPC500): Mark some opcodes as invalid
259
b6518b38
NC		 2602015-09-23 Nick Clifton <nickc@redhat.com>
261
262 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
263 function.
264 * tic30-dis.c (print_branch): Likewise.
265 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
266 value before left shifting.
267 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
268 * hppa-dis.c (print_insn_hppa): Likewise.
269 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
270 array.
271 * msp430-dis.c (msp430_singleoperand): Likewise.
272 (msp430_doubleoperand): Likewise.
273 (print_insn_msp430): Likewise.
274 * nds32-asm.c (parse_operand): Likewise.
275 * sh-opc.h (MASK): Likewise.
276 * v850-dis.c (get_operand_value): Likewise.
277
f04265ec
NC		 2782015-09-22 Nick Clifton <nickc@redhat.com>
279
280 * rx-decode.opc (bwl): Use RX_Bad_Size.
281 (sbwl): Likewise.
282 (ubwl): Likewise. Rename to ubw.
283 (uBWL): Rename to uBW.
284 Replace all references to uBWL with uBW.
285 * rx-decode.c: Regenerate.
286 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
287 (opsize_names): Likewise.
288 (print_insn_rx): Detect and report RX_Bad_Size.
289
6dca4fd1
AB		 2902015-09-22 Anton Blanchard <anton@samba.org>
291
292 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
293
38074311
JM		 2942015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
295
296 * sparc-dis.c (print_insn_sparc): Handle the privileged register
297 %pmcdper.
298
5f40e14d
JS		 2992015-08-24 Jan Stancek <jstancek@redhat.com>
300
301 * i386-dis.c (print_insn): Fix decoding of three byte operands.
302
ab4e4ed5
AF		 3032015-08-21 Alexander Fomin <alexander.fomin@intel.com>
304
305 PR binutils/18257
306 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
307 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
308 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
309 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
310 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
311 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
312 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
313 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
314 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
315 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
316 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
317 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
318 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
319 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
320 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
321 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
322 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
323 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
324 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
325 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
326 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
327 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
328 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
329 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
330 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
331 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
332 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
333 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
334 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
335 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
336 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
337 (vex_w_table): Replace terminals with MOD_TABLE entries for
338 most of mask instructions.
339
919b75f7
AM		 3402015-08-17 Alan Modra <amodra@gmail.com>
341
342 * cgen.sh: Trim trailing space from cgen output.
343 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
344 (print_dis_table): Likewise.
345 * opc2c.c (dump_lines): Likewise.
346 (orig_filename): Warning fix.
347 * ia64-asmtab.c: Regenerate.
348
4ab90a7a
AV		 3492015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
350
351 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
352 and higher with ARM instruction set will now mark the 26-bit
353 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
354 (arm_opcodes): Fix for unpredictable nop being recognized as a
355 teq.
356
40fc1451
SD		 3572015-08-12 Simon Dardis <simon.dardis@imgtec.com>
358
359 * micromips-opc.c (micromips_opcodes): Re-order table so that move
360 based on 'or' is first.
361 * mips-opc.c (mips_builtin_opcodes): Ditto.
362
922c5db5
NC		 3632015-08-11 Nick Clifton <nickc@redhat.com>
364
365 PR 18800
366 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
367 instruction.
368
75fb7498
RS		 3692015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
370
371 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
372
36aed29d
AP		 3732015-08-07 Amit Pawar <Amit.Pawar@amd.com>
374
375 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
376 * i386-init.h: Regenerated.
377
a8484f96
L		 3782015-07-30 H.J. Lu <hongjiu.lu@intel.com>
379
380 PR binutils/13571
381 * i386-dis.c (MOD_0FC3): New.
382 (PREFIX_0FC3): Renamed to ...
383 (PREFIX_MOD_0_0FC3): This.
384 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
385 (prefix_table): Replace Ma with Ev on movntiS.
386 (mod_table): Add MOD_0FC3.
387
37a42ee9
L		 3882015-07-27 H.J. Lu <hongjiu.lu@intel.com>
389
390 * configure: Regenerated.
391
070fe95d
AM		 3922015-07-23 Alan Modra <amodra@gmail.com>
393
394 PR 18708
395 * i386-dis.c (get64): Avoid signed integer overflow.
396
20c2a615
L		 3972015-07-22 Alexander Fomin <alexander.fomin@intel.com>
398
399 PR binutils/18631
400 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
401 "EXEvexHalfBcstXmmq" for the second operand.
402 (EVEX_W_0F79_P_2): Likewise.
403 (EVEX_W_0F7A_P_2): Likewise.
404 (EVEX_W_0F7B_P_2): Likewise.
405
6f1c2142
AM		 4062015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
407
408 * arm-dis.c (print_insn_coprocessor): Added support for quarter
409 float bitfield format.
410 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
411 quarter float bitfield format.
412
8a643cc3
L		 4132015-07-14 H.J. Lu <hongjiu.lu@intel.com>
414
415 * configure: Regenerated.
416
ef5a96d5
AM		 4172015-07-03 Alan Modra <amodra@gmail.com>
418
419 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
420 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
421 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
422
c8c8175b
SL		 4232015-07-01 Sandra Loosemore <sandra@codesourcery.com>
424 Cesar Philippidis <cesar@codesourcery.com>
425
426 * nios2-dis.c (nios2_extract_opcode): New.
427 (nios2_disassembler_state): New.
428 (nios2_find_opcode_hash): Use mach parameter to select correct
429 disassembler state.
430 (nios2_print_insn_arg): Extend to support new R2 argument letters
431 and formats.
432 (print_insn_nios2): Check for 16-bit instruction at end of memory.
433 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
434 (NIOS2_NUM_OPCODES): Rename to...
435 (NIOS2_NUM_R1_OPCODES): This.
436 (nios2_r2_opcodes): New.
437 (NIOS2_NUM_R2_OPCODES): New.
438 (nios2_num_r2_opcodes): New.
439 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
440 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
441 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
442 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
443 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
444
9916071f
AP		 4452015-06-30 Amit Pawar <Amit.Pawar@amd.com>
446
447 * i386-dis.c (OP_Mwaitx): New.
448 (rm_table): Add monitorx/mwaitx.
449 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
450 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
451 (operand_type_init): Add CpuMWAITX.
452 * i386-opc.h (CpuMWAITX): New.
453 (i386_cpu_flags): Add cpumwaitx.
454 * i386-opc.tbl: Add monitorx and mwaitx.
455 * i386-init.h: Regenerated.
456 * i386-tbl.h: Likewise.
457
7b934113
PB		 4582015-06-22 Peter Bergner <bergner@vnet.ibm.com>
459
460 * ppc-opc.c (insert_ls): Test for invalid LS operands.
461 (insert_esync): New function.
462 (LS, WC): Use insert_ls.
463 (ESYNC): Use insert_esync.
464
bdc4de1b
NC		 4652015-06-22 Nick Clifton <nickc@redhat.com>
466
467 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
468 requested region lies beyond it.
469 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
470 looking for 32-bit insns.
471 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
472 data.
473 * sh-dis.c (print_insn_sh): Likewise.
474 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
475 blocks of instructions.
476 * vax-dis.c (print_insn_vax): Check that the requested address
477 does not clash with the stop_vma.
478
11a0cf2e
PB		 4792015-06-19 Peter Bergner <bergner@vnet.ibm.com>
480
070fe95d 481 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 482 * ppc-opc.c (FXM4): Add non-zero optional value.
483 (TBR): Likewise.
484 (SXL): Likewise.
485 (insert_fxm): Handle new default operand value.
486 (extract_fxm): Likewise.
487 (insert_tbr): Likewise.
488 (extract_tbr): Likewise.
489
bdfa8b95
MW		 4902015-06-16 Matthew Wahab <matthew.wahab@arm.com>
491
492 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
493
24b4cf66
SN		 4942015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
495
496 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
497
99a2c561
PB		 4982015-06-12 Peter Bergner <bergner@vnet.ibm.com>
499
500 * ppc-opc.c: Add comment accidentally removed by old commit.
501 (MTMSRD_L): Delete.
502
40f77f82
AM		 5032015-06-04 Peter Bergner <bergner@vnet.ibm.com>
504
505 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
506
13be46a2
NC		 5072015-06-04 Nick Clifton <nickc@redhat.com>
508
509 PR 18474
510 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
511
ddfded2f
MW		 5122015-06-02 Matthew Wahab <matthew.wahab@arm.com>
513
514 * arm-dis.c (arm_opcodes): Add "setpan".
515 (thumb_opcodes): Add "setpan".
516
1af1dd51
MW		 5172015-06-02 Matthew Wahab <matthew.wahab@arm.com>
518
519 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
520 macros.
521
9e1f0fa7
MW		 5222015-06-02 Matthew Wahab <matthew.wahab@arm.com>
523
524 * aarch64-tbl.h (aarch64_feature_rdma): New.
525 (RDMA): New.
526 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
527 * aarch64-asm-2.c: Regenerate.
528 * aarch64-dis-2.c: Regenerate.
529 * aarch64-opc-2.c: Regenerate.
530
290806fd
MW		 5312015-06-02 Matthew Wahab <matthew.wahab@arm.com>
532
533 * aarch64-tbl.h (aarch64_feature_lor): New.
534 (LOR): New.
535 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
536 "stllrb", "stllrh".
537 * aarch64-asm-2.c: Regenerate.
538 * aarch64-dis-2.c: Regenerate.
539 * aarch64-opc-2.c: Regenerate.
540
f21cce2c
MW		 5412015-06-01 Matthew Wahab <matthew.wahab@arm.com>
542
543 * aarch64-opc.c (F_ARCHEXT): New.
544 (aarch64_sys_regs): Add "pan".
545 (aarch64_sys_reg_supported_p): New.
546 (aarch64_pstatefields): Add "pan".
547 (aarch64_pstatefield_supported_p): New.
548
d194d186
JB		 5492015-06-01 Jan Beulich <jbeulich@suse.com>
550
551 * i386-tbl.h: Regenerate.
552
3a8547d2
JB		 5532015-06-01 Jan Beulich <jbeulich@suse.com>
554
555 * i386-dis.c (print_insn): Swap rounding mode specifier and
556 general purpose register in Intel mode.
557
015c54d5
JB		 5582015-06-01 Jan Beulich <jbeulich@suse.com>
559
560 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
561 * i386-tbl.h: Regenerate.
562
071f0063
L		 5632015-05-18 H.J. Lu <hongjiu.lu@intel.com>
564
565 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
566 * i386-init.h: Regenerated.
567
5db04b09
L		 5682015-05-15 H.J. Lu <hongjiu.lu@intel.com>
569
570 PR binutis/18386
571 * i386-dis.c: Add comments for '@'.
572 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
573 (enum x86_64_isa): New.
574 (isa64): Likewise.
575 (print_i386_disassembler_options): Add amd64 and intel64.
576 (print_insn): Handle amd64 and intel64.
577 (putop): Handle '@'.
578 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
579 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
580 * i386-opc.h (AMD64): New.
581 (CpuIntel64): Likewise.
582 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
583 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
584 Mark direct call/jmp without Disp16|Disp32 as Intel64.
585 * i386-init.h: Regenerated.
586 * i386-tbl.h: Likewise.
587
4bc0608a
PB		 5882015-05-14 Peter Bergner <bergner@vnet.ibm.com>
589
590 * ppc-opc.c (IH) New define.
591 (powerpc_opcodes) <wait>: Do not enable for POWER7.
592 <tlbie>: Add RS operand for POWER7.
593 <slbia>: Add IH operand for POWER6.
594
70cead07
L		 5952015-05-11 H.J. Lu <hongjiu.lu@intel.com>
596
597 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
598 direct branch.
599 (jmp): Likewise.
600 * i386-tbl.h: Regenerated.
601
7b6d09fb
L		 6022015-05-11 H.J. Lu <hongjiu.lu@intel.com>
603
604 * configure.ac: Support bfd_iamcu_arch.
605 * disassemble.c (disassembler): Support bfd_iamcu_arch.
606 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
607 CPU_IAMCU_COMPAT_FLAGS.
608 (cpu_flags): Add CpuIAMCU.
609 * i386-opc.h (CpuIAMCU): New.
610 (i386_cpu_flags): Add cpuiamcu.
611 * configure: Regenerated.
612 * i386-init.h: Likewise.
613 * i386-tbl.h: Likewise.
614
31955f99
L		 6152015-05-08 H.J. Lu <hongjiu.lu@intel.com>
616
617 PR binutis/18386
618 * i386-dis.c (X86_64_E8): New.
619 (X86_64_E9): Likewise.
620 Update comments on 'T', 'U', 'V'. Add comments for '^'.
621 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
622 (x86_64_table): Add X86_64_E8 and X86_64_E9.
623 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
624 (putop): Handle '^'.
625 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
626 REX_W.
627
0952813b
DD		 6282015-04-30 DJ Delorie <dj@redhat.com>
629
630 * disassemble.c (disassembler): Choose suitable disassembler based
631 on E_ABI.
632 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
633 it to decode mul/div insns.
634 * rl78-decode.c: Regenerate.
635 * rl78-dis.c (print_insn_rl78): Rename to...
636 (print_insn_rl78_common): ...this, take ISA parameter.
637 (print_insn_rl78): New.
638 (print_insn_rl78_g10): New.
639 (print_insn_rl78_g13): New.
640 (print_insn_rl78_g14): New.
641 (rl78_get_disassembler): New.
642
f9d3ecaa
NC		 6432015-04-29 Nick Clifton <nickc@redhat.com>
644
645 * po/fr.po: Updated French translation.
646
4fff86c5
PB		 6472015-04-27 Peter Bergner <bergner@vnet.ibm.com>
648
649 * ppc-opc.c (DCBT_EO): New define.
650 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
651 <lharx>: Likewise.
652 <stbcx.>: Likewise.
653 <sthcx.>: Likewise.
654 <waitrsv>: Do not enable for POWER7 and later.
655 <waitimpl>: Likewise.
656 <dcbt>: Default to the two operand form of the instruction for all
657 "old" cpus. For "new" cpus, use the operand ordering that matches
658 whether the cpu is server or embedded.
659 <dcbtst>: Likewise.
660
3b78cfe1
AK		 6612015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
662
663 * s390-opc.c: New instruction type VV0UU2.
664 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
665 and WFC.
666
04d824a4
JB		 6672015-04-23 Jan Beulich <jbeulich@suse.com>
668
669 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
670 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
671 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
672 (vfpclasspd, vfpclassps): Add %XZ.
673
09708981
L		 6742015-04-15 H.J. Lu <hongjiu.lu@intel.com>
675
676 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
677 (PREFIX_UD_REPZ): Likewise.
678 (PREFIX_UD_REPNZ): Likewise.
679 (PREFIX_UD_DATA): Likewise.
680 (PREFIX_UD_ADDR): Likewise.
681 (PREFIX_UD_LOCK): Likewise.
682
3888916d
L		 6832015-04-15 H.J. Lu <hongjiu.lu@intel.com>
684
685 * i386-dis.c (prefix_requirement): Removed.
686 (print_insn): Don't set prefix_requirement. Check
687 dp->prefix_requirement instead of prefix_requirement.
688
f24bcbaa
L		 6892015-04-15 H.J. Lu <hongjiu.lu@intel.com>
690
691 PR binutils/17898
692 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
693 (PREFIX_MOD_0_0FC7_REG_6): This.
694 (PREFIX_MOD_3_0FC7_REG_6): New.
695 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
696 (prefix_table): Replace PREFIX_0FC7_REG_6 with
697 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
698 PREFIX_MOD_3_0FC7_REG_7.
699 (mod_table): Replace PREFIX_0FC7_REG_6 with
700 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
701 PREFIX_MOD_3_0FC7_REG_7.
702
507bd325
L		 7032015-04-15 H.J. Lu <hongjiu.lu@intel.com>
704
705 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
706 (PREFIX_MANDATORY_REPNZ): Likewise.
707 (PREFIX_MANDATORY_DATA): Likewise.
708 (PREFIX_MANDATORY_ADDR): Likewise.
709 (PREFIX_MANDATORY_LOCK): Likewise.
710 (PREFIX_MANDATORY): Likewise.
711 (PREFIX_UD_SHIFT): Set to 8
712 (PREFIX_UD_REPZ): Updated.
713 (PREFIX_UD_REPNZ): Likewise.
714 (PREFIX_UD_DATA): Likewise.
715 (PREFIX_UD_ADDR): Likewise.
716 (PREFIX_UD_LOCK): Likewise.
717 (PREFIX_IGNORED_SHIFT): New.
718 (PREFIX_IGNORED_REPZ): Likewise.
719 (PREFIX_IGNORED_REPNZ): Likewise.
720 (PREFIX_IGNORED_DATA): Likewise.
721 (PREFIX_IGNORED_ADDR): Likewise.
722 (PREFIX_IGNORED_LOCK): Likewise.
723 (PREFIX_OPCODE): Likewise.
724 (PREFIX_IGNORED): Likewise.
725 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
726 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
727 (three_byte_table): Likewise.
728 (mod_table): Likewise.
729 (mandatory_prefix): Renamed to ...
730 (prefix_requirement): This.
731 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
732 Update PREFIX_90 entry.
733 (get_valid_dis386): Check prefix_requirement to see if a prefix
734 should be ignored.
735 (print_insn): Replace mandatory_prefix with prefix_requirement.
736
f0fba320
RL		 7372015-04-15 Renlin Li <renlin.li@arm.com>
738
739 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
740 use it for ssat and ssat16.
741 (print_insn_thumb32): Add handle case for 'D' control code.
742
bf890a93
IT		 7432015-04-06 Ilya Tocar <ilya.tocar@intel.com>
744 H.J. Lu <hongjiu.lu@intel.com>
745
746 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
747 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
748 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
749 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
750 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
751 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
752 Fill prefix_requirement field.
753 (struct dis386): Add prefix_requirement field.
754 (dis386): Fill prefix_requirement field.
755 (dis386_twobyte): Ditto.
756 (twobyte_has_mandatory_prefix_: Remove.
757 (reg_table): Fill prefix_requirement field.
758 (prefix_table): Ditto.
759 (x86_64_table): Ditto.
760 (three_byte_table): Ditto.
761 (xop_table): Ditto.
762 (vex_table): Ditto.
763 (vex_len_table): Ditto.
764 (vex_w_table): Ditto.
765 (mod_table): Ditto.
766 (bad_opcode): Ditto.
767 (print_insn): Use prefix_requirement.
768 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
769 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
770 (float_reg): Ditto.
771
2f783c1f
MF		 7722015-03-30 Mike Frysinger <vapier@gentoo.org>
773
774 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
775
b9d94d62
L		 7762015-03-29 H.J. Lu <hongjiu.lu@intel.com>
777
778 * Makefile.in: Regenerated.
779
27c49e9a
AB		 7802015-03-25 Anton Blanchard <anton@samba.org>
781
782 * ppc-dis.c (disassemble_init_powerpc): Only initialise
783 powerpc_opcd_indices and vle_opcd_indices once.
784
c4e676f1
AB		 7852015-03-25 Anton Blanchard <anton@samba.org>
786
787 * ppc-opc.c (powerpc_opcodes): Add slbfee.
788
823d2571
TG		 7892015-03-24 Terry Guo <terry.guo@arm.com>
790
791 * arm-dis.c (opcode32): Updated to use new arm feature struct.
792 (opcode16): Likewise.
793 (coprocessor_opcodes): Replace bit with feature struct.
794 (neon_opcodes): Likewise.
795 (arm_opcodes): Likewise.
796 (thumb_opcodes): Likewise.
797 (thumb32_opcodes): Likewise.
798 (print_insn_coprocessor): Likewise.
799 (print_insn_arm): Likewise.
800 (select_arm_features): Follow new feature struct.
801
029f3522
GG		 8022015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
803
804 * i386-dis.c (rm_table): Add clzero.
805 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
806 Add CPU_CLZERO_FLAGS.
807 (cpu_flags): Add CpuCLZERO.
808 * i386-opc.h: Add CpuCLZERO.
809 * i386-opc.tbl: Add clzero.
810 * i386-init.h: Re-generated.
811 * i386-tbl.h: Re-generated.
812
6914869a
AB		 8132015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
814
815 * mips-opc.c (decode_mips_operand): Fix constraint issues
816 with u and y operands.
817
21e20815
AB		 8182015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
819
820 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
821
6b1d7593
AK		 8222015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
823
824 * s390-opc.c: Add new IBM z13 instructions.
825 * s390-opc.txt: Likewise.
826
c8f89a34
JW		 8272015-03-10 Renlin Li <renlin.li@arm.com>
828
829 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
830 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
831 related alias.
832 * aarch64-asm-2.c: Regenerate.
833 * aarch64-dis-2.c: Likewise.
834 * aarch64-opc-2.c: Likewise.
835
d8282f0e
JW		 8362015-03-03 Jiong Wang <jiong.wang@arm.com>
837
838 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
839
ac994365
OE		 8402015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
841
842 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
843 arch_sh_up.
844 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
845 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
846
fd63f640
V		 8472015-02-23 Vinay <Vinay.G@kpit.com>
848
849 * rl78-decode.opc (MOV): Added space between two operands for
850 'mov' instruction in index addressing mode.
851 * rl78-decode.c: Regenerate.
852
f63c1776
PA		 8532015-02-19 Pedro Alves <palves@redhat.com>
854
855 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
856
07774fcc
PA		 8572015-02-10 Pedro Alves <palves@redhat.com>
858 Tom Tromey <tromey@redhat.com>
859
860 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
861 microblaze_and, microblaze_xor.
862 * microblaze-opc.h (opcodes): Adjust.
863
3f8107ab
AM		 8642015-01-28 James Bowman <james.bowman@ftdichip.com>
865
866 * Makefile.am: Add FT32 files.
867 * configure.ac: Handle FT32.
868 * disassemble.c (disassembler): Call print_insn_ft32.
869 * ft32-dis.c: New file.
870 * ft32-opc.c: New file.
871 * Makefile.in: Regenerate.
872 * configure: Regenerate.
873 * po/POTFILES.in: Regenerate.
874
e5fe4957
KLC		 8752015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
876
877 * nds32-asm.c (keyword_sr): Add new system registers.
878
1e2e8c52
AK		 8792015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
880
881 * s390-dis.c (s390_extract_operand): Support vector register
882 operands.
883 (s390_print_insn_with_opcode): Support new operands types and add
884 new handling of optional operands.
885 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
886 and include opcode/s390.h instead.
887 (struct op_struct): New field `flags'.
888 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
889 (dumpTable): Dump flags.
890 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
891 string.
892 * s390-opc.c: Add new operands types, instruction formats, and
893 instruction masks.
894 (s390_opformats): Add new formats for .insn.
895 * s390-opc.txt: Add new instructions.
896
b90efa5b 8972015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 898
b90efa5b 899 Update year range in copyright notice of all files.
bffb6004 900
b90efa5b 901For older changes see ChangeLog-2014
252b5132 902\f
b90efa5b 903Copyright (C) 2015 Free Software Foundation, Inc.
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NC		 904
905Copying and distribution of this file, with or without modification,
906are permitted in any medium without royalty provided the copyright
907notice and this notice are preserved.
908
252b5132 909Local Variables:
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NC		 910mode: change-log
911left-margin: 8
912fill-column: 74
252b5132
RH		 913version-control: never
914End:
GDB Binutils - Deliverables
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