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MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
49149d59
MR		 12021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
2
3 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
4 COP3 opcode instructions.
5
9573a461
MR		 62021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
7
8 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
9 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
10 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
11 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
12 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
13 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
14 "cop2", and "cop3" entries.
15
fa495743
MR		 162021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
17
18 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
19 entries and associated comments.
20
b930964c
MR		 212021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
22
23 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
24 of "c0".
25
dd844468
MR		 262021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
27
28 * mips-dis.c (mips_cp1_names_mips): New variable.
29 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
30 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
31 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
32 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
33 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
34 "loongson2f".
35
9204ccd4
MR		 362021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
37
38 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
39 handling code over to...
40 <OP_REG_CONTROL>: ... this new case.
41 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
42 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
43 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
44 replacing the `G' operand code with `g'. Update "cftc1" and
45 "cftc2" entries replacing the `E' operand code with `y'.
46 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
47 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
48 entries replacing the `G' operand code with `g'.
49
a3fb396f
MR		 502021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
51
52 * mips-dis.c (mips_cp0_names_r3900): New variable.
53 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
54 for "r3900".
55
cccc84fa
MR		 562021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
57
58 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
59 and "mtthc2" to using the `G' rather than `g' operand code for
60 the coprocessor control register referred.
61
c9de3168
MR		 622021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
63
64 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
65 entries with each other.
66
ebcab741
PB		 672021-05-27 Peter Bergner <bergner@linux.ibm.com>
68
69 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
70
bc30a119
AM		 712021-05-25 Alan Modra <amodra@gmail.com>
72
73 * cris-desc.c: Regenerate.
74 * cris-desc.h: Regenerate.
75 * cris-opc.h: Regenerate.
76 * po/POTFILES.in: Regenerate.
77
54711280
MF		 782021-05-24 Mike Frysinger <vapier@gentoo.org>
79
80 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
81 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
82 (CGEN_CPUS): Add cris.
83 (CRIS_DEPS): Define.
84 (stamp-cris): New rule.
85 * cgen.sh: Handle desc action.
86 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
87 * Makefile.in, configure: Regenerate.
88
113bb761
JN		 892021-05-18 Job Noorman <mtvec@pm.me>
90
91 PR 27814
92 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
93 the elf objects.
94
e683cb41
AC		 952021-05-17 Alex Coplan <alex.coplan@arm.com>
96
97 * arm-dis.c (mve_opcodes): Fix disassembly of
98 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
99 (is_mve_encoding_conflict): MVE vector loads should not match
100 when P = W = 0.
101 (is_mve_unpredictable): It's not unpredictable to use the same
102 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
103
a680affc
NC		 1042021-05-11 Nick Clifton <nickc@redhat.com>
105
106 PR 27840
107 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
108 the end of the code buffer.
109
0b3e14c9
SH		 1102021-05-06 Stafford Horne <shorne@gmail.com>
111
112 PR 21464
113 * or1k-asm.c: Regenerate.
114
6aee2cb2
MF		 1152021-05-01 Max Filippov <jcmvbkbc@gmail.com>
116
117 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
118 info->insn_info_valid.
119
fe134c65
JB		 1202021-04-26 Jan Beulich <jbeulich@suse.com>
121
122 * i386-opc.tbl (lea): Add Optimize.
123 * opcodes/i386-tbl.h: Re-generate.
124
b3ea7639
MF		 1252020-04-23 Max Filippov <jcmvbkbc@gmail.com>
126
127 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
128 of l32r fetch and display referenced literal value.
129
c1cbb7d8
MF		 1302021-04-23 Max Filippov <jcmvbkbc@gmail.com>
131
132 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
133 to 4 for literal disassembly.
134
02202574
PW		 1352021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
136
137 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
138 for TLBI instruction.
139
cd6608e4
PW		 1402021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
141
142 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
143 DC instruction.
144
fe1640ff
JB		 1452021-04-19 Jan Beulich <jbeulich@suse.com>
146
147 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
148 "qualifier".
149 (convert_mov_to_movewide): Add initializer for "value".
150
100e914d
PW		 1512021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
152
153 * aarch64-opc.c: Add RME system registers.
154
a21b96dd
NC		 1552021-04-16 Lifang Xia <lifang_xia@c-sky.com>
156
157 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
158 "addi d,CV,z" to "c.mv d,CV".
159
43e05cd4
AM		 1602021-04-12 Alan Modra <amodra@gmail.com>
161
162 * configure.ac (--enable-checking): Add support.
163 * config.in: Regenerate.
164 * configure: Regenerate.
165
52efda82
TB		 1662021-04-09 Tejas Belagod <tejas.belagod@arm.com>
167
168 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
169 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
170
c3f72de4
AM		 1712021-04-09 Alan Modra <amodra@gmail.com>
172
173 * ppc-dis.c (struct dis_private): Add "special".
174 (POWERPC_DIALECT): Delete. Replace uses with..
175 (private_data): ..this. New inline function.
176 (disassemble_init_powerpc): Init "special" names.
177 (skip_optional_operands): Add is_pcrel arg, set when detecting R
178 field of prefix instructions.
179 (bsearch_reloc, print_got_plt): New functions.
180 (print_insn_powerpc): For pcrel instructions, print target address
181 and symbol if known, and decode plt and got loads too.
182
ce7d813a
AM		 1832021-04-08 Alan Modra <amodra@gmail.com>
184
185 PR 27684
186 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
187
97bf40d8
AM		 1882021-04-08 Alan Modra <amodra@gmail.com>
189
190 PR 27676
191 * ppc-opc.c (DCBT_EO): Move earlier.
192 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
193 (powerpc_operands): Add THCT and THDS entries.
194 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
195
a2e66773
AM		 1962021-04-06 Alan Modra <amodra@gmail.com>
197
198 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
199 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
200 symbol_at_address_func.
201
ab2af25e
AM		 2022021-04-05 Alan Modra <amodra@gmail.com>
203
204 * configure.ac: Don't check for limits.h, string.h, strings.h or
205 stdlib.h.
206 (AC_ISC_POSIX): Don't invoke.
207 * sysdep.h: Include stdlib.h and string.h unconditionally.
208 * i386-opc.h: Include limits.h unconditionally.
209 * wasm32-dis.c: Likewise.
210 * cgen-opc.c: Don't include alloca-conf.h.
211 * config.in: Regenerate.
212 * configure: Regenerate.
213
e9b095a5
ML		 2142021-04-01 Martin Liska <mliska@suse.cz>
215
216 * arm-dis.c (strneq): Remove strneq and use startswith.
217 * cr16-dis.c (print_insn_cr16): Likewise.
218 * score-dis.c (streq): Likewise.
219 (strneq): Likewise.
220 * score7-dis.c (strneq): Likewise.
221
1cb108e4
AM		 2222021-04-01 Alan Modra <amodra@gmail.com>
223
224 PR 27675
225 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
226
78933a4a
AM		 2272021-03-31 Alan Modra <amodra@gmail.com>
228
229 * sysdep.h (POISON_BFD_BOOLEAN): Define.
230 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
231 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
232 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
233 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
234 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
235 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
236 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
237 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
238 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
239 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
240 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
241 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
242 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
243 and TRUE with true throughout.
244
3dfb1b6d
AM		 2452021-03-31 Alan Modra <amodra@gmail.com>
246
247 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
248 * aarch64-dis.h: Likewise.
249 * aarch64-opc.c: Likewise.
250 * avr-dis.c: Likewise.
251 * csky-dis.c: Likewise.
252 * nds32-asm.c: Likewise.
253 * nds32-dis.c: Likewise.
254 * nfp-dis.c: Likewise.
255 * riscv-dis.c: Likewise.
256 * s12z-dis.c: Likewise.
257 * wasm32-dis.c: Likewise.
258
5e042380
JB		 2592021-03-30 Jan Beulich <jbeulich@suse.com>
260
261 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
262 (i386_seg_prefixes): New.
263 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
264 (i386_seg_prefixes): Declare.
265
34684862
JB		 2662021-03-30 Jan Beulich <jbeulich@suse.com>
267
268 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
269
6288d05f
JB		 2702021-03-30 Jan Beulich <jbeulich@suse.com>
271
272 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
273 * i386-reg.tbl (st): Move down.
274 (st(0)): Delete. Extend comment.
275 * i386-tbl.h: Re-generate.
276
bbe1eca6
JB		 2772021-03-29 Jan Beulich <jbeulich@suse.com>
278
279 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
280 (cmpsd): Move next to cmps.
281 (movsd): Move next to movs.
282 (cmpxchg16b): Move to separate section.
283 (fisttp, fisttpll): Likewise.
284 (monitor, mwait): Likewise.
285 * i386-tbl.h: Re-generate.
286
c8cad9d3
JB		 2872021-03-29 Jan Beulich <jbeulich@suse.com>
288
289 * i386-opc.tbl (psadbw): Add <sse2:comm>.
290 (vpsadbw): Add C.
291 * i386-tbl.h: Re-generate.
292
5cdaf100
JB		 2932021-03-29 Jan Beulich <jbeulich@suse.com>
294
295 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
296 pclmul, gfni): New templates. Use them wherever possible. Move
297 SSE4.1 pextrw into respective section.
298 * i386-tbl.h: Re-generate.
299
73e45eb2
JB		 3002021-03-29 Jan Beulich <jbeulich@suse.com>
301
302 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
303 strtoull(). Bump upper loop bound. Widen masks. Sanity check
304 "length".
305 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
306 Convert all of their uses to representation in opcode.
307
9df6f676
JB		 3082021-03-29 Jan Beulich <jbeulich@suse.com>
309
310 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
311 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
312 value of None. Shrink operands to 3 bits.
313
389d00a5
JB		 3142021-03-29 Jan Beulich <jbeulich@suse.com>
315
316 * i386-gen.c (process_i386_opcode_modifier): New parameter
317 "space".
318 (output_i386_opcode): New local variable "space". Adjust
319 process_i386_opcode_modifier() invocation.
320 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
321 invocation.
322 * i386-tbl.h: Re-generate.
323
63b4cc53
AM		 3242021-03-29 Alan Modra <amodra@gmail.com>
325
326 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
327 (fp_qualifier_p, get_data_pattern): Likewise.
328 (aarch64_get_operand_modifier_from_value): Likewise.
329 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
330 (operand_variant_qualifier_p): Likewise.
331 (qualifier_value_in_range_constraint_p): Likewise.
332 (aarch64_get_qualifier_esize): Likewise.
333 (aarch64_get_qualifier_nelem): Likewise.
334 (aarch64_get_qualifier_standard_value): Likewise.
335 (get_lower_bound, get_upper_bound): Likewise.
336 (aarch64_find_best_match, match_operands_qualifier): Likewise.
337 (aarch64_print_operand): Likewise.
338 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
339 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
340 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
341 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
342 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
343 (print_insn_tic6x): Likewise.
344
3d7d6c1b
AM		 3452021-03-29 Alan Modra <amodra@gmail.com>
346
347 * arc-dis.c (extract_operand_value): Correct NULL cast.
348 * frv-opc.h: Regenerate.
349
c3344b62
JB		 3502021-03-26 Jan Beulich <jbeulich@suse.com>
351
352 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
353 MMX form.
354 * i386-tbl.h: Re-generate.
355
efa30ac3
HAQ		 3562021-03-25 Abid Qadeer <abidh@codesourcery.com>
357
358 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
359 immediate in br.n instruction.
360
596a02ff
JB		 3612021-03-25 Jan Beulich <jbeulich@suse.com>
362
363 * i386-dis.c (XMGatherD, VexGatherD): New.
364 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
365 (print_insn): Check masking for S/G insns.
366 (OP_E_memory): New local variable check_gather. Extend mandatory
367 SIB check. Check register conflicts for (EVEX-encoded) gathers.
368 Extend check for disallowed 16-bit addressing.
369 (OP_VEX): New local variables modrm_reg and sib_index. Convert
370 if()s to switch(). Check register conflicts for (VEX-encoded)
371 gathers. Drop no longer reachable cases.
372 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
373 vgatherdp*.
374
53642852
JB		 3752021-03-25 Jan Beulich <jbeulich@suse.com>
376
377 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
378 zeroing-masking without masking.
379
c0e54661
JB		 3802021-03-25 Jan Beulich <jbeulich@suse.com>
381
382 * i386-opc.tbl (invlpgb): Fix multi-operand form.
383 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
384 single-operand forms as deprecated.
385 * i386-tbl.h: Re-generate.
386
5a403766
AM		 3872021-03-25 Alan Modra <amodra@gmail.com>
388
389 PR 27647
390 * ppc-opc.c (XLOCB_MASK): Delete.
391 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
392 XLBH_MASK.
393 (powerpc_opcodes): Accept a BH field on all extended forms of
394 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
395
9a182d04
JB		 3962021-03-24 Jan Beulich <jbeulich@suse.com>
397
398 * i386-gen.c (output_i386_opcode): Drop processing of
399 opcode_length. Calculate length from base_opcode. Adjust prefix
400 encoding determination.
401 (process_i386_opcodes): Drop output of fake opcode_length.
402 * i386-opc.h (struct insn_template): Drop opcode_length field.
403 * i386-opc.tbl: Drop opcode length field from all templates.
404 * i386-tbl.h: Re-generate.
405
35648716
JB		 4062021-03-24 Jan Beulich <jbeulich@suse.com>
407
408 * i386-gen.c (process_i386_opcode_modifier): Return void. New
409 parameter "prefix". Drop local variable "regular_encoding".
410 Record prefix setting / check for consistency.
411 (output_i386_opcode): Parse opcode_length and base_opcode
412 earlier. Derive prefix encoding. Drop no longer applicable
413 consistency checking. Adjust process_i386_opcode_modifier()
414 invocation.
415 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
416 invocation.
417 * i386-tbl.h: Re-generate.
418
31184569
JB		 4192021-03-24 Jan Beulich <jbeulich@suse.com>
420
421 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
422 check.
423 * i386-opc.h (Prefix_*): Move #define-s.
424 * i386-opc.tbl: Move pseudo prefix enumerator values to
425 extension opcode field. Introduce pseudopfx template.
426 * i386-tbl.h: Re-generate.
427
b933fa4b
JB		 4282021-03-23 Jan Beulich <jbeulich@suse.com>
429
430 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
431 comment.
432 * i386-tbl.h: Re-generate.
433
dac10fb0
JB		 4342021-03-23 Jan Beulich <jbeulich@suse.com>
435
436 * i386-opc.h (struct insn_template): Move cpu_flags field past
437 opcode_modifier one.
438 * i386-tbl.h: Re-generate.
439
441f6aca
JB		 4402021-03-23 Jan Beulich <jbeulich@suse.com>
441
442 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
443 * i386-opc.h (OpcodeSpace): New enumerator.
444 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
445 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
446 SPACE_XOP09, SPACE_XOP0A): ... respectively.
447 (struct i386_opcode_modifier): New field opcodespace. Shrink
448 opcodeprefix field.
449 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
450 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
451 OpcodePrefix uses.
452 * i386-tbl.h: Re-generate.
453
08dedd66
ML		 4542021-03-22 Martin Liska <mliska@suse.cz>
455
456 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
457 * arc-dis.c (parse_option): Likewise.
458 * arm-dis.c (parse_arm_disassembler_options): Likewise.
459 * cris-dis.c (print_with_operands): Likewise.
460 * h8300-dis.c (bfd_h8_disassemble): Likewise.
461 * i386-dis.c (print_insn): Likewise.
462 * ia64-gen.c (fetch_insn_class): Likewise.
463 (parse_resource_users): Likewise.
464 (in_iclass): Likewise.
465 (lookup_specifier): Likewise.
466 (insert_opcode_dependencies): Likewise.
467 * mips-dis.c (parse_mips_ase_option): Likewise.
468 (parse_mips_dis_option): Likewise.
469 * s390-dis.c (disassemble_init_s390): Likewise.
470 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
471
80d49d6a
KLC		 4722021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
473
474 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
475
7fce7ea9
PW		 4762021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
477
478 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
479 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
480
78c84bf9
AM		 4812021-03-12 Alan Modra <amodra@gmail.com>
482
483 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
484
fd1fd061
JB		 4852021-03-11 Jan Beulich <jbeulich@suse.com>
486
487 * i386-dis.c (OP_XMM): Re-order checks.
488
ac7a2311
JB		 4892021-03-11 Jan Beulich <jbeulich@suse.com>
490
491 * i386-dis.c (putop): Drop need_vex check when also checking
492 vex.evex.
493 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
494 checking vex.b.
495
da944c8a
JB		 4962021-03-11 Jan Beulich <jbeulich@suse.com>
497
498 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
499 checks. Move case label past broadcast check.
500
b763d508
JB		 5012021-03-10 Jan Beulich <jbeulich@suse.com>
502
503 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
504 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
505 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
506 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
507 EVEX_W_0F38C7_M_0_L_2): Delete.
508 (REG_EVEX_0F38C7_M_0_L_2): New.
509 (intel_operand_size): Handle VEX and EVEX the same for
510 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
511 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
512 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
513 vex_vsib_q_w_d_mode uses.
514 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
515 0F38A1, and 0F38A3 entries.
516 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
517 entry.
518 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
519 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
520 0F38A3 entries.
521
32e31ad7
JB		 5222021-03-10 Jan Beulich <jbeulich@suse.com>
523
524 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
525 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
526 MOD_VEX_0FXOP_09_12): Rename to ...
527 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
528 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
529 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
530 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
531 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
532 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
533 (reg_table): Adjust comments.
534 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
535 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
536 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
537 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
538 (vex_len_table): Adjust opcode 0A_12 entry.
539 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
540 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
541 (rm_table): Move hreset entry.
542
85ba7507
JB		 5432021-03-10 Jan Beulich <jbeulich@suse.com>
544
545 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
546 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
547 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
548 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
549 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
550 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
551 (get_valid_dis386): Also handle 512-bit vector length when
552 vectoring into vex_len_table[].
553 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
554 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
555 entries.
556 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
557 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
558 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
559 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
560 entries.
561
066f82b9
JB		 5622021-03-10 Jan Beulich <jbeulich@suse.com>
563
564 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
565 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
566 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
567 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
568 entries.
569 * i386-dis-evex-len.h (evex_len_table): Likewise.
570 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
571
fc681dd6
JB		 5722021-03-10 Jan Beulich <jbeulich@suse.com>
573
574 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
575 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
576 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
577 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
578 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
579 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
580 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
581 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
582 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
583 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
584 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
585 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
586 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
587 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
588 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
589 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
590 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
591 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
592 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
593 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
594 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
595 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
596 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
597 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
598 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
599 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
600 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
601 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
602 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
603 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
604 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
605 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
606 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
607 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
608 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
609 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
610 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
611 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
612 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
613 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
614 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
615 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
616 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
617 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
618 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
619 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
620 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
621 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
622 EVEX_W_0F3A43_L_n): New.
623 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
624 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
625 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
626 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
627 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
628 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
629 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
630 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
631 0F385B, 0F38C6, and 0F38C7 entries.
632 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
633 0F38C6 and 0F38C7.
634 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
635 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
636 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
637 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
638
13954a31
JB		 6392021-03-10 Jan Beulich <jbeulich@suse.com>
640
641 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
642 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
643 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
644 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
645 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
646 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
647 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
648 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
649 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
650 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
651 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
652 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
653 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
654 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
655 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
656 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
657 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
658 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
659 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
660 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
661 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
662 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
663 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
664 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
665 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
666 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
667 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
668 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
669 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
670 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
671 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
672 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
673 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
674 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
675 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
676 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
677 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
678 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
679 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
680 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
681 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
682 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
683 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
684 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
685 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
686 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
687 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
688 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
689 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
690 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
691 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
692 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
693 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
694 VEX_W_0F99_P_2_LEN_0): Delete.
695 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
696 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
697 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
698 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
699 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
700 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
701 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
702 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
703 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
704 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
705 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
706 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
707 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
708 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
709 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
710 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
711 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
712 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
713 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
714 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
715 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
716 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
717 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
718 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
719 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
720 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
721 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
722 (prefix_table): No longer link to vex_len_table[] for opcodes
723 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
724 0F92, 0F93, 0F98, and 0F99.
725 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
726 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
727 0F98, and 0F99.
728 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
729 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
730 0F98, and 0F99.
731 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
732 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
733 0F98, and 0F99.
734 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
735 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
736 0F98, and 0F99.
737
14d10c6c
JB		 7382021-03-10 Jan Beulich <jbeulich@suse.com>
739
740 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
741 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
742 REG_VEX_0F73_M_0 respectively.
743 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
744 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
745 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
746 MOD_VEX_0F73_REG_7): Delete.
747 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
748 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
749 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
750 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
751 PREFIX_VEX_0F3AF0_L_0 respectively.
752 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
753 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
754 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
755 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
756 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
757 VEX_LEN_0F38F7): New.
758 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
759 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
760 0F72, and 0F73. No longer link to vex_len_table[] for opcode
761 0F38F3.
762 (prefix_table): No longer link to vex_len_table[] for opcodes
763 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
764 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
765 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
766 0F38F6, 0F38F7, and 0F3AF0.
767 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
768 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
769 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
770 0F73.
771
00ec1875
JB		 7722021-03-10 Jan Beulich <jbeulich@suse.com>
773
774 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
775 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
776 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
777 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
778 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
779 (MOD_0F71, MOD_0F72, MOD_0F73): New.
780 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
781 73.
782 (reg_table): No longer link to mod_table[] for opcodes 0F71,
783 0F72, and 0F73.
784 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
785 0F73.
786
31941983
JB		 7872021-03-10 Jan Beulich <jbeulich@suse.com>
788
789 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
790 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
791 (reg_table): Don't link to mod_table[] where not needed. Add
792 PREFIX_IGNORED to nop entries.
793 (prefix_table): Replace PREFIX_OPCODE in nop entries.
794 (mod_table): Add nop entries next to prefetch ones. Drop
795 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
796 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
797 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
798 PREFIX_OPCODE from endbr* entries.
799 (get_valid_dis386): Also consider entry's name when zapping
800 vindex.
801 (print_insn): Handle PREFIX_IGNORED.
802
742732c7
JB		 8032021-03-09 Jan Beulich <jbeulich@suse.com>
804
805 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
806 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
807 element.
808 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
809 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
810 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
811 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
812 (struct i386_opcode_modifier): Delete notrackprefixok,
813 islockable, hleprefixok, and repprefixok fields. Add prefixok
814 field.
815 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
816 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
817 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
818 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
819 Replace HLEPrefixOk.
820 * opcodes/i386-tbl.h: Re-generate.
821
e93a3b27
JB		 8222021-03-09 Jan Beulich <jbeulich@suse.com>
823
824 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
825 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
826 64-bit form.
827 * opcodes/i386-tbl.h: Re-generate.
828
75363b6d
JB		 8292021-03-03 Jan Beulich <jbeulich@suse.com>
830
831 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
832 for {} instead of {0}. Don't look for '0'.
833 * i386-opc.tbl: Drop operand count field. Drop redundant operand
834 size specifiers.
835
5a9f5403
NC		 8362021-02-19 Nelson Chu <nelson.chu@sifive.com>
837
838 PR 27158
839 * riscv-dis.c (print_insn_args): Updated encoding macros.
840 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
841 (match_c_addi16sp): Updated encoding macros.
842 (match_c_lui): Likewise.
843 (match_c_lui_with_hint): Likewise.
844 (match_c_addi4spn): Likewise.
845 (match_c_slli): Likewise.
846 (match_slli_as_c_slli): Likewise.
847 (match_c_slli64): Likewise.
848 (match_srxi_as_c_srxi): Likewise.
849 (riscv_insn_types): Added .insn css/cl/cs.
850
3d73d29e
NC		 8512021-02-18 Nelson Chu <nelson.chu@sifive.com>
852
853 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
854 (default_priv_spec): Updated type to riscv_spec_class.
855 (parse_riscv_dis_option): Updated.
856 * riscv-opc.c: Moved stuff and make the file tidy.
857
b9b204b3
AM		 8582021-02-17 Alan Modra <amodra@gmail.com>
859
860 * wasm32-dis.c: Include limits.h.
861 (CHAR_BIT): Provide backup define.
862 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
863 Correct signed overflow checking.
864
394ae71f
JB		 8652021-02-16 Jan Beulich <jbeulich@suse.com>
866
867 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
868 * i386-tbl.h: Re-generate.
869
b818b220
JB		 8702021-02-16 Jan Beulich <jbeulich@suse.com>
871
872 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
873 Oword.
874 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
875
ba2b480f
AK		 8762021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
877
878 * s390-mkopc.c (main): Accept arch14 as cpu string.
879 * s390-opc.txt: Add new arch14 instructions.
880
95148614
NA		 8812021-02-04 Nick Alcock <nick.alcock@oracle.com>
882
883 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
884 favour of LIBINTL.
885 * configure: Regenerated.
886
bfd428bc
MF		 8872021-02-08 Mike Frysinger <vapier@gentoo.org>
888
889 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
890 * tic54x-opc.c (regs): Rename to ...
891 (tic54x_regs): ... this.
892 (mmregs): Rename to ...
893 (tic54x_mmregs): ... this.
894 (condition_codes): Rename to ...
895 (tic54x_condition_codes): ... this.
896 (cc2_codes): Rename to ...
897 (tic54x_cc2_codes): ... this.
898 (cc3_codes): Rename to ...
899 (tic54x_cc3_codes): ... this.
900 (status_bits): Rename to ...
901 (tic54x_status_bits): ... this.
902 (misc_symbols): Rename to ...
903 (tic54x_misc_symbols): ... this.
904
24075dcc
NC		 9052021-02-04 Nelson Chu <nelson.chu@sifive.com>
906
907 * riscv-opc.c (MASK_RVB_IMM): Removed.
908 (riscv_opcodes): Removed zb* instructions.
909 (riscv_ext_version_table): Removed versions for zb*.
910
c3ffb8f3
AM		 9112021-01-26 Alan Modra <amodra@gmail.com>
912
913 * i386-gen.c (parse_template): Ensure entire template_instance
914 is initialised.
915
1942a048
NC		 9162021-01-15 Nelson Chu <nelson.chu@sifive.com>
917
918 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
919 (riscv_fpr_names_abi): Likewise.
920 (riscv_opcodes): Likewise.
921 (riscv_insn_types): Likewise.
922
b800637e
NC		 9232021-01-15 Nelson Chu <nelson.chu@sifive.com>
924
925 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
926
dcd709e0
NC		 9272021-01-15 Nelson Chu <nelson.chu@sifive.com>
928
929 * riscv-dis.c: Comments tidy and improvement.
930 * riscv-opc.c: Likewise.
931
5347ed60
AM		 9322021-01-13 Alan Modra <amodra@gmail.com>
933
934 * Makefile.in: Regenerate.
935
d546b610
L		 9362021-01-12 H.J. Lu <hongjiu.lu@intel.com>
937
938 PR binutils/26792
939 * configure.ac: Use GNU_MAKE_JOBSERVER.
940 * aclocal.m4: Regenerated.
941 * configure: Likewise.
942
6d104cac
NC		 9432021-01-12 Nick Clifton <nickc@redhat.com>
944
945 * po/sr.po: Updated Serbian translation.
946
83b33c6c
L		 9472021-01-11 H.J. Lu <hongjiu.lu@intel.com>
948
949 PR ld/27173
950 * configure: Regenerated.
951
82c70b08
KT		 9522021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
953
954 * aarch64-asm-2.c: Regenerate.
955 * aarch64-dis-2.c: Likewise.
956 * aarch64-opc-2.c: Likewise.
957 * aarch64-opc.c (aarch64_print_operand):
958 Delete handling of AARCH64_OPND_CSRE_CSR.
959 * aarch64-tbl.h (aarch64_feature_csre): Delete.
960 (CSRE): Likewise.
961 (_CSRE_INSN): Likewise.
962 (aarch64_opcode_table): Delete csr.
963
a8aa72b9
NC		 9642021-01-11 Nick Clifton <nickc@redhat.com>
965
966 * po/de.po: Updated German translation.
967 * po/fr.po: Updated French translation.
968 * po/pt_BR.po: Updated Brazilian Portuguese translation.
969 * po/sv.po: Updated Swedish translation.
970 * po/uk.po: Updated Ukranian translation.
971
a4966cd9
L		 9722021-01-09 H.J. Lu <hongjiu.lu@intel.com>
973
974 * configure: Regenerated.
975
573fe3fb
NC		 9762021-01-09 Nick Clifton <nickc@redhat.com>
977
978 * configure: Regenerate.
979 * po/opcodes.pot: Regenerate.
980
055bc77a
NC		 9812021-01-09 Nick Clifton <nickc@redhat.com>
982
983 * 2.36 release branch crated.
984
aae7fcb8
PB		 9852021-01-08 Peter Bergner <bergner@linux.ibm.com>
986
987 * ppc-opc.c (insert_dw, (extract_dw): New functions.
988 (DW, (XRC_MASK): Define.
989 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
990
64307045
AM		 9912021-01-09 Alan Modra <amodra@gmail.com>
992
993 * configure: Regenerate.
994
ed205222
NC		 9952021-01-08 Nick Clifton <nickc@redhat.com>
996
997 * po/sv.po: Updated Swedish translation.
998
fb932b57
NC		 9992021-01-08 Nick Clifton <nickc@redhat.com>
1000
e84c8716
NC		 1001 PR 27129
1002 * aarch64-dis.c (determine_disassembling_preference): Move call to
1003 aarch64_match_operands_constraint outside of the assertion.
1004 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1005 Replace with a return of FALSE.
1006
fb932b57
NC		 1007 PR 27139
1008 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1009 core system register.
1010
f4782128
ST		 10112021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1012
1013 * configure: Regenerate.
1014
1b0927db
NC		 10152021-01-07 Nick Clifton <nickc@redhat.com>
1016
1017 * po/fr.po: Updated French translation.
1018
3b288c8e
FN		 10192021-01-07 Fredrik Noring <noring@nocrew.org>
1020
1021 * m68k-opc.c (chkl): Change minimum architecture requirement to
1022 m68020.
1023
aa881ecd
PT		 10242021-01-07 Philipp Tomsich <prt@gnu.org>
1025
1026 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1027
2652cfad
CXW		 10282021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1029 Jim Wilson <jimw@sifive.com>
1030 Andrew Waterman <andrew@sifive.com>
1031 Maxim Blinov <maxim.blinov@embecosm.com>
1032 Kito Cheng <kito.cheng@sifive.com>
1033 Nelson Chu <nelson.chu@sifive.com>
1034
1035 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1036 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1037
250d07de
AM		 10382021-01-01 Alan Modra <amodra@gmail.com>
1039
1040 Update year range in copyright notice of all files.
1041
c2795844 1042For older changes see ChangeLog-2020
3499769a 1043\f
c2795844 1044Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 1045
1046Copying and distribution of this file, with or without modification,
1047are permitted in any medium without royalty provided the copyright
1048notice and this notice are preserved.
1049
1050Local Variables:
1051mode: change-log
1052left-margin: 8
1053fill-column: 74
1054version-control: never
1055End:
GDB Binutils - Deliverables
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