[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2017-03-21  Rinat Zelig  <rinat@mellanox.com>

	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	(insert_nps_imm_offset): New function.
	(extract_nps_imm_offset): New function.
	(insert_nps_imm_entry): New function.
	(extract_nps_imm_entry): New function.

2017-03-17  Alan Modra  <amodra@gmail.com>

	PR 21248
	* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
	mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
	those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.

2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
	<c.andi>: Likewise.
	<c.addiw> Likewise.

2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.

2017-03-13  Andrew Waterman  <andrew@sifive.com>

	* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
	<srl> Likewise.
	<srai> Likewise.
	<sra> Likewise.

2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Replace S with Load.
	* i386-opc.h (S): Removed.
	(Load): New.
	(i386_opcode_modifier): Replace s with load.
	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	and {evex}.  Replace S with Load.
	* i386-tbl.h: Regenerated.

2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Use CpuCET on rdsspq.
	* i386-tbl.h: Regenerated.

2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
	<vsx>: Do not use PPC_OPCODE_VSX3;

2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.

2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	(MOD_0F1E_PREFIX_1): Likewise.
	(MOD_0F38F5_PREFIX_2): Likewise.
	(MOD_0F38F6_PREFIX_0): Likewise.
	(RM_0F1E_MOD_3_REG_7): Likewise.
	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	(PREFIX_0F1E): Likewise.
	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	(PREFIX_0F38F5): Likewise.
	(dis386_twobyte): Use PREFIX_0F1E.
	(reg_table): Add REG_0F1E_MOD_3.
	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	(three_byte_table): Use PREFIX_0F38F5.
	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	PREFIX_MOD_3_0F01_REG_5_RM_2.
	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	(cpu_flags): Add CpuCET.
	* i386-opc.h (CpuCET): New enum.
	(CpuUnused): Commented out.
	(i386_cpu_flags): Add cpucet.
	* i386-opc.tbl: Add Intel CET instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2017-03-06  Alan Modra  <amodra@gmail.com>

	PR 21124
	* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
	(extract_raq, extract_ras, extract_rbx): New functions.
	(powerpc_operands): Use opposite corresponding insert function.
	(Q_MASK): Define.
	(powerpc_opcodes): Apply Q_MASK to all quad insns with even
	register restriction.

2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>

	* disassemble.c Include "safe-ctype.h".
	(disassemble_init_for_target): Handle s390 init.
	(remove_whitespace_and_extra_commas): New function.
	(disassembler_options_cmp): Likewise.
	* arm-dis.c: Include "libiberty.h".
	(NUM_ELEM): Delete.
	(regnames): Use long disassembler style names.
	Add force-thumb and no-force-thumb options.
	(NUM_ARM_REGNAMES): Rename from this...
	(NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
	(get_arm_regname_num_options): Delete.
	(set_arm_regname_option): Likewise.
	(get_arm_regnames): Likewise.
	(parse_disassembler_options): Likewise.
	(parse_arm_disassembler_option): Rename from this...
	(parse_arm_disassembler_options): ...to this.  Make static.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
	(print_insn): Use parse_arm_disassembler_options.
	(disassembler_options_arm): New function.
	(print_arm_disassembler_options): Handle updated regnames.
	* ppc-dis.c: Include "libiberty.h".
	(ppc_opts): Add "32" and "64" entries.
	(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
	(powerpc_init_dialect): Add break to switch statement.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro.
	(disassembler_options_powerpc): New function.
	(print_ppc_disassembler_options): Use ARRAY_SIZE.
	Remove printing of "32" and "64".
	* s390-dis.c: Include "libiberty.h".
	(init_flag): Remove unneeded variable.
	(struct s390_options_t): New structure type.
	(options): New structure.
	(init_disasm): Rename from this...
	(disassemble_init_s390): ...to this.  Add initializations for
	current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
	(print_insn_s390): Delete call to init_disasm.
	(disassembler_options_s390): New function.
	(print_s390_disassembler_options): Print using information from
	struct 'options'.
	* po/opcodes.pot: Regenerate.

2017-02-28  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (PCMPESTR_Fixup): New.
	(VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
	(prefix_table): Use PCMPESTR_Fixup.
	(vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
	PCMPESTR_Fixup.
	(vex_w_table): Delete VPCMPESTR{I,M} entries.
	* i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
	Split 64-bit and non-64-bit variants.
	* opcodes/i386-tbl.h: Re-generate.

2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
	(OP_SVE_V_HSD): New macros.
	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
	(aarch64_opcode_table): Add new SVE instructions.
	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
	for rotation operands.  Add new SVE operands.
	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
	(ins_sve_quad_index): Likewise.
	(ins_imm_rotate): Split into...
	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
	functions.
	(aarch64_ins_sve_addr_ri_s4): New function.
	(aarch64_ins_sve_quad_index): Likewise.
	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
	(ext_sve_quad_index): Likewise.
	(ext_imm_rotate): Split into...
	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
	functions.
	(aarch64_ext_sve_addr_ri_s4): New function.
	(aarch64_ext_sve_quad_index): Likewise.
	(aarch64_ext_sve_index): Allow quad indices.
	(do_misc_decoding): Likewise.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
	aarch64_field_kinds.
	(OPD_F_OD_MASK): Widen by one bit.
	(OPD_F_NO_ZR): Bump accordingly.
	(get_operand_field_width): New function.
	* aarch64-opc.c (fields): Add new SVE fields.
	(operand_general_constraint_met_p): Handle new SVE operands.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.

2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
	(aarch64_feature_compnum): ...this.
	(SIMD_V8_3): Replace with...
	(COMPNUM): ...this.
	(CNUM_INSN): New macro.
	(aarch64_opcode_table): Use it for the complex number instructions.

2017-02-24  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.

2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>

	Add support for associating SPARC ASIs with an architecture level.
	* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
	* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
	decoding of SPARC ASIs.

2017-02-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (get_valid_dis386): Don't special case VEX opcode
	82. For 3-byte VEX only special case opcode 77 in VEX_0F space.

2017-02-21  Jan Beulich  <jbeulich@suse.com>

	* aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
	1 (instead of to itself). Correct typo.

2017-02-14  Andrew Waterman  <andrew@sifive.com>

	* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
	pseudoinstructions.

2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
	(aarch64_sys_reg_supported_p): Handle them.

2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (UIMM6_20R): Define.
	(SIMM12_20): Use above.
	(SIMM12_20R): Define.
	(SIMM3_5_S): Use above.
	(UIMM7_A32_11R_S): Define.
	(UIMM7_9_S): Use above.
	(UIMM3_13R_S): Define.
	(SIMM11_A32_7_S): Use above.
	(SIMM9_8R): Define.
	(UIMM10_A32_8_S): Use above.
	(UIMM8_8R_S): Define.
	(W6): Use above.
	(arc_relax_opcodes): Use all above defines.

2017-02-15  Vineet Gupta <vgupta@synopsys.com>

	* arc-regs.h: Distinguish some of the registers different on
	ARC700 and HS38 cpus.

2017-02-14  Alan Modra  <amodra@gmail.com>

	PR 21118
	* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
	with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.

2017-02-11  Stafford Horne  <shorne@gmail.com>
	    Alan Modra  <amodra@gmail.com>

	* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
	Use insn_bytes_value and insn_int_value directly instead.  Don't
	free allocated memory until function exit.

2017-02-10  Nicholas Piggin  <npiggin@gmail.com>

	* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.

2017-02-03  Nick Clifton  <nickc@redhat.com>

	PR 21096
	* aarch64-opc.c (print_register_list): Ensure that the register
	list index will fir into the tb buffer.
	(print_register_offset_address): Likewise.
	* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.

2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>

	PR 21056
	* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
	instructions when the previous fetch packet ends with a 32-bit
	instruction.

2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>

        * pru-opc.c: Remove vague reference to a future GDB port.

2017-01-20  Nick Clifton  <nickc@redhat.com>

	* po/ga.po: Updated Irish translation.

2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.

2017-01-13  Yao Qi  <yao.qi@linaro.org>

	* m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
	if FETCH_DATA returns 0.
	(m68k_scan_mask): Likewise.
	(print_insn_m68k): Update code to handle -1 return value.

2017-01-13  Yao Qi  <yao.qi@linaro.org>

	* m68k-dis.c (enum print_insn_arg_error): New.
	(NEXTBYTE): Replace -3 with
	PRINT_INSN_ARG_MEMORY_ERROR.
	(NEXTULONG): Likewise.
	(NEXTSINGLE): Likewise.
	(NEXTDOUBLE): Likewise.
	(NEXTDOUBLE): Likewise.
	(NEXTPACKED): Likewise.
	(FETCH_ARG): Likewise.
	(FETCH_DATA): Update comments.
	(print_insn_arg): Update comments. Replace magic numbers with
	enum.
	(match_insn_m68k): Likewise.

2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
	CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
	* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
	(i386_cpu_flags): Add cpuavx512_vpopcntdq.
	* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.

2017-01-12  Yao Qi  <yao.qi@linaro.org>

	* msp430-dis.c (msp430_singleoperand): Return -1 if
	msp430dis_opcode_signed returns false.
	(msp430_doubleoperand): Likewise.
	(msp430_branchinstr): Return -1 if
	msp430dis_opcode_unsigned returns false.
	(msp430x_calla_instr): Likewise.
	(print_insn_msp430): Likewise.

2017-01-05  Nick Clifton  <nickc@redhat.com>

	PR 20946
	* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
	could not be matched.
	(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
	NULL.

2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
	(aarch64_opcode_table): Use RCPC_INSN.

2017-01-03  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
	extension.
	* riscv-opcodes/all-opcodes: Likewise.

2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>

	* riscv-dis.c (print_insn_args): Add fall through comment.

2017-01-03  Nick Clifton  <nickc@redhat.com>

	* po/sr.po: New Serbian translation.
	* configure.ac (ALL_LINGUAS): Add sr.
	* configure: Regenerate.

2017-01-02  Alan Modra  <amodra@gmail.com>

	* epiphany-desc.h: Regenerate.
	* epiphany-opc.h: Regenerate.
	* fr30-desc.h: Regenerate.
	* fr30-opc.h: Regenerate.
	* frv-desc.h: Regenerate.
	* frv-opc.h: Regenerate.
	* ip2k-desc.h: Regenerate.
	* ip2k-opc.h: Regenerate.
	* iq2000-desc.h: Regenerate.
	* iq2000-opc.h: Regenerate.
	* lm32-desc.h: Regenerate.
	* lm32-opc.h: Regenerate.
	* m32c-desc.h: Regenerate.
	* m32c-opc.h: Regenerate.
	* m32r-desc.h: Regenerate.
	* m32r-opc.h: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-opc.h: Regenerate.
	* mt-desc.h: Regenerate.
	* mt-opc.h: Regenerate.
	* or1k-desc.h: Regenerate.
	* or1k-opc.h: Regenerate.
	* xc16x-desc.h: Regenerate.
	* xc16x-opc.h: Regenerate.
	* xstormy16-desc.h: Regenerate.
	* xstormy16-opc.h: Regenerate.

2017-01-02  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2016
\f
Copyright (C) 2017 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
645d3342 RZ	1	2017-03-21 Rinat Zelig <rinat@mellanox.com>
	2
	3	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	4	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	5	(insert_nps_imm_offset): New function.
	6	(extract_nps_imm_offset): New function.
	7	(insert_nps_imm_entry): New function.
	8	(extract_nps_imm_entry): New function.
	9
4b94dd2d AM	10	2017-03-17 Alan Modra <amodra@gmail.com>
	11
	12	PR 21248
	13	* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
	14	mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
	15	those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
	16
b416fe87 KC	17	2017-03-14 Kito Cheng <kito.cheng@gmail.com>
	18
	19	* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
	20	<c.andi>: Likewise.
	21	<c.addiw> Likewise.
	22
03b039a5 KC	23	2017-03-14 Kito Cheng <kito.cheng@gmail.com>
	24
	25	* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
	26
2c232b83 AW	27	2017-03-13 Andrew Waterman <andrew@sifive.com>
	28
	29	* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
	30	<srl> Likewise.
	31	<srai> Likewise.
	32	<sra> Likewise.
	33
86fa6981 L	34	2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
	35
	36	* i386-gen.c (opcode_modifiers): Replace S with Load.
	37	* i386-opc.h (S): Removed.
	38	(Load): New.
	39	(i386_opcode_modifier): Replace s with load.
	40	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	41	and {evex}. Replace S with Load.
	42	* i386-tbl.h: Regenerated.
	43
c1fe188b L	44	2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
	45
	46	* i386-opc.tbl: Use CpuCET on rdsspq.
	47	* i386-tbl.h: Regenerated.
	48
4b8b687e PB	49	2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
	50
	51	* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
	52	<vsx>: Do not use PPC_OPCODE_VSX3;
	53
1437d063 PB	54	2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
	55
	56	* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
	57
603555e5 L	58	2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
	59
	60	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	61	(MOD_0F1E_PREFIX_1): Likewise.
	62	(MOD_0F38F5_PREFIX_2): Likewise.
	63	(MOD_0F38F6_PREFIX_0): Likewise.
	64	(RM_0F1E_MOD_3_REG_7): Likewise.
	65	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	66	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	67	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	68	(PREFIX_0F1E): Likewise.
	69	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	70	(PREFIX_0F38F5): Likewise.
	71	(dis386_twobyte): Use PREFIX_0F1E.
	72	(reg_table): Add REG_0F1E_MOD_3.
	73	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	74	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	75	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
	76	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	77	(three_byte_table): Use PREFIX_0F38F5.
	78	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	79	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	80	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	81	RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	82	PREFIX_MOD_3_0F01_REG_5_RM_2.
	83	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	84	(cpu_flags): Add CpuCET.
	85	* i386-opc.h (CpuCET): New enum.
	86	(CpuUnused): Commented out.
	87	(i386_cpu_flags): Add cpucet.
	88	* i386-opc.tbl: Add Intel CET instructions.
	89	* i386-init.h: Regenerated.
	90	* i386-tbl.h: Likewise.
	91
73f07bff AM	92	2017-03-06 Alan Modra <amodra@gmail.com>
	93
	94	PR 21124
	95	* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
	96	(extract_raq, extract_ras, extract_rbx): New functions.
	97	(powerpc_operands): Use opposite corresponding insert function.
	98	(Q_MASK): Define.
	99	(powerpc_opcodes): Apply Q_MASK to all quad insns with even
	100	register restriction.
	101
65b48a81 PB	102	2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
	103
	104	* disassemble.c Include "safe-ctype.h".
	105	(disassemble_init_for_target): Handle s390 init.
	106	(remove_whitespace_and_extra_commas): New function.
	107	(disassembler_options_cmp): Likewise.
	108	* arm-dis.c: Include "libiberty.h".
	109	(NUM_ELEM): Delete.
	110	(regnames): Use long disassembler style names.
	111	Add force-thumb and no-force-thumb options.
	112	(NUM_ARM_REGNAMES): Rename from this...
	113	(NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
	114	(get_arm_regname_num_options): Delete.
	115	(set_arm_regname_option): Likewise.
	116	(get_arm_regnames): Likewise.
	117	(parse_disassembler_options): Likewise.
	118	(parse_arm_disassembler_option): Rename from this...
	119	(parse_arm_disassembler_options): ...to this. Make static.
	120	Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
	121	(print_insn): Use parse_arm_disassembler_options.
	122	(disassembler_options_arm): New function.
	123	(print_arm_disassembler_options): Handle updated regnames.
	124	* ppc-dis.c: Include "libiberty.h".
	125	(ppc_opts): Add "32" and "64" entries.
	126	(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
	127	(powerpc_init_dialect): Add break to switch statement.
	128	Use new FOR_EACH_DISASSEMBLER_OPTION macro.
	129	(disassembler_options_powerpc): New function.
	130	(print_ppc_disassembler_options): Use ARRAY_SIZE.
	131	Remove printing of "32" and "64".
	132	* s390-dis.c: Include "libiberty.h".
	133	(init_flag): Remove unneeded variable.
	134	(struct s390_options_t): New structure type.
	135	(options): New structure.
	136	(init_disasm): Rename from this...
	137	(disassemble_init_s390): ...to this. Add initializations for
	138	current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
	139	(print_insn_s390): Delete call to init_disasm.
	140	(disassembler_options_s390): New function.
	141	(print_s390_disassembler_options): Print using information from
	142	struct 'options'.
	143	* po/opcodes.pot: Regenerate.
	144
15c7c1d8 JB	145	2017-02-28 Jan Beulich <jbeulich@suse.com>
	146
	147	* i386-dis.c (PCMPESTR_Fixup): New.
	148	(VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
	149	(prefix_table): Use PCMPESTR_Fixup.
	150	(vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
	151	PCMPESTR_Fixup.
	152	(vex_w_table): Delete VPCMPESTR{I,M} entries.
	153	* i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
	154	Split 64-bit and non-64-bit variants.
	155	* opcodes/i386-tbl.h: Re-generate.
	156
582e12bf RS	157	2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
	158
	159	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
	160	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
	161	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
	162	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
	163	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
	164	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
	165	(OP_SVE_V_HSD): New macros.
	166	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
	167	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
	168	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
	169	(aarch64_opcode_table): Add new SVE instructions.
	170	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
	171	for rotation operands. Add new SVE operands.
	172	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
	173	(ins_sve_quad_index): Likewise.
	174	(ins_imm_rotate): Split into...
	175	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
	176	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
	177	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
	178	functions.
	179	(aarch64_ins_sve_addr_ri_s4): New function.
	180	(aarch64_ins_sve_quad_index): Likewise.
	181	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
	182	* aarch64-asm-2.c: Regenerate.
	183	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
	184	(ext_sve_quad_index): Likewise.
	185	(ext_imm_rotate): Split into...
	186	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
	187	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
	188	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
	189	functions.
	190	(aarch64_ext_sve_addr_ri_s4): New function.
	191	(aarch64_ext_sve_quad_index): Likewise.
	192	(aarch64_ext_sve_index): Allow quad indices.
	193	(do_misc_decoding): Likewise.
	194	* aarch64-dis-2.c: Regenerate.
	195	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
	196	aarch64_field_kinds.
	197	(OPD_F_OD_MASK): Widen by one bit.
	198	(OPD_F_NO_ZR): Bump accordingly.
	199	(get_operand_field_width): New function.
	200	* aarch64-opc.c (fields): Add new SVE fields.
	201	(operand_general_constraint_met_p): Handle new SVE operands.
	202	(aarch64_print_operand): Likewise.
	203	* aarch64-opc-2.c: Regenerate.
	204
f482d304 RS	205	2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
	206
	207	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
	208	(aarch64_feature_compnum): ...this.
	209	(SIMD_V8_3): Replace with...
	210	(COMPNUM): ...this.
	211	(CNUM_INSN): New macro.
	212	(aarch64_opcode_table): Use it for the complex number instructions.
	213
7db2c588 JB	214	2017-02-24 Jan Beulich <jbeulich@suse.com>
	215
	216	* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
	217
1e9d41d4 SL	218	2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
	219
	220	Add support for associating SPARC ASIs with an architecture level.
	221	* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
	222	* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
	223	decoding of SPARC ASIs.
	224
53c4d625 JB	225	2017-02-23 Jan Beulich <jbeulich@suse.com>
	226
	227	* i386-dis.c (get_valid_dis386): Don't special case VEX opcode
	228	82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
	229
11648de5 JB	230	2017-02-21 Jan Beulich <jbeulich@suse.com>
	231
	232	* aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
	233	1 (instead of to itself). Correct typo.
	234
f98d33be AW	235	2017-02-14 Andrew Waterman <andrew@sifive.com>
	236
	237	* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
	238	pseudoinstructions.
	239
773fb663 RS	240	2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
	241
	242	* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
	243	(aarch64_sys_reg_supported_p): Handle them.
	244
cc07cda6 CZ	245	2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
	246
	247	* arc-opc.c (UIMM6_20R): Define.
	248	(SIMM12_20): Use above.
	249	(SIMM12_20R): Define.
	250	(SIMM3_5_S): Use above.
	251	(UIMM7_A32_11R_S): Define.
	252	(UIMM7_9_S): Use above.
	253	(UIMM3_13R_S): Define.
	254	(SIMM11_A32_7_S): Use above.
	255	(SIMM9_8R): Define.
	256	(UIMM10_A32_8_S): Use above.
	257	(UIMM8_8R_S): Define.
	258	(W6): Use above.
	259	(arc_relax_opcodes): Use all above defines.
	260
66a5a740 VG	261	2017-02-15 Vineet Gupta <vgupta@synopsys.com>
	262
	263	* arc-regs.h: Distinguish some of the registers different on
	264	ARC700 and HS38 cpus.
	265
7e0de605 AM	266	2017-02-14 Alan Modra <amodra@gmail.com>
	267
	268	PR 21118
	269	* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
	270	with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
	271
54064fdb AM	272	2017-02-11 Stafford Horne <shorne@gmail.com>
	273	Alan Modra <amodra@gmail.com>
	274
	275	* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
	276	Use insn_bytes_value and insn_int_value directly instead. Don't
	277	free allocated memory until function exit.
	278
dce75bf9 NP	279	2017-02-10 Nicholas Piggin <npiggin@gmail.com>
	280
	281	* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
	282
1b7e3d2f NC	283	2017-02-03 Nick Clifton <nickc@redhat.com>
	284
	285	PR 21096
	286	* aarch64-opc.c (print_register_list): Ensure that the register
	287	list index will fir into the tb buffer.
	288	(print_register_offset_address): Likewise.
	289	* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
	290
8ec5cf65 AD	291	2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
	292
	293	PR 21056
	294	* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
	295	instructions when the previous fetch packet ends with a 32-bit
	296	instruction.
	297
a1aa5e81 DD	298	2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
	299
	300	* pru-opc.c: Remove vague reference to a future GDB port.
	301
add3afb2 NC	302	2017-01-20 Nick Clifton <nickc@redhat.com>
	303
	304	* po/ga.po: Updated Irish translation.
	305
c13a63b0 SN	306	2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
	307
	308	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
	309
9608051a YQ	310	2017-01-13 Yao Qi <yao.qi@linaro.org>
	311
	312	* m68k-dis.c (match_insn_m68k): Extend comments. Return -1
	313	if FETCH_DATA returns 0.
	314	(m68k_scan_mask): Likewise.
	315	(print_insn_m68k): Update code to handle -1 return value.
	316
f622ea96 YQ	317	2017-01-13 Yao Qi <yao.qi@linaro.org>
	318
	319	* m68k-dis.c (enum print_insn_arg_error): New.
	320	(NEXTBYTE): Replace -3 with
	321	PRINT_INSN_ARG_MEMORY_ERROR.
	322	(NEXTULONG): Likewise.
	323	(NEXTSINGLE): Likewise.
	324	(NEXTDOUBLE): Likewise.
	325	(NEXTDOUBLE): Likewise.
	326	(NEXTPACKED): Likewise.
	327	(FETCH_ARG): Likewise.
	328	(FETCH_DATA): Update comments.
	329	(print_insn_arg): Update comments. Replace magic numbers with
	330	enum.
	331	(match_insn_m68k): Likewise.
	332
620214f7 IT	333	2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
	334
	335	* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
	336	* i386-dis-evex.h (evex_table): Updated.
	337	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
	338	CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	339	(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
	340	* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
	341	(i386_cpu_flags): Add cpuavx512_vpopcntdq.
	342	* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
	343	* i386-init.h: Regenerate.
	344	* i386-tbl.h: Ditto.
	345
d95014a2 YQ	346	2017-01-12 Yao Qi <yao.qi@linaro.org>
	347
	348	* msp430-dis.c (msp430_singleoperand): Return -1 if
	349	msp430dis_opcode_signed returns false.
	350	(msp430_doubleoperand): Likewise.
	351	(msp430_branchinstr): Return -1 if
	352	msp430dis_opcode_unsigned returns false.
	353	(msp430x_calla_instr): Likewise.
	354	(print_insn_msp430): Likewise.
	355
0ae60c3e NC	356	2017-01-05 Nick Clifton <nickc@redhat.com>
	357
	358	PR 20946
	359	* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
	360	could not be matched.
	361	(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
	362	NULL.
	363
d74d4880 SN	364	2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
	365
	366	* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
	367	(aarch64_opcode_table): Use RCPC_INSN.
	368
cc917fd9 KC	369	2017-01-03 Kito Cheng <kito.cheng@gmail.com>
	370
	371	* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
	372	extension.
	373	* riscv-opcodes/all-opcodes: Likewise.
	374
b52d3cfc DP	375	2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
	376
	377	* riscv-dis.c (print_insn_args): Add fall through comment.
	378
f90c58d5 NC	379	2017-01-03 Nick Clifton <nickc@redhat.com>
	380
	381	* po/sr.po: New Serbian translation.
	382	* configure.ac (ALL_LINGUAS): Add sr.
	383	* configure: Regenerate.
	384
f47b0d4a AM	385	2017-01-02 Alan Modra <amodra@gmail.com>
	386
	387	* epiphany-desc.h: Regenerate.
	388	* epiphany-opc.h: Regenerate.
	389	* fr30-desc.h: Regenerate.
	390	* fr30-opc.h: Regenerate.
	391	* frv-desc.h: Regenerate.
	392	* frv-opc.h: Regenerate.
	393	* ip2k-desc.h: Regenerate.
	394	* ip2k-opc.h: Regenerate.
	395	* iq2000-desc.h: Regenerate.
	396	* iq2000-opc.h: Regenerate.
	397	* lm32-desc.h: Regenerate.
	398	* lm32-opc.h: Regenerate.
	399	* m32c-desc.h: Regenerate.
	400	* m32c-opc.h: Regenerate.
	401	* m32r-desc.h: Regenerate.
	402	* m32r-opc.h: Regenerate.
	403	* mep-desc.h: Regenerate.
	404	* mep-opc.h: Regenerate.
	405	* mt-desc.h: Regenerate.
	406	* mt-opc.h: Regenerate.
	407	* or1k-desc.h: Regenerate.
	408	* or1k-opc.h: Regenerate.
	409	* xc16x-desc.h: Regenerate.
	410	* xc16x-opc.h: Regenerate.
	411	* xstormy16-desc.h: Regenerate.
	412	* xstormy16-opc.h: Regenerate.
	413
2571583a AM	414	2017-01-02 Alan Modra <amodra@gmail.com>
	415
	416	Update year range in copyright notice of all files.
	417
5c1ad6b5	418	For older changes see ChangeLog-2016
3499769a	419	\f
5c1ad6b5	420	Copyright (C) 2017 Free Software Foundation, Inc.
3499769a AM	421
	422	Copying and distribution of this file, with or without modification,
	423	are permitted in any medium without royalty provided the copyright
	424	notice and this notice are preserved.
	425
	426	Local Variables:
	427	mode: change-log
	428	left-margin: 8
	429	fill-column: 74
	430	version-control: never
	431	End: