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PR25961, buffer overflow in coff_swap_aux_in
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
09c1e68a
AC		 12020-04-30 Alex Coplan <alex.coplan@arm.com>
2
3 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
4 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
5 (operand_general_constraint_met_p): validate
6 AARCH64_OPND_UNDEFINED.
7 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
8 for FLD_imm16_2.
9 * aarch64-asm-2.c: Regenerated.
10 * aarch64-dis-2.c: Regenerated.
11 * aarch64-opc-2.c: Regenerated.
12
9654d51a
NC		 132020-04-29 Nick Clifton <nickc@redhat.com>
14
15 PR 22699
16 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
17 and SETRC insns.
18
c2e71e57
NC		 192020-04-29 Nick Clifton <nickc@redhat.com>
20
21 * po/sv.po: Updated Swedish translation.
22
5c936ef5
NC		 232020-04-29 Nick Clifton <nickc@redhat.com>
24
25 PR 22699
26 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
27 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
28 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
29 IMM0_8U case.
30
bb2a1453
AS		 312020-04-21 Andreas Schwab <schwab@linux-m68k.org>
32
33 PR 25848
34 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
35 cmpi only on m68020up and cpu32.
36
c2e5c986
SD		 372020-04-20 Sudakshina Das <sudi.das@arm.com>
38
39 * aarch64-asm.c (aarch64_ins_none): New.
40 * aarch64-asm.h (ins_none): New declaration.
41 * aarch64-dis.c (aarch64_ext_none): New.
42 * aarch64-dis.h (ext_none): New declaration.
43 * aarch64-opc.c (aarch64_print_operand): Update case for
44 AARCH64_OPND_BARRIER_PSB.
45 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
46 (AARCH64_OPERANDS): Update inserter/extracter for
47 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
48 * aarch64-asm-2.c: Regenerated.
49 * aarch64-dis-2.c: Regenerated.
50 * aarch64-opc-2.c: Regenerated.
51
8a6e1d1d
SD		 522020-04-20 Sudakshina Das <sudi.das@arm.com>
53
54 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
55 (aarch64_feature_ras, RAS): Likewise.
56 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
57 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
58 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
59 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
60 * aarch64-asm-2.c: Regenerated.
61 * aarch64-dis-2.c: Regenerated.
62 * aarch64-opc-2.c: Regenerated.
63
e409955d
FS		 642020-04-17 Fredrik Strupe <fredrik@strupe.net>
65
66 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
67 (print_insn_neon): Support disassembly of conditional
68 instructions.
69
c54a9b56
DF		 702020-02-16 David Faust <david.faust@oracle.com>
71
72 * bpf-desc.c: Regenerate.
73 * bpf-desc.h: Likewise.
74 * bpf-opc.c: Regenerate.
75 * bpf-opc.h: Likewise.
76
bb651e8b
CL		 772020-04-07 Lili Cui <lili.cui@intel.com>
78
79 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
80 (prefix_table): New instructions (see prefixes above).
81 (rm_table): Likewise
82 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
83 CPU_ANY_TSXLDTRK_FLAGS.
84 (cpu_flags): Add CpuTSXLDTRK.
85 * i386-opc.h (enum): Add CpuTSXLDTRK.
86 (i386_cpu_flags): Add cputsxldtrk.
87 * i386-opc.tbl: Add XSUSPLDTRK insns.
88 * i386-init.h: Regenerate.
89 * i386-tbl.h: Likewise.
90
4b27d27c
L		 912020-04-02 Lili Cui <lili.cui@intel.com>
92
93 * i386-dis.c (prefix_table): New instructions serialize.
94 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
95 CPU_ANY_SERIALIZE_FLAGS.
96 (cpu_flags): Add CpuSERIALIZE.
97 * i386-opc.h (enum): Add CpuSERIALIZE.
98 (i386_cpu_flags): Add cpuserialize.
99 * i386-opc.tbl: Add SERIALIZE insns.
100 * i386-init.h: Regenerate.
101 * i386-tbl.h: Likewise.
102
832a5807
AM		 1032020-03-26 Alan Modra <amodra@gmail.com>
104
105 * disassemble.h (opcodes_assert): Declare.
106 (OPCODES_ASSERT): Define.
107 * disassemble.c: Don't include assert.h. Include opintl.h.
108 (opcodes_assert): New function.
109 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
110 (bfd_h8_disassemble): Reduce size of data array. Correctly
111 calculate maxlen. Omit insn decoding when insn length exceeds
112 maxlen. Exit from nibble loop when looking for E, before
113 accessing next data byte. Move processing of E outside loop.
114 Replace tests of maxlen in loop with assertions.
115
4c4addbe
AM		 1162020-03-26 Alan Modra <amodra@gmail.com>
117
118 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
119
a18cd0ca
AM		 1202020-03-25 Alan Modra <amodra@gmail.com>
121
122 * z80-dis.c (suffix): Init mybuf.
123
57cb32b3
AM		 1242020-03-22 Alan Modra <amodra@gmail.com>
125
126 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
127 successflly read from section.
128
beea5cc1
AM		 1292020-03-22 Alan Modra <amodra@gmail.com>
130
131 * arc-dis.c (find_format): Use ISO C string concatenation rather
132 than line continuation within a string. Don't access needs_limm
133 before testing opcode != NULL.
134
03704c77
AM		 1352020-03-22 Alan Modra <amodra@gmail.com>
136
137 * ns32k-dis.c (print_insn_arg): Update comment.
138 (print_insn_ns32k): Reduce size of index_offset array, and
139 initialize, passing -1 to print_insn_arg for args that are not
140 an index. Don't exit arg loop early. Abort on bad arg number.
141
d1023b5d
AM		 1422020-03-22 Alan Modra <amodra@gmail.com>
143
144 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
145 * s12z-opc.c: Formatting.
146 (operands_f): Return an int.
147 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
148 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
149 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
150 (exg_sex_discrim): Likewise.
151 (create_immediate_operand, create_bitfield_operand),
152 (create_register_operand_with_size, create_register_all_operand),
153 (create_register_all16_operand, create_simple_memory_operand),
154 (create_memory_operand, create_memory_auto_operand): Don't
155 segfault on malloc failure.
156 (z_ext24_decode): Return an int status, negative on fail, zero
157 on success.
158 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
159 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
160 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
161 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
162 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
163 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
164 (loop_primitive_decode, shift_decode, psh_pul_decode),
165 (bit_field_decode): Similarly.
166 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
167 to return value, update callers.
168 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
169 Don't segfault on NULL operand.
170 (decode_operation): Return OP_INVALID on first fail.
171 (decode_s12z): Check all reads, returning -1 on fail.
172
340f3ac8
AM		 1732020-03-20 Alan Modra <amodra@gmail.com>
174
175 * metag-dis.c (print_insn_metag): Don't ignore status from
176 read_memory_func.
177
fe90ae8a
AM		 1782020-03-20 Alan Modra <amodra@gmail.com>
179
180 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
181 Initialize parts of buffer not written when handling a possible
182 2-byte insn at end of section. Don't attempt decoding of such
183 an insn by the 4-byte machinery.
184
833d919c
AM		 1852020-03-20 Alan Modra <amodra@gmail.com>
186
187 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
188 partially filled buffer. Prevent lookup of 4-byte insns when
189 only VLE 2-byte insns are possible due to section size. Print
190 ".word" rather than ".long" for 2-byte leftovers.
191
327ef784
NC		 1922020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
193
194 PR 25641
195 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
196
1673df32
JB		 1972020-03-13 Jan Beulich <jbeulich@suse.com>
198
199 * i386-dis.c (X86_64_0D): Rename to ...
200 (X86_64_0E): ... this.
201
384f3689
L		 2022020-03-09 H.J. Lu <hongjiu.lu@intel.com>
203
204 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
205 * Makefile.in: Regenerated.
206
865e2027
JB		 2072020-03-09 Jan Beulich <jbeulich@suse.com>
208
209 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
210 3-operand pseudos.
211 * i386-tbl.h: Re-generate.
212
2f13234b
JB		 2132020-03-09 Jan Beulich <jbeulich@suse.com>
214
215 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
216 vprot*, vpsha*, and vpshl*.
217 * i386-tbl.h: Re-generate.
218
3fabc179
JB		 2192020-03-09 Jan Beulich <jbeulich@suse.com>
220
221 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
222 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
223 * i386-tbl.h: Re-generate.
224
3677e4c1
JB		 2252020-03-09 Jan Beulich <jbeulich@suse.com>
226
227 * i386-gen.c (set_bitfield): Ignore zero-length field names.
228 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
229 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
230 * i386-tbl.h: Re-generate.
231
4c4898e8
JB		 2322020-03-09 Jan Beulich <jbeulich@suse.com>
233
234 * i386-gen.c (struct template_arg, struct template_instance,
235 struct template_param, struct template, templates,
236 parse_template, expand_templates): New.
237 (process_i386_opcodes): Various local variables moved to
238 expand_templates. Call parse_template and expand_templates.
239 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
240 * i386-tbl.h: Re-generate.
241
bc49bfd8
JB		 2422020-03-06 Jan Beulich <jbeulich@suse.com>
243
244 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
245 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
246 register and memory source templates. Replace VexW= by VexW*
247 where applicable.
248 * i386-tbl.h: Re-generate.
249
4873e243
JB		 2502020-03-06 Jan Beulich <jbeulich@suse.com>
251
252 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
253 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
254 * i386-tbl.h: Re-generate.
255
672a349b
JB		 2562020-03-06 Jan Beulich <jbeulich@suse.com>
257
258 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
259 * i386-tbl.h: Re-generate.
260
4ed21b58
JB		 2612020-03-06 Jan Beulich <jbeulich@suse.com>
262
263 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
264 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
265 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
266 VexW0 on SSE2AVX variants.
267 (vmovq): Drop NoRex64 from XMM/XMM variants.
268 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
269 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
270 applicable use VexW0.
271 * i386-tbl.h: Re-generate.
272
643bb870
JB		 2732020-03-06 Jan Beulich <jbeulich@suse.com>
274
275 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
276 * i386-opc.h (Rex64): Delete.
277 (struct i386_opcode_modifier): Remove rex64 field.
278 * i386-opc.tbl (crc32): Drop Rex64.
279 Replace Rex64 with Size64 everywhere else.
280 * i386-tbl.h: Re-generate.
281
a23b33b3
JB		 2822020-03-06 Jan Beulich <jbeulich@suse.com>
283
284 * i386-dis.c (OP_E_memory): Exclude recording of used address
285 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
286 addressed memory operands for MPX insns.
287
a0497384
JB		 2882020-03-06 Jan Beulich <jbeulich@suse.com>
289
290 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
291 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
292 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
293 (ptwrite): Split into non-64-bit and 64-bit forms.
294 * i386-tbl.h: Re-generate.
295
b630c145
JB		 2962020-03-06 Jan Beulich <jbeulich@suse.com>
297
298 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
299 template.
300 * i386-tbl.h: Re-generate.
301
a847e322
JB		 3022020-03-04 Jan Beulich <jbeulich@suse.com>
303
304 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
305 (prefix_table): Move vmmcall here. Add vmgexit.
306 (rm_table): Replace vmmcall entry by prefix_table[] escape.
307 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
308 (cpu_flags): Add CpuSEV_ES entry.
309 * i386-opc.h (CpuSEV_ES): New.
310 (union i386_cpu_flags): Add cpusev_es field.
311 * i386-opc.tbl (vmgexit): New.
312 * i386-init.h, i386-tbl.h: Re-generate.
313
3cd7f3e3
L		 3142020-03-03 H.J. Lu <hongjiu.lu@intel.com>
315
316 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
317 with MnemonicSize.
318 * i386-opc.h (IGNORESIZE): New.
319 (DEFAULTSIZE): Likewise.
320 (IgnoreSize): Removed.
321 (DefaultSize): Likewise.
322 (MnemonicSize): New.
323 (i386_opcode_modifier): Replace ignoresize/defaultsize with
324 mnemonicsize.
325 * i386-opc.tbl (IgnoreSize): New.
326 (DefaultSize): Likewise.
327 * i386-tbl.h: Regenerated.
328
b8ba1385
SB		 3292020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
330
331 PR 25627
332 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
333 instructions.
334
10d97a0f
L		 3352020-03-03 H.J. Lu <hongjiu.lu@intel.com>
336
337 PR gas/25622
338 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
339 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
340 * i386-tbl.h: Regenerated.
341
dc1e8a47
AM		 3422020-02-26 Alan Modra <amodra@gmail.com>
343
344 * aarch64-asm.c: Indent labels correctly.
345 * aarch64-dis.c: Likewise.
346 * aarch64-gen.c: Likewise.
347 * aarch64-opc.c: Likewise.
348 * alpha-dis.c: Likewise.
349 * i386-dis.c: Likewise.
350 * nds32-asm.c: Likewise.
351 * nfp-dis.c: Likewise.
352 * visium-dis.c: Likewise.
353
265b4673
CZ		 3542020-02-25 Claudiu Zissulescu <claziss@gmail.com>
355
356 * arc-regs.h (int_vector_base): Make it available for all ARC
357 CPUs.
358
bd0cf5a6
NC		 3592020-02-20 Nelson Chu <nelson.chu@sifive.com>
360
361 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
362 changed.
363
fa164239
JW		 3642020-02-19 Nelson Chu <nelson.chu@sifive.com>
365
366 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
367 c.mv/c.li if rs1 is zero.
368
272a84b1
L		 3692020-02-17 H.J. Lu <hongjiu.lu@intel.com>
370
371 * i386-gen.c (cpu_flag_init): Replace CpuABM with
372 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
373 CPU_POPCNT_FLAGS.
374 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
375 * i386-opc.h (CpuABM): Removed.
376 (CpuPOPCNT): New.
377 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
378 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
379 popcnt. Remove CpuABM from lzcnt.
380 * i386-init.h: Regenerated.
381 * i386-tbl.h: Likewise.
382
1f730c46
JB		 3832020-02-17 Jan Beulich <jbeulich@suse.com>
384
385 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
386 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
387 VexW1 instead of open-coding them.
388 * i386-tbl.h: Re-generate.
389
c8f8eebc
JB		 3902020-02-17 Jan Beulich <jbeulich@suse.com>
391
392 * i386-opc.tbl (AddrPrefixOpReg): Define.
393 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
394 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
395 templates. Drop NoRex64.
396 * i386-tbl.h: Re-generate.
397
b9915cbc
JB		 3982020-02-17 Jan Beulich <jbeulich@suse.com>
399
400 PR gas/6518
401 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
402 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
403 into Intel syntax instance (with Unpsecified) and AT&T one
404 (without).
405 (vcvtneps2bf16): Likewise, along with folding the two so far
406 separate ones.
407 * i386-tbl.h: Re-generate.
408
ce504911
L		 4092020-02-16 H.J. Lu <hongjiu.lu@intel.com>
410
411 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
412 CPU_ANY_SSE4A_FLAGS.
413
dabec65d
AM		 4142020-02-17 Alan Modra <amodra@gmail.com>
415
416 * i386-gen.c (cpu_flag_init): Correct last change.
417
af5c13b0
L		 4182020-02-16 H.J. Lu <hongjiu.lu@intel.com>
419
420 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
421 CPU_ANY_SSE4_FLAGS.
422
6867aac0
L		 4232020-02-14 H.J. Lu <hongjiu.lu@intel.com>
424
425 * i386-opc.tbl (movsx): Remove Intel syntax comments.
426 (movzx): Likewise.
427
65fca059
JB		 4282020-02-14 Jan Beulich <jbeulich@suse.com>
429
430 PR gas/25438
431 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
432 destination for Cpu64-only variant.
433 (movzx): Fold patterns.
434 * i386-tbl.h: Re-generate.
435
7deea9aa
JB		 4362020-02-13 Jan Beulich <jbeulich@suse.com>
437
438 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
439 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
440 CPU_ANY_SSE4_FLAGS entry.
441 * i386-init.h: Re-generate.
442
6c0946d0
JB		 4432020-02-12 Jan Beulich <jbeulich@suse.com>
444
445 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
446 with Unspecified, making the present one AT&T syntax only.
447 * i386-tbl.h: Re-generate.
448
ddb56fe6
JB		 4492020-02-12 Jan Beulich <jbeulich@suse.com>
450
451 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
452 * i386-tbl.h: Re-generate.
453
5990e377
JB		 4542020-02-12 Jan Beulich <jbeulich@suse.com>
455
456 PR gas/24546
457 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
458 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
459 Amd64 and Intel64 templates.
460 (call, jmp): Likewise for far indirect variants. Dro
461 Unspecified.
462 * i386-tbl.h: Re-generate.
463
50128d0c
JB		 4642020-02-11 Jan Beulich <jbeulich@suse.com>
465
466 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
467 * i386-opc.h (ShortForm): Delete.
468 (struct i386_opcode_modifier): Remove shortform field.
469 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
470 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
471 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
472 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
473 Drop ShortForm.
474 * i386-tbl.h: Re-generate.
475
1e05b5c4
JB		 4762020-02-11 Jan Beulich <jbeulich@suse.com>
477
478 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
479 fucompi): Drop ShortForm from operand-less templates.
480 * i386-tbl.h: Re-generate.
481
2f5dd314
AM		 4822020-02-11 Alan Modra <amodra@gmail.com>
483
484 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
485 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
486 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
487 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
488 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
489
5aae9ae9
MM		 4902020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
491
492 * arm-dis.c (print_insn_cde): Define 'V' parse character.
493 (cde_opcodes): Add VCX* instructions.
494
4934a27c
MM		 4952020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
496 Matthew Malcomson <matthew.malcomson@arm.com>
497
498 * arm-dis.c (struct cdeopcode32): New.
499 (CDE_OPCODE): New macro.
500 (cde_opcodes): New disassembly table.
501 (regnames): New option to table.
502 (cde_coprocs): New global variable.
503 (print_insn_cde): New
504 (print_insn_thumb32): Use print_insn_cde.
505 (parse_arm_disassembler_options): Parse coprocN args.
506
4b5aaf5f
L		 5072020-02-10 H.J. Lu <hongjiu.lu@intel.com>
508
509 PR gas/25516
510 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
511 with ISA64.
512 * i386-opc.h (AMD64): Removed.
513 (Intel64): Likewose.
514 (AMD64): New.
515 (INTEL64): Likewise.
516 (INTEL64ONLY): Likewise.
517 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
518 * i386-opc.tbl (Amd64): New.
519 (Intel64): Likewise.
520 (Intel64Only): Likewise.
521 Replace AMD64 with Amd64. Update sysenter/sysenter with
522 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
523 * i386-tbl.h: Regenerated.
524
9fc0b501
SB		 5252020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
526
527 PR 25469
528 * z80-dis.c: Add support for GBZ80 opcodes.
529
c5d7be0c
AM		 5302020-02-04 Alan Modra <amodra@gmail.com>
531
532 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
533
44e4546f
AM		 5342020-02-03 Alan Modra <amodra@gmail.com>
535
536 * m32c-ibld.c: Regenerate.
537
b2b1453a
AM		 5382020-02-01 Alan Modra <amodra@gmail.com>
539
540 * frv-ibld.c: Regenerate.
541
4102be5c
JB		 5422020-01-31 Jan Beulich <jbeulich@suse.com>
543
544 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
545 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
546 (OP_E_memory): Replace xmm_mdq_mode case label by
547 vex_scalar_w_dq_mode one.
548 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
549
825bd36c
JB		 5502020-01-31 Jan Beulich <jbeulich@suse.com>
551
552 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
553 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
554 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
555 (intel_operand_size): Drop vex_w_dq_mode case label.
556
c3036ed0
RS		 5572020-01-31 Richard Sandiford <richard.sandiford@arm.com>
558
559 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
560 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
561
0c115f84
AM		 5622020-01-30 Alan Modra <amodra@gmail.com>
563
564 * m32c-ibld.c: Regenerate.
565
bd434cc4
JM		 5662020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
567
568 * bpf-opc.c: Regenerate.
569
aeab2b26
JB		 5702020-01-30 Jan Beulich <jbeulich@suse.com>
571
572 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
573 (dis386): Use them to replace C2/C3 table entries.
574 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
575 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
576 ones. Use Size64 instead of DefaultSize on Intel64 ones.
577 * i386-tbl.h: Re-generate.
578
62b3f548
JB		 5792020-01-30 Jan Beulich <jbeulich@suse.com>
580
581 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
582 forms.
583 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
584 DefaultSize.
585 * i386-tbl.h: Re-generate.
586
1bd8ae10
AM		 5872020-01-30 Alan Modra <amodra@gmail.com>
588
589 * tic4x-dis.c (tic4x_dp): Make unsigned.
590
bc31405e
L		 5912020-01-27 H.J. Lu <hongjiu.lu@intel.com>
592 Jan Beulich <jbeulich@suse.com>
593
594 PR binutils/25445
595 * i386-dis.c (MOVSXD_Fixup): New function.
596 (movsxd_mode): New enum.
597 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
598 (intel_operand_size): Handle movsxd_mode.
599 (OP_E_register): Likewise.
600 (OP_G): Likewise.
601 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
602 register on movsxd. Add movsxd with 16-bit destination register
603 for AMD64 and Intel64 ISAs.
604 * i386-tbl.h: Regenerated.
605
7568c93b
TC		 6062020-01-27 Tamar Christina <tamar.christina@arm.com>
607
608 PR 25403
609 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
610 * aarch64-asm-2.c: Regenerate
611 * aarch64-dis-2.c: Likewise.
612 * aarch64-opc-2.c: Likewise.
613
c006a730
JB		 6142020-01-21 Jan Beulich <jbeulich@suse.com>
615
616 * i386-opc.tbl (sysret): Drop DefaultSize.
617 * i386-tbl.h: Re-generate.
618
c906a69a
JB		 6192020-01-21 Jan Beulich <jbeulich@suse.com>
620
621 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
622 Dword.
623 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
624 * i386-tbl.h: Re-generate.
625
26916852
NC		 6262020-01-20 Nick Clifton <nickc@redhat.com>
627
628 * po/de.po: Updated German translation.
629 * po/pt_BR.po: Updated Brazilian Portuguese translation.
630 * po/uk.po: Updated Ukranian translation.
631
4d6cbb64
AM		 6322020-01-20 Alan Modra <amodra@gmail.com>
633
634 * hppa-dis.c (fput_const): Remove useless cast.
635
2bddb71a
AM		 6362020-01-20 Alan Modra <amodra@gmail.com>
637
638 * arm-dis.c (print_insn_arm): Wrap 'T' value.
639
1b1bb2c6
NC		 6402020-01-18 Nick Clifton <nickc@redhat.com>
641
642 * configure: Regenerate.
643 * po/opcodes.pot: Regenerate.
644
ae774686
NC		 6452020-01-18 Nick Clifton <nickc@redhat.com>
646
647 Binutils 2.34 branch created.
648
07f1f3aa
CB		 6492020-01-17 Christian Biesinger <cbiesinger@google.com>
650
651 * opintl.h: Fix spelling error (seperate).
652
42e04b36
L		 6532020-01-17 H.J. Lu <hongjiu.lu@intel.com>
654
655 * i386-opc.tbl: Add {vex} pseudo prefix.
656 * i386-tbl.h: Regenerated.
657
2da2eaf4
AV		 6582020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
659
660 PR 25376
661 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
662 (neon_opcodes): Likewise.
663 (select_arm_features): Make sure we enable MVE bits when selecting
664 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
665 any architecture.
666
d0849eed
JB		 6672020-01-16 Jan Beulich <jbeulich@suse.com>
668
669 * i386-opc.tbl: Drop stale comment from XOP section.
670
9cf70a44
JB		 6712020-01-16 Jan Beulich <jbeulich@suse.com>
672
673 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
674 (extractps): Add VexWIG to SSE2AVX forms.
675 * i386-tbl.h: Re-generate.
676
4814632e
JB		 6772020-01-16 Jan Beulich <jbeulich@suse.com>
678
679 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
680 Size64 from and use VexW1 on SSE2AVX forms.
681 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
682 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
683 * i386-tbl.h: Re-generate.
684
aad09917
AM		 6852020-01-15 Alan Modra <amodra@gmail.com>
686
687 * tic4x-dis.c (tic4x_version): Make unsigned long.
688 (optab, optab_special, registernames): New file scope vars.
689 (tic4x_print_register): Set up registernames rather than
690 malloc'd registertable.
691 (tic4x_disassemble): Delete optable and optable_special. Use
692 optab and optab_special instead. Throw away old optab,
693 optab_special and registernames when info->mach changes.
694
7a6bf3be
SB		 6952020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
696
697 PR 25377
698 * z80-dis.c (suffix): Use .db instruction to generate double
699 prefix.
700
ca1eaac0
AM		 7012020-01-14 Alan Modra <amodra@gmail.com>
702
703 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
704 values to unsigned before shifting.
705
1d67fe3b
TT		 7062020-01-13 Thomas Troeger <tstroege@gmx.de>
707
708 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
709 flow instructions.
710 (print_insn_thumb16, print_insn_thumb32): Likewise.
711 (print_insn): Initialize the insn info.
712 * i386-dis.c (print_insn): Initialize the insn info fields, and
713 detect jumps.
714
5e4f7e05
CZ		 7152012-01-13 Claudiu Zissulescu <claziss@gmail.com>
716
717 * arc-opc.c (C_NE): Make it required.
718
b9fe6b8a
CZ		 7192012-01-13 Claudiu Zissulescu <claziss@gmail.com>
720
721 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
722 reserved register name.
723
90dee485
AM		 7242020-01-13 Alan Modra <amodra@gmail.com>
725
726 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
727 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
728
febda64f
AM		 7292020-01-13 Alan Modra <amodra@gmail.com>
730
731 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
732 result of wasm_read_leb128 in a uint64_t and check that bits
733 are not lost when copying to other locals. Use uint32_t for
734 most locals. Use PRId64 when printing int64_t.
735
df08b588
AM		 7362020-01-13 Alan Modra <amodra@gmail.com>
737
738 * score-dis.c: Formatting.
739 * score7-dis.c: Formatting.
740
b2c759ce
AM		 7412020-01-13 Alan Modra <amodra@gmail.com>
742
743 * score-dis.c (print_insn_score48): Use unsigned variables for
744 unsigned values. Don't left shift negative values.
745 (print_insn_score32): Likewise.
746 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
747
5496abe1
AM		 7482020-01-13 Alan Modra <amodra@gmail.com>
749
750 * tic4x-dis.c (tic4x_print_register): Remove dead code.
751
202e762b
AM		 7522020-01-13 Alan Modra <amodra@gmail.com>
753
754 * fr30-ibld.c: Regenerate.
755
7ef412cf
AM		 7562020-01-13 Alan Modra <amodra@gmail.com>
757
758 * xgate-dis.c (print_insn): Don't left shift signed value.
759 (ripBits): Formatting, use 1u.
760
7f578b95
AM		 7612020-01-10 Alan Modra <amodra@gmail.com>
762
763 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
764 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
765
441af85b
AM		 7662020-01-10 Alan Modra <amodra@gmail.com>
767
768 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
769 and XRREG value earlier to avoid a shift with negative exponent.
770 * m10200-dis.c (disassemble): Similarly.
771
bce58db4
NC		 7722020-01-09 Nick Clifton <nickc@redhat.com>
773
774 PR 25224
775 * z80-dis.c (ld_ii_ii): Use correct cast.
776
40c75bc8
SB		 7772020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
778
779 PR 25224
780 * z80-dis.c (ld_ii_ii): Use character constant when checking
781 opcode byte value.
782
d835a58b
JB		 7832020-01-09 Jan Beulich <jbeulich@suse.com>
784
785 * i386-dis.c (SEP_Fixup): New.
786 (SEP): Define.
787 (dis386_twobyte): Use it for sysenter/sysexit.
788 (enum x86_64_isa): Change amd64 enumerator to value 1.
789 (OP_J): Compare isa64 against intel64 instead of amd64.
790 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
791 forms.
792 * i386-tbl.h: Re-generate.
793
030a2e78
AM		 7942020-01-08 Alan Modra <amodra@gmail.com>
795
796 * z8k-dis.c: Include libiberty.h
797 (instr_data_s): Make max_fetched unsigned.
798 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
799 Don't exceed byte_info bounds.
800 (output_instr): Make num_bytes unsigned.
801 (unpack_instr): Likewise for nibl_count and loop.
802 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
803 idx unsigned.
804 * z8k-opc.h: Regenerate.
805
bb82aefe
SV		 8062020-01-07 Shahab Vahedi <shahab@synopsys.com>
807
808 * arc-tbl.h (llock): Use 'LLOCK' as class.
809 (llockd): Likewise.
810 (scond): Use 'SCOND' as class.
811 (scondd): Likewise.
812 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
813 (scondd): Likewise.
814
cc6aa1a6
AM		 8152020-01-06 Alan Modra <amodra@gmail.com>
816
817 * m32c-ibld.c: Regenerate.
818
660e62b1
AM		 8192020-01-06 Alan Modra <amodra@gmail.com>
820
821 PR 25344
822 * z80-dis.c (suffix): Don't use a local struct buffer copy.
823 Peek at next byte to prevent recursion on repeated prefix bytes.
824 Ensure uninitialised "mybuf" is not accessed.
825 (print_insn_z80): Don't zero n_fetch and n_used here,..
826 (print_insn_z80_buf): ..do it here instead.
827
c9ae58fe
AM		 8282020-01-04 Alan Modra <amodra@gmail.com>
829
830 * m32r-ibld.c: Regenerate.
831
5f57d4ec
AM		 8322020-01-04 Alan Modra <amodra@gmail.com>
833
834 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
835
2c5c1196
AM		 8362020-01-04 Alan Modra <amodra@gmail.com>
837
838 * crx-dis.c (match_opcode): Avoid shift left of signed value.
839
2e98c6c5
AM		 8402020-01-04 Alan Modra <amodra@gmail.com>
841
842 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
843
567dfba2
JB		 8442020-01-03 Jan Beulich <jbeulich@suse.com>
845
5437a02a
JB		 846 * aarch64-tbl.h (aarch64_opcode_table): Use
847 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
848
8492020-01-03 Jan Beulich <jbeulich@suse.com>
850
851 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 852 forms of SUDOT and USDOT.
853
8c45011a
JB		 8542020-01-03 Jan Beulich <jbeulich@suse.com>
855
5437a02a 856 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 857 uzip{1,2}.
858 * opcodes/aarch64-dis-2.c: Re-generate.
859
f4950f76
JB		 8602020-01-03 Jan Beulich <jbeulich@suse.com>
861
5437a02a 862 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 863 FMMLA encoding.
864 * opcodes/aarch64-dis-2.c: Re-generate.
865
6655dba2
SB		 8662020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
867
868 * z80-dis.c: Add support for eZ80 and Z80 instructions.
869
b14ce8bf
AM		 8702020-01-01 Alan Modra <amodra@gmail.com>
871
872 Update year range in copyright notice of all files.
873
0b114740 874For older changes see ChangeLog-2019
3499769a 875\f
0b114740 876Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 877
878Copying and distribution of this file, with or without modification,
879are permitted in any medium without royalty provided the copyright
880notice and this notice are preserved.
881
882Local Variables:
883mode: change-log
884left-margin: 8
885fill-column: 74
886version-control: never
887End:
GDB Binutils - Deliverables
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