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x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit mode
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4dd4e639
JB		 12018-11-06 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
4 vpbroadcast{d,q} with GPR operand.
5
9819647a
JB		 62018-11-06 Jan Beulich <jbeulich@suse.com>
7
8 * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
9 * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
10 cases up one level in the hierarchy.
11
58a211d2
JB		 122018-11-06 Jan Beulich <jbeulich@suse.com>
13
14 * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
15 MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
16 (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
17 into MOD_VEX_0F93_P_3_LEN_0.
18 (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
19 operand cases up one level in the hierarchy.
20
b50c9f31
JB		 212018-11-06 Jan Beulich <jbeulich@suse.com>
22
23 * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
24 VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
25 EVEX_W_0F3A22_P_2): Delete.
26 (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
27 entries up one level in the hierarchy.
28 (OP_E_memory): Handle dq_mode when determining Disp8 shift
29 value.
30 * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
31 entries up one level in the hierarchy.
32 * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
33 VexWIG for AVX flavors.
34 * i386-tbl.h: Re-generate.
35
931d03b7
JB		 362018-11-06 Jan Beulich <jbeulich@suse.com>
37
38 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
39 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
40 vcvtusi2ss, kmovd): Drop VexW=1.
41 * i386-tbl.h: Re-generate.
42
fd71a375
JB		 432018-11-06 Jan Beulich <jbeulich@suse.com>
44
45 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
46 EVex512, EVexLIG, EVexDYN): New.
47 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
48 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
49 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
50 of EVex=4 (aka EVexLIG).
51 * i386-tbl.h: Re-generate.
52
563c7eef
JB		 532018-11-06 Jan Beulich <jbeulich@suse.com>
54
55 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
56 (vpmaxub): Re-order attributes on AVX512BW flavor.
57 * i386-tbl.h: Re-generate.
58
0aaca1d9
JB		 592018-11-06 Jan Beulich <jbeulich@suse.com>
60
61 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
62 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
63 Vex=1 on AVX / AVX2 flavors.
64 (vpmaxub): Re-order attributes on AVX512BW flavor.
65 * i386-tbl.h: Re-generate.
66
bbae6b11
JB		 672018-11-06 Jan Beulich <jbeulich@suse.com>
68
69 * i386-opc.tbl (VexW0, VexW1): New.
70 (vphadd*, vphsub*): Use VexW0 on XOP variants.
71 * i386-tbl.h: Re-generate.
72
192c2bfb
JD		 732018-10-22 John Darrington <john@darrington.wattle.id.au>
74
75 * s12z-dis.c (decode_possible_symbol): Add fallback case.
76 (rel_15_7): Likewise.
77
0b347048
TC		 782018-10-19 Tamar Christina <tamar.christina@arm.com>
79
80 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
81 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
82 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
83
66e6f0b7
MM		 842018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
85
86 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
87 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
88
673fe0f0
JB		 892018-10-10 Jan Beulich <jbeulich@suse.com>
90
91 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
92 Size64. Add Size.
93 * i386-opc.h (Size16, Size32, Size64): Delete.
94 (Size): New.
95 (SIZE16, SIZE32, SIZE64): Define.
96 (struct i386_opcode_modifier): Drop size16, size32, and size64.
97 Add size.
98 * i386-opc.tbl (Size16, Size32, Size64): Define.
99 * i386-tbl.h: Re-generate.
100
104fefee
SD		 1012018-10-09 Sudakshina Das <sudi.das@arm.com>
102
103 * aarch64-opc.c (operand_general_constraint_met_p): Add
104 SSBS in the check for one-bit immediate.
105 (aarch64_sys_regs): New entry for SSBS.
106 (aarch64_sys_reg_supported_p): New check for above.
107 (aarch64_pstatefields): New entry for SSBS.
108 (aarch64_pstatefield_supported_p): New check for above.
109
a97330e7
SD		 1102018-10-09 Sudakshina Das <sudi.das@arm.com>
111
112 * aarch64-opc.c (aarch64_sys_regs): New entries for
113 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
114 (aarch64_sys_reg_supported_p): New checks for above.
115
ff605452
SD		 1162018-10-09 Sudakshina Das <sudi.das@arm.com>
117
118 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
119 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
120 with the hint immediate.
121 * aarch64-opc.c (aarch64_hint_options): New entries for
122 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
123 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
124 while checking for HINT_OPD_F_NOPRINT flag.
125 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
126 extract value.
127 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
128 (aarch64_opcode_table): Add entry for BTI.
129 (AARCH64_OPERANDS): Add new description for BTI targets.
130 * aarch64-asm-2.c: Regenerate.
131 * aarch64-dis-2.c: Regenerate.
132 * aarch64-opc-2.c: Regenerate.
133
af4bcb4c
SD		 1342018-10-09 Sudakshina Das <sudi.das@arm.com>
135
136 * aarch64-opc.c (aarch64_sys_regs): New entries for
137 rndr and rndrrs.
138 (aarch64_sys_reg_supported_p): New check for above.
139
3fd229a4
SD		 1402018-10-09 Sudakshina Das <sudi.das@arm.com>
141
142 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
143 (aarch64_sys_ins_reg_supported_p): New check for above.
144
2ac435d4
SD		 1452018-10-09 Sudakshina Das <sudi.das@arm.com>
146
147 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
148 AARCH64_OPND_SYSREG_SR.
149 * aarch64-opc.c (aarch64_print_operand): Likewise.
150 (aarch64_sys_regs_sr): Define table.
151 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
152 AARCH64_FEATURE_PREDRES.
153 * aarch64-tbl.h (aarch64_feature_predres): New.
154 (PREDRES, PREDRES_INSN): New.
155 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
156 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
157 * aarch64-asm-2.c: Regenerate.
158 * aarch64-dis-2.c: Regenerate.
159 * aarch64-opc-2.c: Regenerate.
160
68dfbb92
SD		 1612018-10-09 Sudakshina Das <sudi.das@arm.com>
162
163 * aarch64-tbl.h (aarch64_feature_sb): New.
164 (SB, SB_INSN): New.
165 (aarch64_opcode_table): Add entry for sb.
166 * aarch64-asm-2.c: Regenerate.
167 * aarch64-dis-2.c: Regenerate.
168 * aarch64-opc-2.c: Regenerate.
169
13c60ad7
SD		 1702018-10-09 Sudakshina Das <sudi.das@arm.com>
171
172 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
173 (aarch64_feature_frintts): New.
174 (FLAGMANIP, FRINTTS): New.
175 (aarch64_opcode_table): Add entries for xaflag, axflag
176 and frint[32,64][x,z] instructions.
177 * aarch64-asm-2.c: Regenerate.
178 * aarch64-dis-2.c: Regenerate.
179 * aarch64-opc-2.c: Regenerate.
180
70d56181
SD		 1812018-10-09 Sudakshina Das <sudi.das@arm.com>
182
183 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
184 (ARMV8_5, V8_5_INSN): New.
185
780f601c
TC		 1862018-10-08 Tamar Christina <tamar.christina@arm.com>
187
188 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
189
a4e78aa5
L		 1902018-10-05 H.J. Lu <hongjiu.lu@intel.com>
191
192 * i386-dis.c (rm_table): Add enclv.
193 * i386-opc.tbl: Add enclv.
194 * i386-tbl.h: Regenerated.
195
7fadb25d
SD		 1962018-10-05 Sudakshina Das <sudi.das@arm.com>
197
198 * arm-dis.c (arm_opcodes): Add sb.
199 (thumb32_opcodes): Likewise.
200
07f5f4c6
RH		 2012018-10-05 Richard Henderson <rth@twiddle.net>
202 Stafford Horne <shorne@gmail.com>
203
204 * or1k-desc.c: Regenerate.
205 * or1k-desc.h: Regenerate.
206 * or1k-opc.c: Regenerate.
207 * or1k-opc.h: Regenerate.
208 * or1k-opinst.c: Regenerate.
209
c8e98e36
SH		 2102018-10-05 Richard Henderson <rth@twiddle.net>
211
212 * or1k-asm.c: Regenerated.
213 * or1k-desc.c: Regenerated.
214 * or1k-desc.h: Regenerated.
215 * or1k-dis.c: Regenerated.
216 * or1k-ibld.c: Regenerated.
217 * or1k-opc.c: Regenerated.
218 * or1k-opc.h: Regenerated.
219 * or1k-opinst.c: Regenerated.
220
1c4f3780
RH		 2212018-10-05 Richard Henderson <rth@twiddle.net>
222
223 * or1k-asm.c: Regenerate.
224
bde90be2
TC		 2252018-10-03 Tamar Christina <tamar.christina@arm.com>
226
227 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
228 * aarch64-dis.c (print_operands): Refactor to take notes.
229 (print_verifier_notes): New.
230 (print_aarch64_insn): Apply constraint verifier.
231 (print_insn_aarch64_word): Update call to print_aarch64_insn.
232 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
233
a68f4cd2
TC		 2342018-10-03 Tamar Christina <tamar.christina@arm.com>
235
236 * aarch64-opc.c (init_insn_block): New.
237 (verify_constraints, aarch64_is_destructive_by_operands): New.
238 * aarch64-opc.h (verify_constraints): New.
239
755b748f
TC		 2402018-10-03 Tamar Christina <tamar.christina@arm.com>
241
242 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
243 * aarch64-opc.c (verify_ldpsw): Update arguments.
244
1d482394
TC		 2452018-10-03 Tamar Christina <tamar.christina@arm.com>
246
247 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
248 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
249
7e84b55d
TC		 2502018-10-03 Tamar Christina <tamar.christina@arm.com>
251
252 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
253 * aarch64-dis.c (insn_sequence): New.
254
eae424ae
TC		 2552018-10-03 Tamar Christina <tamar.christina@arm.com>
256
257 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
258 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
259 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
260 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
261 constraints.
262 (_SVE_INSNC): New.
263 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
264 constraints.
265 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
266 F_SCAN flags.
267 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
268 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
269 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
270 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
271 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
272 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
273 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
274
64a336ac
PD		 2752018-10-02 Palmer Dabbelt <palmer@sifive.com>
276
277 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
278
6031ac35
SL		 2792018-09-23 Sandra Loosemore <sandra@codesourcery.com>
280
281 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
282 are used when extracting signed fields and converting them to
283 potentially 64-bit types.
284
f24ff6e9
SM		 2852018-09-21 Simon Marchi <simon.marchi@ericsson.com>
286
287 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
288 * Makefile.in: Re-generate.
289 * aclocal.m4: Re-generate.
290 * configure: Re-generate.
291 * configure.ac: Remove check for -Wno-missing-field-initializers.
292 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
293 (csky_v2_opcodes): Likewise.
294
53b6d6f5
MR		 2952018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
296
297 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
298
fbaf61ad
NC		 2992018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
300
301 * nds32-asm.c (operand_fields): Remove the unused fields.
302 (nds32_opcodes): Remove the unused instructions.
303 * nds32-dis.c (nds32_ex9_info): Removed.
304 (nds32_parse_opcode): Updated.
305 (print_insn_nds32): Likewise.
306 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
307 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
308 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
309 build_opcode_hash_table): New functions.
310 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
311 nds32_opcode_table): New.
312 (hw_ktabs): Declare it to a pointer rather than an array.
313 (build_hash_table): Removed.
314 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
315 SYN_ROPT and upadte HW_GPR and HW_INT.
316 * nds32-dis.c (keywords): Remove const.
317 (match_field): New function.
318 (nds32_parse_opcode): Updated.
319 * disassemble.c (disassemble_init_for_target):
320 Add disassemble_init_nds32.
321 * nds32-dis.c (eum map_type): New.
322 (nds32_private_data): Likewise.
323 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
324 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
325 (print_insn_nds32): Updated.
326 * nds32-asm.c (parse_aext_reg): Add new parameter.
327 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
328 are allowed to use.
329 All callers changed.
330 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
331 (operand_fields): Add new fields.
332 (nds32_opcodes): Add new instructions.
333 (keyword_aridxi_mx): New keyword.
334 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
335 and NASM_ATTR_ZOL.
336 (ALU2_1, ALU2_2, ALU2_3): New macros.
337 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
338
4e2b1898
JW		 3392018-09-17 Kito Cheng <kito@andestech.com>
340
341 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
342
04e2a182
L		 3432018-09-17 H.J. Lu <hongjiu.lu@intel.com>
344
345 PR gas/23670
346 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
347 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
348 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
349 (EVEX_LEN_0F7E_P_1): Likewise.
350 (EVEX_LEN_0F7E_P_2): Likewise.
351 (EVEX_LEN_0FD6_P_2): Likewise.
352 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
353 (EVEX_LEN_TABLE): Likewise.
354 (EVEX_LEN_0F6E_P_2): New enum.
355 (EVEX_LEN_0F7E_P_1): Likewise.
356 (EVEX_LEN_0F7E_P_2): Likewise.
357 (EVEX_LEN_0FD6_P_2): Likewise.
358 (evex_len_table): New.
359 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
360 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
361 * i386-tbl.h: Regenerated.
362
d5f787c2
L		 3632018-09-17 H.J. Lu <hongjiu.lu@intel.com>
364
365 PR gas/23665
366 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
367 VEX_LEN_0F7E_P_2 entries.
368 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
369 * i386-tbl.h: Regenerated.
370
ec6f095a
L		 3712018-09-17 H.J. Lu <hongjiu.lu@intel.com>
372
373 * i386-dis.c (VZERO_Fixup): Removed.
374 (VZERO): Likewise.
375 (VEX_LEN_0F10_P_1): Likewise.
376 (VEX_LEN_0F10_P_3): Likewise.
377 (VEX_LEN_0F11_P_1): Likewise.
378 (VEX_LEN_0F11_P_3): Likewise.
379 (VEX_LEN_0F2E_P_0): Likewise.
380 (VEX_LEN_0F2E_P_2): Likewise.
381 (VEX_LEN_0F2F_P_0): Likewise.
382 (VEX_LEN_0F2F_P_2): Likewise.
383 (VEX_LEN_0F51_P_1): Likewise.
384 (VEX_LEN_0F51_P_3): Likewise.
385 (VEX_LEN_0F52_P_1): Likewise.
386 (VEX_LEN_0F53_P_1): Likewise.
387 (VEX_LEN_0F58_P_1): Likewise.
388 (VEX_LEN_0F58_P_3): Likewise.
389 (VEX_LEN_0F59_P_1): Likewise.
390 (VEX_LEN_0F59_P_3): Likewise.
391 (VEX_LEN_0F5A_P_1): Likewise.
392 (VEX_LEN_0F5A_P_3): Likewise.
393 (VEX_LEN_0F5C_P_1): Likewise.
394 (VEX_LEN_0F5C_P_3): Likewise.
395 (VEX_LEN_0F5D_P_1): Likewise.
396 (VEX_LEN_0F5D_P_3): Likewise.
397 (VEX_LEN_0F5E_P_1): Likewise.
398 (VEX_LEN_0F5E_P_3): Likewise.
399 (VEX_LEN_0F5F_P_1): Likewise.
400 (VEX_LEN_0F5F_P_3): Likewise.
401 (VEX_LEN_0FC2_P_1): Likewise.
402 (VEX_LEN_0FC2_P_3): Likewise.
403 (VEX_LEN_0F3A0A_P_2): Likewise.
404 (VEX_LEN_0F3A0B_P_2): Likewise.
405 (VEX_W_0F10_P_0): Likewise.
406 (VEX_W_0F10_P_1): Likewise.
407 (VEX_W_0F10_P_2): Likewise.
408 (VEX_W_0F10_P_3): Likewise.
409 (VEX_W_0F11_P_0): Likewise.
410 (VEX_W_0F11_P_1): Likewise.
411 (VEX_W_0F11_P_2): Likewise.
412 (VEX_W_0F11_P_3): Likewise.
413 (VEX_W_0F12_P_0_M_0): Likewise.
414 (VEX_W_0F12_P_0_M_1): Likewise.
415 (VEX_W_0F12_P_1): Likewise.
416 (VEX_W_0F12_P_2): Likewise.
417 (VEX_W_0F12_P_3): Likewise.
418 (VEX_W_0F13_M_0): Likewise.
419 (VEX_W_0F14): Likewise.
420 (VEX_W_0F15): Likewise.
421 (VEX_W_0F16_P_0_M_0): Likewise.
422 (VEX_W_0F16_P_0_M_1): Likewise.
423 (VEX_W_0F16_P_1): Likewise.
424 (VEX_W_0F16_P_2): Likewise.
425 (VEX_W_0F17_M_0): Likewise.
426 (VEX_W_0F28): Likewise.
427 (VEX_W_0F29): Likewise.
428 (VEX_W_0F2B_M_0): Likewise.
429 (VEX_W_0F2E_P_0): Likewise.
430 (VEX_W_0F2E_P_2): Likewise.
431 (VEX_W_0F2F_P_0): Likewise.
432 (VEX_W_0F2F_P_2): Likewise.
433 (VEX_W_0F50_M_0): Likewise.
434 (VEX_W_0F51_P_0): Likewise.
435 (VEX_W_0F51_P_1): Likewise.
436 (VEX_W_0F51_P_2): Likewise.
437 (VEX_W_0F51_P_3): Likewise.
438 (VEX_W_0F52_P_0): Likewise.
439 (VEX_W_0F52_P_1): Likewise.
440 (VEX_W_0F53_P_0): Likewise.
441 (VEX_W_0F53_P_1): Likewise.
442 (VEX_W_0F58_P_0): Likewise.
443 (VEX_W_0F58_P_1): Likewise.
444 (VEX_W_0F58_P_2): Likewise.
445 (VEX_W_0F58_P_3): Likewise.
446 (VEX_W_0F59_P_0): Likewise.
447 (VEX_W_0F59_P_1): Likewise.
448 (VEX_W_0F59_P_2): Likewise.
449 (VEX_W_0F59_P_3): Likewise.
450 (VEX_W_0F5A_P_0): Likewise.
451 (VEX_W_0F5A_P_1): Likewise.
452 (VEX_W_0F5A_P_3): Likewise.
453 (VEX_W_0F5B_P_0): Likewise.
454 (VEX_W_0F5B_P_1): Likewise.
455 (VEX_W_0F5B_P_2): Likewise.
456 (VEX_W_0F5C_P_0): Likewise.
457 (VEX_W_0F5C_P_1): Likewise.
458 (VEX_W_0F5C_P_2): Likewise.
459 (VEX_W_0F5C_P_3): Likewise.
460 (VEX_W_0F5D_P_0): Likewise.
461 (VEX_W_0F5D_P_1): Likewise.
462 (VEX_W_0F5D_P_2): Likewise.
463 (VEX_W_0F5D_P_3): Likewise.
464 (VEX_W_0F5E_P_0): Likewise.
465 (VEX_W_0F5E_P_1): Likewise.
466 (VEX_W_0F5E_P_2): Likewise.
467 (VEX_W_0F5E_P_3): Likewise.
468 (VEX_W_0F5F_P_0): Likewise.
469 (VEX_W_0F5F_P_1): Likewise.
470 (VEX_W_0F5F_P_2): Likewise.
471 (VEX_W_0F5F_P_3): Likewise.
472 (VEX_W_0F60_P_2): Likewise.
473 (VEX_W_0F61_P_2): Likewise.
474 (VEX_W_0F62_P_2): Likewise.
475 (VEX_W_0F63_P_2): Likewise.
476 (VEX_W_0F64_P_2): Likewise.
477 (VEX_W_0F65_P_2): Likewise.
478 (VEX_W_0F66_P_2): Likewise.
479 (VEX_W_0F67_P_2): Likewise.
480 (VEX_W_0F68_P_2): Likewise.
481 (VEX_W_0F69_P_2): Likewise.
482 (VEX_W_0F6A_P_2): Likewise.
483 (VEX_W_0F6B_P_2): Likewise.
484 (VEX_W_0F6C_P_2): Likewise.
485 (VEX_W_0F6D_P_2): Likewise.
486 (VEX_W_0F6F_P_1): Likewise.
487 (VEX_W_0F6F_P_2): Likewise.
488 (VEX_W_0F70_P_1): Likewise.
489 (VEX_W_0F70_P_2): Likewise.
490 (VEX_W_0F70_P_3): Likewise.
491 (VEX_W_0F71_R_2_P_2): Likewise.
492 (VEX_W_0F71_R_4_P_2): Likewise.
493 (VEX_W_0F71_R_6_P_2): Likewise.
494 (VEX_W_0F72_R_2_P_2): Likewise.
495 (VEX_W_0F72_R_4_P_2): Likewise.
496 (VEX_W_0F72_R_6_P_2): Likewise.
497 (VEX_W_0F73_R_2_P_2): Likewise.
498 (VEX_W_0F73_R_3_P_2): Likewise.
499 (VEX_W_0F73_R_6_P_2): Likewise.
500 (VEX_W_0F73_R_7_P_2): Likewise.
501 (VEX_W_0F74_P_2): Likewise.
502 (VEX_W_0F75_P_2): Likewise.
503 (VEX_W_0F76_P_2): Likewise.
504 (VEX_W_0F77_P_0): Likewise.
505 (VEX_W_0F7C_P_2): Likewise.
506 (VEX_W_0F7C_P_3): Likewise.
507 (VEX_W_0F7D_P_2): Likewise.
508 (VEX_W_0F7D_P_3): Likewise.
509 (VEX_W_0F7E_P_1): Likewise.
510 (VEX_W_0F7F_P_1): Likewise.
511 (VEX_W_0F7F_P_2): Likewise.
512 (VEX_W_0FAE_R_2_M_0): Likewise.
513 (VEX_W_0FAE_R_3_M_0): Likewise.
514 (VEX_W_0FC2_P_0): Likewise.
515 (VEX_W_0FC2_P_1): Likewise.
516 (VEX_W_0FC2_P_2): Likewise.
517 (VEX_W_0FC2_P_3): Likewise.
518 (VEX_W_0FD0_P_2): Likewise.
519 (VEX_W_0FD0_P_3): Likewise.
520 (VEX_W_0FD1_P_2): Likewise.
521 (VEX_W_0FD2_P_2): Likewise.
522 (VEX_W_0FD3_P_2): Likewise.
523 (VEX_W_0FD4_P_2): Likewise.
524 (VEX_W_0FD5_P_2): Likewise.
525 (VEX_W_0FD6_P_2): Likewise.
526 (VEX_W_0FD7_P_2_M_1): Likewise.
527 (VEX_W_0FD8_P_2): Likewise.
528 (VEX_W_0FD9_P_2): Likewise.
529 (VEX_W_0FDA_P_2): Likewise.
530 (VEX_W_0FDB_P_2): Likewise.
531 (VEX_W_0FDC_P_2): Likewise.
532 (VEX_W_0FDD_P_2): Likewise.
533 (VEX_W_0FDE_P_2): Likewise.
534 (VEX_W_0FDF_P_2): Likewise.
535 (VEX_W_0FE0_P_2): Likewise.
536 (VEX_W_0FE1_P_2): Likewise.
537 (VEX_W_0FE2_P_2): Likewise.
538 (VEX_W_0FE3_P_2): Likewise.
539 (VEX_W_0FE4_P_2): Likewise.
540 (VEX_W_0FE5_P_2): Likewise.
541 (VEX_W_0FE6_P_1): Likewise.
542 (VEX_W_0FE6_P_2): Likewise.
543 (VEX_W_0FE6_P_3): Likewise.
544 (VEX_W_0FE7_P_2_M_0): Likewise.
545 (VEX_W_0FE8_P_2): Likewise.
546 (VEX_W_0FE9_P_2): Likewise.
547 (VEX_W_0FEA_P_2): Likewise.
548 (VEX_W_0FEB_P_2): Likewise.
549 (VEX_W_0FEC_P_2): Likewise.
550 (VEX_W_0FED_P_2): Likewise.
551 (VEX_W_0FEE_P_2): Likewise.
552 (VEX_W_0FEF_P_2): Likewise.
553 (VEX_W_0FF0_P_3_M_0): Likewise.
554 (VEX_W_0FF1_P_2): Likewise.
555 (VEX_W_0FF2_P_2): Likewise.
556 (VEX_W_0FF3_P_2): Likewise.
557 (VEX_W_0FF4_P_2): Likewise.
558 (VEX_W_0FF5_P_2): Likewise.
559 (VEX_W_0FF6_P_2): Likewise.
560 (VEX_W_0FF7_P_2): Likewise.
561 (VEX_W_0FF8_P_2): Likewise.
562 (VEX_W_0FF9_P_2): Likewise.
563 (VEX_W_0FFA_P_2): Likewise.
564 (VEX_W_0FFB_P_2): Likewise.
565 (VEX_W_0FFC_P_2): Likewise.
566 (VEX_W_0FFD_P_2): Likewise.
567 (VEX_W_0FFE_P_2): Likewise.
568 (VEX_W_0F3800_P_2): Likewise.
569 (VEX_W_0F3801_P_2): Likewise.
570 (VEX_W_0F3802_P_2): Likewise.
571 (VEX_W_0F3803_P_2): Likewise.
572 (VEX_W_0F3804_P_2): Likewise.
573 (VEX_W_0F3805_P_2): Likewise.
574 (VEX_W_0F3806_P_2): Likewise.
575 (VEX_W_0F3807_P_2): Likewise.
576 (VEX_W_0F3808_P_2): Likewise.
577 (VEX_W_0F3809_P_2): Likewise.
578 (VEX_W_0F380A_P_2): Likewise.
579 (VEX_W_0F380B_P_2): Likewise.
580 (VEX_W_0F3817_P_2): Likewise.
581 (VEX_W_0F381C_P_2): Likewise.
582 (VEX_W_0F381D_P_2): Likewise.
583 (VEX_W_0F381E_P_2): Likewise.
584 (VEX_W_0F3820_P_2): Likewise.
585 (VEX_W_0F3821_P_2): Likewise.
586 (VEX_W_0F3822_P_2): Likewise.
587 (VEX_W_0F3823_P_2): Likewise.
588 (VEX_W_0F3824_P_2): Likewise.
589 (VEX_W_0F3825_P_2): Likewise.
590 (VEX_W_0F3828_P_2): Likewise.
591 (VEX_W_0F3829_P_2): Likewise.
592 (VEX_W_0F382A_P_2_M_0): Likewise.
593 (VEX_W_0F382B_P_2): Likewise.
594 (VEX_W_0F3830_P_2): Likewise.
595 (VEX_W_0F3831_P_2): Likewise.
596 (VEX_W_0F3832_P_2): Likewise.
597 (VEX_W_0F3833_P_2): Likewise.
598 (VEX_W_0F3834_P_2): Likewise.
599 (VEX_W_0F3835_P_2): Likewise.
600 (VEX_W_0F3837_P_2): Likewise.
601 (VEX_W_0F3838_P_2): Likewise.
602 (VEX_W_0F3839_P_2): Likewise.
603 (VEX_W_0F383A_P_2): Likewise.
604 (VEX_W_0F383B_P_2): Likewise.
605 (VEX_W_0F383C_P_2): Likewise.
606 (VEX_W_0F383D_P_2): Likewise.
607 (VEX_W_0F383E_P_2): Likewise.
608 (VEX_W_0F383F_P_2): Likewise.
609 (VEX_W_0F3840_P_2): Likewise.
610 (VEX_W_0F3841_P_2): Likewise.
611 (VEX_W_0F38DB_P_2): Likewise.
612 (VEX_W_0F3A08_P_2): Likewise.
613 (VEX_W_0F3A09_P_2): Likewise.
614 (VEX_W_0F3A0A_P_2): Likewise.
615 (VEX_W_0F3A0B_P_2): Likewise.
616 (VEX_W_0F3A0C_P_2): Likewise.
617 (VEX_W_0F3A0D_P_2): Likewise.
618 (VEX_W_0F3A0E_P_2): Likewise.
619 (VEX_W_0F3A0F_P_2): Likewise.
620 (VEX_W_0F3A21_P_2): Likewise.
621 (VEX_W_0F3A40_P_2): Likewise.
622 (VEX_W_0F3A41_P_2): Likewise.
623 (VEX_W_0F3A42_P_2): Likewise.
624 (VEX_W_0F3A62_P_2): Likewise.
625 (VEX_W_0F3A63_P_2): Likewise.
626 (VEX_W_0F3ADF_P_2): Likewise.
627 (VEX_LEN_0F77_P_0): New.
628 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
629 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
630 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
631 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
632 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
633 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
634 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
635 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
636 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
637 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
638 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
639 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
640 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
641 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
642 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
643 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
644 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
645 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
646 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
647 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
648 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
649 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
650 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
651 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
652 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
653 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
654 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
655 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
656 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
657 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
658 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
659 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
660 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
661 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
662 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
663 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
664 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
665 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
666 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
667 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
668 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
669 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
670 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
671 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
672 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
673 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
674 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
675 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
676 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
677 (vex_table): Update VEX 0F28 and 0F29 entries.
678 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
679 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
680 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
681 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
682 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
683 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
684 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
685 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
686 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
687 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
688 VEX_LEN_0F3A0B_P_2 entries.
689 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
690 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
691 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
692 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
693 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
694 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
695 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
696 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
697 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
698 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
699 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
700 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
701 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
702 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
703 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
704 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
705 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
706 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
707 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
708 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
709 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
710 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
711 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
712 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
713 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
714 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
715 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
716 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
717 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
718 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
719 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
720 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
721 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
722 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
723 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
724 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
725 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
726 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
727 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
728 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
729 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
730 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
731 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
732 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
733 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
734 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
735 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
736 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
737 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
738 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
739 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
740 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
741 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
742 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
743 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
744 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
745 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
746 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
747 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
748 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
749 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
750 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
751 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
752 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
753 VEX_W_0F3ADF_P_2 entries.
754 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
755 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
756 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
757
6fa52824
L		 7582018-09-17 H.J. Lu <hongjiu.lu@intel.com>
759
760 * i386-opc.tbl (VexWIG): New.
761 Replace VexW=3 with VexWIG.
762
db4cc665
L		 7632018-09-15 H.J. Lu <hongjiu.lu@intel.com>
764
765 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
766 * i386-tbl.h: Regenerated.
767
3c374143
L		 7682018-09-15 H.J. Lu <hongjiu.lu@intel.com>
769
770 PR gas/23665
771 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
772 VEX_LEN_0FD6_P_2 entries.
773 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
774 * i386-tbl.h: Regenerated.
775
6865c043
L		 7762018-09-14 H.J. Lu <hongjiu.lu@intel.com>
777
778 PR gas/23642
779 * i386-opc.h (VEXWIG): New.
780 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
781 * i386-tbl.h: Regenerated.
782
70df6fc9
L		 7832018-09-14 H.J. Lu <hongjiu.lu@intel.com>
784
785 PR binutils/23655
786 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
787 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
788 * i386-dis.c (EXxEVexR64): New.
789 (evex_rounding_64_mode): Likewise.
790 (OP_Rounding): Handle evex_rounding_64_mode.
791
d20dee9e
L		 7922018-09-14 H.J. Lu <hongjiu.lu@intel.com>
793
794 PR binutils/23655
795 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
796 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
797 * i386-dis.c (Edqa): New.
798 (dqa_mode): Likewise.
799 (intel_operand_size): Handle dqa_mode as m_mode.
800 (OP_E_register): Handle dqa_mode as dq_mode.
801 (OP_E_memory): Set shift for dqa_mode based on address_mode.
802
5074ad8a
L		 8032018-09-14 H.J. Lu <hongjiu.lu@intel.com>
804
805 * i386-dis.c (OP_E_memory): Reformat.
806
556059dd
JB		 8072018-09-14 Jan Beulich <jbeulich@suse.com>
808
809 * i386-opc.tbl (crc32): Fold byte and word forms.
810 * i386-tbl.h: Re-generate.
811
41d1ab6a
L		 8122018-09-13 H.J. Lu <hongjiu.lu@intel.com>
813
814 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
815 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
816 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
817 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
818 * i386-tbl.h: Regenerated.
819
57f6375e
JB		 8202018-09-13 Jan Beulich <jbeulich@suse.com>
821
822 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
823 meaningless.
824 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
825 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
826 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
827 * i386-tbl.h: Re-generate.
828
2589a7e5
JB		 8292018-09-13 Jan Beulich <jbeulich@suse.com>
830
831 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
832 AVX512_4VNNIW insns.
833 * i386-tbl.h: Re-generate.
834
a760eb41
JB		 8352018-09-13 Jan Beulich <jbeulich@suse.com>
836
837 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
838 meaningless.
839 * i386-tbl.h: Re-generate.
840
e9042658
JB		 8412018-09-13 Jan Beulich <jbeulich@suse.com>
842
843 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
844 meaningless.
845 * i386-tbl.h: Re-generate.
846
9caa306f
JB		 8472018-09-13 Jan Beulich <jbeulich@suse.com>
848
849 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
850 meaningless.
851 * i386-tbl.h: Re-generate.
852
fb6ce599
JB		 8532018-09-13 Jan Beulich <jbeulich@suse.com>
854
855 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
856 meaningless.
857 * i386-tbl.h: Re-generate.
858
6a8da886
JB		 8592018-09-13 Jan Beulich <jbeulich@suse.com>
860
861 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
862 meaningless.
863 * i386-tbl.h: Re-generate.
864
c7f27919
JB		 8652018-09-13 Jan Beulich <jbeulich@suse.com>
866
867 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
868 * i386-tbl.h: Re-generate.
869
0f407ee9
JB		 8702018-09-13 Jan Beulich <jbeulich@suse.com>
871
872 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
873 * i386-tbl.h: Re-generate.
874
2fbbbee5
JB		 8752018-09-13 Jan Beulich <jbeulich@suse.com>
876
877 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
878 meaningless.
879 * i386-tbl.h: Re-generate.
880
2b02b9a2
JB		 8812018-09-13 Jan Beulich <jbeulich@suse.com>
882
883 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
884 meaningless.
885 * i386-tbl.h: Re-generate.
886
963c68aa
JB		 8872018-09-13 Jan Beulich <jbeulich@suse.com>
888
889 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
890 * i386-tbl.h: Re-generate.
891
64e025c3
JB		 8922018-09-13 Jan Beulich <jbeulich@suse.com>
893
894 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
895 * i386-tbl.h: Re-generate.
896
47603f88
JB		 8972018-09-13 Jan Beulich <jbeulich@suse.com>
898
899 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
900 * i386-tbl.h: Re-generate.
901
0001cfd0
JB		 9022018-09-13 Jan Beulich <jbeulich@suse.com>
903
904 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
905 meaningless.
906 * i386-tbl.h: Re-generate.
907
be4b452e
JB		 9082018-09-13 Jan Beulich <jbeulich@suse.com>
909
910 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
911 meaningless.
912 * i386-tbl.h: Re-generate.
913
d09a1394
JB		 9142018-09-13 Jan Beulich <jbeulich@suse.com>
915
916 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
917 meaningless.
918 * i386-tbl.h: Re-generate.
919
07599e13
JB		 9202018-09-13 Jan Beulich <jbeulich@suse.com>
921
922 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
923 * i386-tbl.h: Re-generate.
924
1ee3e487
JB		 9252018-09-13 Jan Beulich <jbeulich@suse.com>
926
927 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
928 * i386-tbl.h: Re-generate.
929
a5f580e5
JB		 9302018-09-13 Jan Beulich <jbeulich@suse.com>
931
932 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
933 * i386-tbl.h: Re-generate.
934
49d5d12d
JB		 9352018-09-13 Jan Beulich <jbeulich@suse.com>
936
937 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
938 (vpbroadcastw, rdpid): Drop NoRex64.
939 * i386-tbl.h: Re-generate.
940
f5eb1d70
JB		 9412018-09-13 Jan Beulich <jbeulich@suse.com>
942
943 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
944 store templates, adding D.
945 * i386-tbl.h: Re-generate.
946
dbbc8b7e
JB		 9472018-09-13 Jan Beulich <jbeulich@suse.com>
948
949 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
950 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
951 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
952 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
953 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
954 Fold load and store templates where possible, adding D. Drop
955 IgnoreSize where it was pointlessly present. Drop redundant
956 *word.
957 * i386-tbl.h: Re-generate.
958
d276ec69
JB		 9592018-09-13 Jan Beulich <jbeulich@suse.com>
960
961 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
962 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
963 (intel_operand_size): Handle v_bndmk_mode.
964 (OP_E_memory): Likewise. Produce (bad) when also riprel.
965
9da4dfd6
JD		 9662018-09-08 John Darrington <john@darrington.wattle.id.au>
967
968 * disassemble.c (ARCH_s12z): Define if ARCH_all.
969
be192bc2
JW		 9702018-08-31 Kito Cheng <kito@andestech.com>
971
972 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
973 compressed floating point instructions.
974
43135d3b
JW		 9752018-08-30 Kito Cheng <kito@andestech.com>
976
977 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
978 riscv_opcode.xlen_requirement.
979 * riscv-opc.c (riscv_opcodes): Update for struct change.
980
df28970f
MA		 9812018-08-29 Martin Aberg <maberg@gaisler.com>
982
983 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
984 psr (PWRPSR) instruction.
985
9108bc33
CX		 9862018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
987
988 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
989
bd782c07
CX		 9902018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
991
992 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
993
ac8cb70f
CX		 9942018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
995
996 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
997 loongson3a as an alias of gs464 for compatibility.
998 * mips-opc.c (mips_opcodes): Change Comments.
999
a693765e
CX		 10002018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1001
1002 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1003 option.
1004 (print_mips_disassembler_options): Document -M loongson-ext.
1005 * mips-opc.c (LEXT2): New macro.
1006 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1007
bdc6c06e
CX		 10082018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1009
1010 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1011 descriptors.
1012 (parse_mips_ase_option): Handle -M loongson-ext option.
1013 (print_mips_disassembler_options): Document -M loongson-ext.
1014 * mips-opc.c (IL3A): Delete.
1015 * mips-opc.c (LEXT): New macro.
1016 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1017 instructions.
1018
716c08de
CX		 10192018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1020
1021 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1022 descriptors.
1023 (parse_mips_ase_option): Handle -M loongson-cam option.
1024 (print_mips_disassembler_options): Document -M loongson-cam.
1025 * mips-opc.c (LCAM): New macro.
1026 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1027 instructions.
1028
9cf7e568
AM		 10292018-08-21 Alan Modra <amodra@gmail.com>
1030
1031 * ppc-dis.c (operand_value_powerpc): Init "invalid".
1032 (skip_optional_operands): Count optional operands, and update
1033 ppc_optional_operand_value call.
1034 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1035 (extract_vlensi): Likewise.
1036 (extract_fxm): Return default value for missing optional operand.
1037 (extract_ls, extract_raq, extract_tbr): Likewise.
1038 (insert_sxl, extract_sxl): New functions.
1039 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1040 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1041 flag and extra entry.
1042 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1043 extract_sxl.
1044
d203b41a 10452018-08-20 Alan Modra <amodra@gmail.com>
f4107842 1046
d203b41a 1047 * sh-opc.h (MASK): Simplify.
f4107842 1048
08a8fe2f 10492018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 1050
d203b41a
AM		 1051 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1052 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 1053 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 1054
08a8fe2f 10552018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 1056
1057 * s12z.h: Delete.
7ba3ba91 1058
1bc60e56
L		 10592018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1060
1061 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1062 address with the addr32 prefix and without base nor index
1063 registers.
1064
d871f3f4
L		 10652018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1066
1067 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1068 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1069 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1070 (cpu_flags): Add CpuCMOV and CpuFXSR.
1071 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1072 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1073 * i386-init.h: Regenerated.
1074 * i386-tbl.h: Likewise.
1075
b6523c37 10762018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1077
1078 * arc-regs.h: Update auxiliary registers.
1079
e968fc9b
JB		 10802018-08-06 Jan Beulich <jbeulich@suse.com>
1081
1082 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1083 (RegIP, RegIZ): Define.
1084 * i386-reg.tbl: Adjust comments.
1085 (rip): Use Qword instead of BaseIndex. Use RegIP.
1086 (eip): Use Dword instead of BaseIndex. Use RegIP.
1087 (riz): Add Qword. Use RegIZ.
1088 (eiz): Add Dword. Use RegIZ.
1089 * i386-tbl.h: Re-generate.
1090
dbf8be89
JB		 10912018-08-03 Jan Beulich <jbeulich@suse.com>
1092
1093 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1094 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1095 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1096 * i386-tbl.h: Re-generate.
1097
c48dadc9
JB		 10982018-08-03 Jan Beulich <jbeulich@suse.com>
1099
1100 * i386-gen.c (operand_types): Remove Mem field.
1101 * i386-opc.h (union i386_operand_type): Remove mem field.
1102 * i386-init.h, i386-tbl.h: Re-generate.
1103
cb86a42a
AM		 11042018-08-01 Alan Modra <amodra@gmail.com>
1105
1106 * po/POTFILES.in: Regenerate.
1107
07cc0450
NC		 11082018-07-31 Nick Clifton <nickc@redhat.com>
1109
1110 * po/sv.po: Updated Swedish translation.
1111
1424ad86
JB		 11122018-07-31 Jan Beulich <jbeulich@suse.com>
1113
1114 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1115 * i386-init.h, i386-tbl.h: Re-generate.
1116
ae2387fe
JB		 11172018-07-31 Jan Beulich <jbeulich@suse.com>
1118
1119 * i386-opc.h (ZEROING_MASKING) Rename to ...
1120 (DYNAMIC_MASKING): ... this. Adjust comment.
1121 * i386-opc.tbl (MaskingMorZ): Define.
1122 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1123 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1124 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1125 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1126 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1127 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1128 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1129 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1130 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1131
6ff00b5e
JB		 11322018-07-31 Jan Beulich <jbeulich@suse.com>
1133
1134 * i386-opc.tbl: Use element rather than vector size for AVX512*
1135 scatter/gather insns.
1136 * i386-tbl.h: Re-generate.
1137
e951d5ca
JB		 11382018-07-31 Jan Beulich <jbeulich@suse.com>
1139
1140 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1141 (cpu_flags): Drop CpuVREX.
1142 * i386-opc.h (CpuVREX): Delete.
1143 (union i386_cpu_flags): Remove cpuvrex.
1144 * i386-init.h, i386-tbl.h: Re-generate.
1145
eb41b248
JW		 11462018-07-30 Jim Wilson <jimw@sifive.com>
1147
1148 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1149 fields.
1150 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1151
b8891f8d
AJ		 11522018-07-30 Andrew Jenner <andrew@codesourcery.com>
1153
1154 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1155 * Makefile.in: Regenerated.
1156 * configure.ac: Add C-SKY.
1157 * configure: Regenerated.
1158 * csky-dis.c: New file.
1159 * csky-opc.h: New file.
1160 * disassemble.c (ARCH_csky): Define.
1161 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1162 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1163
16065af1
AM		 11642018-07-27 Alan Modra <amodra@gmail.com>
1165
1166 * ppc-opc.c (insert_sprbat): Correct function parameter and
1167 return type.
1168 (extract_sprbat): Likewise, variable too.
1169
fa758a70
AC		 11702018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1171 Alan Modra <amodra@gmail.com>
1172
1173 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1174 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1175 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1176 support disjointed BAT.
1177 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1178 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1179 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1180
4a1b91ea
L		 11812018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1182 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1183
1184 * i386-gen.c (adjust_broadcast_modifier): New function.
1185 (process_i386_opcode_modifier): Add an argument for operands.
1186 Adjust the Broadcast value based on operands.
1187 (output_i386_opcode): Pass operand_types to
1188 process_i386_opcode_modifier.
1189 (process_i386_opcodes): Pass NULL as operands to
1190 process_i386_opcode_modifier.
1191 * i386-opc.h (BYTE_BROADCAST): New.
1192 (WORD_BROADCAST): Likewise.
1193 (DWORD_BROADCAST): Likewise.
1194 (QWORD_BROADCAST): Likewise.
1195 (i386_opcode_modifier): Expand broadcast to 3 bits.
1196 * i386-tbl.h: Regenerated.
1197
67ce483b
AM		 11982018-07-24 Alan Modra <amodra@gmail.com>
1199
1200 PR 23430
1201 * or1k-desc.h: Regenerate.
1202
4174bfff
JB		 12032018-07-24 Jan Beulich <jbeulich@suse.com>
1204
1205 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1206 vcvtusi2ss, and vcvtusi2sd.
1207 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1208 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1209 * i386-tbl.h: Re-generate.
1210
04e65276
CZ		 12112018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1212
1213 * arc-opc.c (extract_w6): Fix extending the sign.
1214
47e6f81c
CZ		 12152018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1216
1217 * arc-tbl.h (vewt): Allow it for ARC EM family.
1218
bb71536f
AM		 12192018-07-23 Alan Modra <amodra@gmail.com>
1220
1221 PR 23419
1222 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1223 opcode variants for mtspr/mfspr encodings.
1224
8095d2f7
CX		 12252018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1226 Maciej W. Rozycki <macro@mips.com>
1227
1228 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1229 loongson3a descriptors.
1230 (parse_mips_ase_option): Handle -M loongson-mmi option.
1231 (print_mips_disassembler_options): Document -M loongson-mmi.
1232 * mips-opc.c (LMMI): New macro.
1233 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1234 instructions.
1235
5f32791e
JB		 12362018-07-19 Jan Beulich <jbeulich@suse.com>
1237
1238 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1239 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1240 IgnoreSize and [XYZ]MMword where applicable.
1241 * i386-tbl.h: Re-generate.
1242
625cbd7a
JB		 12432018-07-19 Jan Beulich <jbeulich@suse.com>
1244
1245 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1246 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1247 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1248 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1249 * i386-tbl.h: Re-generate.
1250
86b15c32
JB		 12512018-07-19 Jan Beulich <jbeulich@suse.com>
1252
1253 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1254 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1255 VPCLMULQDQ templates into their respective AVX512VL counterparts
1256 where possible, using Disp8ShiftVL and CheckRegSize instead of
1257 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1258 * i386-tbl.h: Re-generate.
1259
cf769ed5
JB		 12602018-07-19 Jan Beulich <jbeulich@suse.com>
1261
1262 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1263 AVX512VL counterparts where possible, using Disp8ShiftVL and
1264 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1265 IgnoreSize) as appropriate.
1266 * i386-tbl.h: Re-generate.
1267
8282b7ad
JB		 12682018-07-19 Jan Beulich <jbeulich@suse.com>
1269
1270 * i386-opc.tbl: Fold AVX512BW templates into their respective
1271 AVX512VL counterparts where possible, using Disp8ShiftVL and
1272 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1273 IgnoreSize) as appropriate.
1274 * i386-tbl.h: Re-generate.
1275
755908cc
JB		 12762018-07-19 Jan Beulich <jbeulich@suse.com>
1277
1278 * i386-opc.tbl: Fold AVX512CD templates into their respective
1279 AVX512VL counterparts where possible, using Disp8ShiftVL and
1280 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1281 IgnoreSize) as appropriate.
1282 * i386-tbl.h: Re-generate.
1283
7091c612
JB		 12842018-07-19 Jan Beulich <jbeulich@suse.com>
1285
1286 * i386-opc.h (DISP8_SHIFT_VL): New.
1287 * i386-opc.tbl (Disp8ShiftVL): Define.
1288 (various): Fold AVX512VL templates into their respective
1289 AVX512F counterparts where possible, using Disp8ShiftVL and
1290 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1291 IgnoreSize) as appropriate.
1292 * i386-tbl.h: Re-generate.
1293
c30be56e
JB		 12942018-07-19 Jan Beulich <jbeulich@suse.com>
1295
1296 * Makefile.am: Change dependencies and rule for
1297 $(srcdir)/i386-init.h.
1298 * Makefile.in: Re-generate.
1299 * i386-gen.c (process_i386_opcodes): New local variable
1300 "marker". Drop opening of input file. Recognize marker and line
1301 number directives.
1302 * i386-opc.tbl (OPCODE_I386_H): Define.
1303 (i386-opc.h): Include it.
1304 (None): Undefine.
1305
11a322db
L		 13062018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1307
1308 PR gas/23418
1309 * i386-opc.h (Byte): Update comments.
1310 (Word): Likewise.
1311 (Dword): Likewise.
1312 (Fword): Likewise.
1313 (Qword): Likewise.
1314 (Tbyte): Likewise.
1315 (Xmmword): Likewise.
1316 (Ymmword): Likewise.
1317 (Zmmword): Likewise.
1318 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1319 vcvttps2uqq.
1320 * i386-tbl.h: Regenerated.
1321
cde3679e
NC		 13222018-07-12 Sudakshina Das <sudi.das@arm.com>
1323
1324 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1325 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1326 * aarch64-asm-2.c: Regenerate.
1327 * aarch64-dis-2.c: Regenerate.
1328 * aarch64-opc-2.c: Regenerate.
1329
45a28947
TC		 13302018-07-12 Tamar Christina <tamar.christina@arm.com>
1331
1332 PR binutils/23192
1333 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1334 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1335 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1336 sqdmulh, sqrdmulh): Use Em16.
1337
c597cc3d
SD		 13382018-07-11 Sudakshina Das <sudi.das@arm.com>
1339
1340 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1341 csdb together with them.
1342 (thumb32_opcodes): Likewise.
1343
a79eaed6
JB		 13442018-07-11 Jan Beulich <jbeulich@suse.com>
1345
1346 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1347 requiring 32-bit registers as operands 2 and 3. Improve
1348 comments.
1349 (mwait, mwaitx): Fold templates. Improve comments.
1350 OPERAND_TYPE_INOUTPORTREG.
1351 * i386-tbl.h: Re-generate.
1352
2fb5be8d
JB		 13532018-07-11 Jan Beulich <jbeulich@suse.com>
1354
1355 * i386-gen.c (operand_type_init): Remove
1356 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1357 OPERAND_TYPE_INOUTPORTREG.
1358 * i386-init.h: Re-generate.
1359
7f5cad30
JB		 13602018-07-11 Jan Beulich <jbeulich@suse.com>
1361
1362 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1363 (wrssq, wrussq): Add Qword.
1364 * i386-tbl.h: Re-generate.
1365
f0a85b07
JB		 13662018-07-11 Jan Beulich <jbeulich@suse.com>
1367
1368 * i386-opc.h: Rename OTMax to OTNum.
1369 (OTNumOfUints): Adjust calculation.
1370 (OTUnused): Directly alias to OTNum.
1371
9dcb0ba4
MR		 13722018-07-09 Maciej W. Rozycki <macro@mips.com>
1373
1374 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1375 `reg_xys'.
1376 (lea_reg_xys): Likewise.
1377 (print_insn_loop_primitive): Rename `reg' local variable to
1378 `reg_dxy'.
1379
f311ba7e
TC		 13802018-07-06 Tamar Christina <tamar.christina@arm.com>
1381
1382 PR binutils/23242
1383 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1384
cba05feb
TC		 13852018-07-06 Tamar Christina <tamar.christina@arm.com>
1386
1387 PR binutils/23369
1388 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1389 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1390
471b9d15
MR		 13912018-07-02 Maciej W. Rozycki <macro@mips.com>
1392
1393 PR tdep/8282
1394 * mips-dis.c (mips_option_arg_t): New enumeration.
1395 (mips_options): New variable.
1396 (disassembler_options_mips): New function.
1397 (print_mips_disassembler_options): Reimplement in terms of
1398 `disassembler_options_mips'.
1399 * arm-dis.c (disassembler_options_arm): Adapt to using the
1400 `disasm_options_and_args_t' structure.
1401 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1402 * s390-dis.c (disassembler_options_s390): Likewise.
1403
c0c468d5
TP		 14042018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1405
1406 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1407 expected result.
1408 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1409 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1410 * testsuite/ld-arm/tls-longplt.d: Likewise.
1411
369c9167
TC		 14122018-06-29 Tamar Christina <tamar.christina@arm.com>
1413
1414 PR binutils/23192
1415 * aarch64-asm-2.c: Regenerate.
1416 * aarch64-dis-2.c: Likewise.
1417 * aarch64-opc-2.c: Likewise.
1418 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1419 * aarch64-opc.c (operand_general_constraint_met_p,
1420 aarch64_print_operand): Likewise.
1421 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1422 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1423 fmlal2, fmlsl2.
1424 (AARCH64_OPERANDS): Add Em2.
1425
30aa1306
NC		 14262018-06-26 Nick Clifton <nickc@redhat.com>
1427
1428 * po/uk.po: Updated Ukranian translation.
1429 * po/de.po: Updated German translation.
1430 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1431
eca4b721
NC		 14322018-06-26 Nick Clifton <nickc@redhat.com>
1433
1434 * nfp-dis.c: Fix spelling mistake.
1435
71300e2c
NC		 14362018-06-24 Nick Clifton <nickc@redhat.com>
1437
1438 * configure: Regenerate.
1439 * po/opcodes.pot: Regenerate.
1440
719d8288
NC		 14412018-06-24 Nick Clifton <nickc@redhat.com>
1442
1443 2.31 branch created.
1444
514cd3a0
TC		 14452018-06-19 Tamar Christina <tamar.christina@arm.com>
1446
1447 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1448 * aarch64-asm-2.c: Regenerate.
1449 * aarch64-dis-2.c: Likewise.
1450
385e4d0f
MR		 14512018-06-21 Maciej W. Rozycki <macro@mips.com>
1452
1453 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1454 `-M ginv' option description.
1455
160d1b3d
SH		 14562018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1457
1458 PR gas/23305
1459 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1460 la and lla.
1461
d0ac1c44
SM		 14622018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1463
1464 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1465 * configure.ac: Remove AC_PREREQ.
1466 * Makefile.in: Re-generate.
1467 * aclocal.m4: Re-generate.
1468 * configure: Re-generate.
1469
6f20c942
FS		 14702018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1471
1472 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1473 mips64r6 descriptors.
1474 (parse_mips_ase_option): Handle -Mginv option.
1475 (print_mips_disassembler_options): Document -Mginv.
1476 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1477 (GINV): New macro.
1478 (mips_opcodes): Define ginvi and ginvt.
1479
730c3174
SE		 14802018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1481 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1482
1483 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1484 * mips-opc.c (CRC, CRC64): New macros.
1485 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1486 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1487 crc32cd for CRC64.
1488
cb366992
EB		 14892018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1490
1491 PR 20319
1492 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1493 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1494
ce72cd46
AM		 14952018-06-06 Alan Modra <amodra@gmail.com>
1496
1497 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1498 setjmp. Move init for some other vars later too.
1499
4b8e28c7
MF		 15002018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1501
1502 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1503 (dis_private): Add new fields for property section tracking.
1504 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1505 (xtensa_instruction_fits): New functions.
1506 (fetch_data): Bump minimal fetch size to 4.
1507 (print_insn_xtensa): Make struct dis_private static.
1508 Load and prepare property table on section change.
1509 Don't disassemble literals. Don't disassemble instructions that
1510 cross property table boundaries.
1511
55e99962
L		 15122018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1513
1514 * configure: Regenerated.
1515
733bd0ab
JB		 15162018-06-01 Jan Beulich <jbeulich@suse.com>
1517
1518 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1519 * i386-tbl.h: Re-generate.
1520
dfd27d41
JB		 15212018-06-01 Jan Beulich <jbeulich@suse.com>
1522
1523 * i386-opc.tbl (sldt, str): Add NoRex64.
1524 * i386-tbl.h: Re-generate.
1525
64795710
JB		 15262018-06-01 Jan Beulich <jbeulich@suse.com>
1527
1528 * i386-opc.tbl (invpcid): Add Oword.
1529 * i386-tbl.h: Re-generate.
1530
030157d8
AM		 15312018-06-01 Alan Modra <amodra@gmail.com>
1532
1533 * sysdep.h (_bfd_error_handler): Don't declare.
1534 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1535 * rl78-decode.opc: Likewise.
1536 * msp430-decode.c: Regenerate.
1537 * rl78-decode.c: Regenerate.
1538
a9660a6f
AP		 15392018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1540
1541 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1542 * i386-init.h : Regenerated.
1543
277eb7f6
AM		 15442018-05-25 Alan Modra <amodra@gmail.com>
1545
1546 * Makefile.in: Regenerate.
1547 * po/POTFILES.in: Regenerate.
1548
98553ad3
PB		 15492018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1550
1551 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1552 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1553 (insert_bab, extract_bab, insert_btab, extract_btab,
1554 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1555 (BAT, BBA VBA RBS XB6S): Delete macros.
1556 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1557 (BB, BD, RBX, XC6): Update for new macros.
1558 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1559 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1560 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1561 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1562
7b4ae824
JD		 15632018-05-18 John Darrington <john@darrington.wattle.id.au>
1564
1565 * Makefile.am: Add support for s12z architecture.
1566 * configure.ac: Likewise.
1567 * disassemble.c: Likewise.
1568 * disassemble.h: Likewise.
1569 * Makefile.in: Regenerate.
1570 * configure: Regenerate.
1571 * s12z-dis.c: New file.
1572 * s12z.h: New file.
1573
29e0f0a1
AM		 15742018-05-18 Alan Modra <amodra@gmail.com>
1575
1576 * nfp-dis.c: Don't #include libbfd.h.
1577 (init_nfp3200_priv): Use bfd_get_section_contents.
1578 (nit_nfp6000_mecsr_sec): Likewise.
1579
809276d2
NC		 15802018-05-17 Nick Clifton <nickc@redhat.com>
1581
1582 * po/zh_CN.po: Updated simplified Chinese translation.
1583
ff329288
TC		 15842018-05-16 Tamar Christina <tamar.christina@arm.com>
1585
1586 PR binutils/23109
1587 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1588 * aarch64-dis-2.c: Regenerate.
1589
f9830ec1
TC		 15902018-05-15 Tamar Christina <tamar.christina@arm.com>
1591
1592 PR binutils/21446
1593 * aarch64-asm.c (opintl.h): Include.
1594 (aarch64_ins_sysreg): Enforce read/write constraints.
1595 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1596 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1597 (F_REG_READ, F_REG_WRITE): New.
1598 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1599 AARCH64_OPND_SYSREG.
1600 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1601 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1602 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1603 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1604 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1605 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1606 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1607 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1608 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1609 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1610 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1611 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1612 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1613 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1614 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1615 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1616 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1617
7d02540a
TC		 16182018-05-15 Tamar Christina <tamar.christina@arm.com>
1619
1620 PR binutils/21446
1621 * aarch64-dis.c (no_notes: New.
1622 (parse_aarch64_dis_option): Support notes.
1623 (aarch64_decode_insn, print_operands): Likewise.
1624 (print_aarch64_disassembler_options): Document notes.
1625 * aarch64-opc.c (aarch64_print_operand): Support notes.
1626
561a72d4
TC		 16272018-05-15 Tamar Christina <tamar.christina@arm.com>
1628
1629 PR binutils/21446
1630 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1631 and take error struct.
1632 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1633 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1634 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1635 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1636 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1637 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1638 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1639 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1640 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1641 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1642 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1643 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1644 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1645 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1646 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1647 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1648 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1649 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1650 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1651 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1652 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1653 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1654 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1655 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1656 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1657 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1658 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1659 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1660 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1661 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1662 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1663 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1664 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1665 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1666 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1667 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1668 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1669 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1670 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1671 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1672 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1673 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1674 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1675 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1676 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1677 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1678 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1679 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1680 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1681 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1682 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1683 (determine_disassembling_preference, aarch64_decode_insn,
1684 print_insn_aarch64_word, print_insn_data): Take errors struct.
1685 (print_insn_aarch64): Use errors.
1686 * aarch64-asm-2.c: Regenerate.
1687 * aarch64-dis-2.c: Regenerate.
1688 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1689 boolean in aarch64_insert_operan.
1690 (print_operand_extractor): Likewise.
1691 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1692
1678bd35
FT		 16932018-05-15 Francois H. Theron <francois.theron@netronome.com>
1694
1695 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1696
06cfb1c8
L		 16972018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1698
1699 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1700
84f9f8c3
AM		 17012018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1702
1703 * cr16-opc.c (cr16_instruction): Comment typo fix.
1704 * hppa-dis.c (print_insn_hppa): Likewise.
1705
e6f372ba
JW		 17062018-05-08 Jim Wilson <jimw@sifive.com>
1707
1708 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1709 (match_c_slli64, match_srxi_as_c_srxi): New.
1710 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1711 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1712 <c.slli, c.srli, c.srai>: Use match_s_slli.
1713 <c.slli64, c.srli64, c.srai64>: New.
1714
f413a913
AM		 17152018-05-08 Alan Modra <amodra@gmail.com>
1716
1717 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1718 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1719 partition opcode space for index lookup.
1720
a87a6478
PB		 17212018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1722
1723 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1724 <insn_length>: ...with this. Update usage.
1725 Remove duplicate call to *info->memory_error_func.
1726
c0a30a9f
L		 17272018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1728 H.J. Lu <hongjiu.lu@intel.com>
1729
1730 * i386-dis.c (Gva): New.
1731 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1732 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1733 (prefix_table): New instructions (see prefix above).
1734 (mod_table): New instructions (see prefix above).
1735 (OP_G): Handle va_mode.
1736 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1737 CPU_MOVDIR64B_FLAGS.
1738 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1739 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1740 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1741 * i386-opc.tbl: Add movidir{i,64b}.
1742 * i386-init.h: Regenerated.
1743 * i386-tbl.h: Likewise.
1744
75c0a438
L		 17452018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1746
1747 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1748 AddrPrefixOpReg.
1749 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1750 (AddrPrefixOpReg): This.
1751 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1752 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1753
2ceb7719
PB		 17542018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1755
1756 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1757 (vle_num_opcodes): Likewise.
1758 (spe2_num_opcodes): Likewise.
1759 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1760 initialization loop.
1761 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1762 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1763 only once.
1764
b3ac5c6c
TC		 17652018-05-01 Tamar Christina <tamar.christina@arm.com>
1766
1767 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1768
fe944acf
FT		 17692018-04-30 Francois H. Theron <francois.theron@netronome.com>
1770
1771 Makefile.am: Added nfp-dis.c.
1772 configure.ac: Added bfd_nfp_arch.
1773 disassemble.h: Added print_insn_nfp prototype.
1774 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1775 nfp-dis.c: New, for NFP support.
1776 po/POTFILES.in: Added nfp-dis.c to the list.
1777 Makefile.in: Regenerate.
1778 configure: Regenerate.
1779
e2195274
JB		 17802018-04-26 Jan Beulich <jbeulich@suse.com>
1781
1782 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1783 templates into their base ones.
1784 * i386-tlb.h: Re-generate.
1785
59ef5df4
JB		 17862018-04-26 Jan Beulich <jbeulich@suse.com>
1787
1788 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1789 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1790 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1791 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1792 * i386-init.h: Re-generate.
1793
6e041cf4
JB		 17942018-04-26 Jan Beulich <jbeulich@suse.com>
1795
1796 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1797 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1798 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1799 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1800 comment.
1801 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1802 and CpuRegMask.
1803 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1804 CpuRegMask: Delete.
1805 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1806 cpuregzmm, and cpuregmask.
1807 * i386-init.h: Re-generate.
1808 * i386-tbl.h: Re-generate.
1809
0e0eea78
JB		 18102018-04-26 Jan Beulich <jbeulich@suse.com>
1811
1812 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1813 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1814 * i386-init.h: Re-generate.
1815
2f1bada2
JB		 18162018-04-26 Jan Beulich <jbeulich@suse.com>
1817
1818 * i386-gen.c (VexImmExt): Delete.
1819 * i386-opc.h (VexImmExt, veximmext): Delete.
1820 * i386-opc.tbl: Drop all VexImmExt uses.
1821 * i386-tlb.h: Re-generate.
1822
bacd1457
JB		 18232018-04-25 Jan Beulich <jbeulich@suse.com>
1824
1825 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1826 register-only forms.
1827 * i386-tlb.h: Re-generate.
1828
10bba94b
TC		 18292018-04-25 Tamar Christina <tamar.christina@arm.com>
1830
1831 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1832
c48935d7
IT		 18332018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1834
1835 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1836 PREFIX_0F1C.
1837 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1838 (cpu_flags): Add CpuCLDEMOTE.
1839 * i386-init.h: Regenerate.
1840 * i386-opc.h (enum): Add CpuCLDEMOTE,
1841 (i386_cpu_flags): Add cpucldemote.
1842 * i386-opc.tbl: Add cldemote.
1843 * i386-tbl.h: Regenerate.
1844
211dc24b
AM		 18452018-04-16 Alan Modra <amodra@gmail.com>
1846
1847 * Makefile.am: Remove sh5 and sh64 support.
1848 * configure.ac: Likewise.
1849 * disassemble.c: Likewise.
1850 * disassemble.h: Likewise.
1851 * sh-dis.c: Likewise.
1852 * sh64-dis.c: Delete.
1853 * sh64-opc.c: Delete.
1854 * sh64-opc.h: Delete.
1855 * Makefile.in: Regenerate.
1856 * configure: Regenerate.
1857 * po/POTFILES.in: Regenerate.
1858
a9a4b302
AM		 18592018-04-16 Alan Modra <amodra@gmail.com>
1860
1861 * Makefile.am: Remove w65 support.
1862 * configure.ac: Likewise.
1863 * disassemble.c: Likewise.
1864 * disassemble.h: Likewise.
1865 * w65-dis.c: Delete.
1866 * w65-opc.h: Delete.
1867 * Makefile.in: Regenerate.
1868 * configure: Regenerate.
1869 * po/POTFILES.in: Regenerate.
1870
04cb01fd
AM		 18712018-04-16 Alan Modra <amodra@gmail.com>
1872
1873 * configure.ac: Remove we32k support.
1874 * configure: Regenerate.
1875
c2bf1eec
AM		 18762018-04-16 Alan Modra <amodra@gmail.com>
1877
1878 * Makefile.am: Remove m88k support.
1879 * configure.ac: Likewise.
1880 * disassemble.c: Likewise.
1881 * disassemble.h: Likewise.
1882 * m88k-dis.c: Delete.
1883 * Makefile.in: Regenerate.
1884 * configure: Regenerate.
1885 * po/POTFILES.in: Regenerate.
1886
6793974d
AM		 18872018-04-16 Alan Modra <amodra@gmail.com>
1888
1889 * Makefile.am: Remove i370 support.
1890 * configure.ac: Likewise.
1891 * disassemble.c: Likewise.
1892 * disassemble.h: Likewise.
1893 * i370-dis.c: Delete.
1894 * i370-opc.c: Delete.
1895 * Makefile.in: Regenerate.
1896 * configure: Regenerate.
1897 * po/POTFILES.in: Regenerate.
1898
e82aa794
AM		 18992018-04-16 Alan Modra <amodra@gmail.com>
1900
1901 * Makefile.am: Remove h8500 support.
1902 * configure.ac: Likewise.
1903 * disassemble.c: Likewise.
1904 * disassemble.h: Likewise.
1905 * h8500-dis.c: Delete.
1906 * h8500-opc.h: Delete.
1907 * Makefile.in: Regenerate.
1908 * configure: Regenerate.
1909 * po/POTFILES.in: Regenerate.
1910
fceadf09
AM		 19112018-04-16 Alan Modra <amodra@gmail.com>
1912
1913 * configure.ac: Remove tahoe support.
1914 * configure: Regenerate.
1915
ae1d3843
L		 19162018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1917
1918 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1919 umwait.
1920 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1921 64-bit mode.
1922 * i386-tbl.h: Regenerated.
1923
de89d0a3
IT		 19242018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1925
1926 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1927 PREFIX_MOD_1_0FAE_REG_6.
1928 (va_mode): New.
1929 (OP_E_register): Use va_mode.
1930 * i386-dis-evex.h (prefix_table):
1931 New instructions (see prefixes above).
1932 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1933 (cpu_flags): Likewise.
1934 * i386-opc.h (enum): Likewise.
1935 (i386_cpu_flags): Likewise.
1936 * i386-opc.tbl: Add umonitor, umwait, tpause.
1937 * i386-init.h: Regenerate.
1938 * i386-tbl.h: Likewise.
1939
a8eb42a8
AM		 19402018-04-11 Alan Modra <amodra@gmail.com>
1941
1942 * opcodes/i860-dis.c: Delete.
1943 * opcodes/i960-dis.c: Delete.
1944 * Makefile.am: Remove i860 and i960 support.
1945 * configure.ac: Likewise.
1946 * disassemble.c: Likewise.
1947 * disassemble.h: Likewise.
1948 * Makefile.in: Regenerate.
1949 * configure: Regenerate.
1950 * po/POTFILES.in: Regenerate.
1951
caf0678c
L		 19522018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1953
1954 PR binutils/23025
1955 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1956 to 0.
1957 (print_insn): Clear vex instead of vex.evex.
1958
4fb0d2b9
NC		 19592018-04-04 Nick Clifton <nickc@redhat.com>
1960
1961 * po/es.po: Updated Spanish translation.
1962
c39e5b26
JB		 19632018-03-28 Jan Beulich <jbeulich@suse.com>
1964
1965 * i386-gen.c (opcode_modifiers): Delete VecESize.
1966 * i386-opc.h (VecESize): Delete.
1967 (struct i386_opcode_modifier): Delete vecesize.
1968 * i386-opc.tbl: Drop VecESize.
1969 * i386-tlb.h: Re-generate.
1970
8e6e0792
JB		 19712018-03-28 Jan Beulich <jbeulich@suse.com>
1972
1973 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1974 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1975 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1976 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1977 * i386-tlb.h: Re-generate.
1978
9f123b91
JB		 19792018-03-28 Jan Beulich <jbeulich@suse.com>
1980
1981 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1982 Fold AVX512 forms
1983 * i386-tlb.h: Re-generate.
1984
9646c87b
JB		 19852018-03-28 Jan Beulich <jbeulich@suse.com>
1986
1987 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1988 (vex_len_table): Drop Y for vcvt*2si.
1989 (putop): Replace plain 'Y' handling by abort().
1990
c8d59609
NC		 19912018-03-28 Nick Clifton <nickc@redhat.com>
1992
1993 PR 22988
1994 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1995 instructions with only a base address register.
1996 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1997 handle AARHC64_OPND_SVE_ADDR_R.
1998 (aarch64_print_operand): Likewise.
1999 * aarch64-asm-2.c: Regenerate.
2000 * aarch64_dis-2.c: Regenerate.
2001 * aarch64-opc-2.c: Regenerate.
2002
b8c169f3
JB		 20032018-03-22 Jan Beulich <jbeulich@suse.com>
2004
2005 * i386-opc.tbl: Drop VecESize from register only insn forms and
2006 memory forms not allowing broadcast.
2007 * i386-tlb.h: Re-generate.
2008
96bc132a
JB		 20092018-03-22 Jan Beulich <jbeulich@suse.com>
2010
2011 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2012 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2013 sha256*): Drop Disp<N>.
2014
9f79e886
JB		 20152018-03-22 Jan Beulich <jbeulich@suse.com>
2016
2017 * i386-dis.c (EbndS, bnd_swap_mode): New.
2018 (prefix_table): Use EbndS.
2019 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2020 * i386-opc.tbl (bndmov): Move misplaced Load.
2021 * i386-tlb.h: Re-generate.
2022
d6793fa1
JB		 20232018-03-22 Jan Beulich <jbeulich@suse.com>
2024
2025 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2026 templates allowing memory operands and folded ones for register
2027 only flavors.
2028 * i386-tlb.h: Re-generate.
2029
f7768225
JB		 20302018-03-22 Jan Beulich <jbeulich@suse.com>
2031
2032 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2033 256-bit templates. Drop redundant leftover Disp<N>.
2034 * i386-tlb.h: Re-generate.
2035
0e35537d
JW		 20362018-03-14 Kito Cheng <kito.cheng@gmail.com>
2037
2038 * riscv-opc.c (riscv_insn_types): New.
2039
b4a3689a
NC		 20402018-03-13 Nick Clifton <nickc@redhat.com>
2041
2042 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2043
d3d50934
L		 20442018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2045
2046 * i386-opc.tbl: Add Optimize to clr.
2047 * i386-tbl.h: Regenerated.
2048
bd5dea88
L		 20492018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2050
2051 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2052 * i386-opc.h (OldGcc): Removed.
2053 (i386_opcode_modifier): Remove oldgcc.
2054 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2055 instructions for old (<= 2.8.1) versions of gcc.
2056 * i386-tbl.h: Regenerated.
2057
e771e7c9
JB		 20582018-03-08 Jan Beulich <jbeulich@suse.com>
2059
2060 * i386-opc.h (EVEXDYN): New.
2061 * i386-opc.tbl: Fold various AVX512VL templates.
2062 * i386-tlb.h: Re-generate.
2063
ed438a93
JB		 20642018-03-08 Jan Beulich <jbeulich@suse.com>
2065
2066 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2067 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2068 vpexpandd, vpexpandq): Fold AFX512VF templates.
2069 * i386-tlb.h: Re-generate.
2070
454172a9
JB		 20712018-03-08 Jan Beulich <jbeulich@suse.com>
2072
2073 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2074 Fold 128- and 256-bit VEX-encoded templates.
2075 * i386-tlb.h: Re-generate.
2076
36824150
JB		 20772018-03-08 Jan Beulich <jbeulich@suse.com>
2078
2079 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2080 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2081 vpexpandd, vpexpandq): Fold AVX512F templates.
2082 * i386-tlb.h: Re-generate.
2083
e7f5c0a9
JB		 20842018-03-08 Jan Beulich <jbeulich@suse.com>
2085
2086 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2087 64-bit templates. Drop Disp<N>.
2088 * i386-tlb.h: Re-generate.
2089
25a4277f
JB		 20902018-03-08 Jan Beulich <jbeulich@suse.com>
2091
2092 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2093 and 256-bit templates.
2094 * i386-tlb.h: Re-generate.
2095
d2224064
JB		 20962018-03-08 Jan Beulich <jbeulich@suse.com>
2097
2098 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2099 * i386-tlb.h: Re-generate.
2100
1b193f0b
JB		 21012018-03-08 Jan Beulich <jbeulich@suse.com>
2102
2103 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2104 Drop NoAVX.
2105 * i386-tlb.h: Re-generate.
2106
f2f6a710
JB		 21072018-03-08 Jan Beulich <jbeulich@suse.com>
2108
2109 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2110 * i386-tlb.h: Re-generate.
2111
38e314eb
JB		 21122018-03-08 Jan Beulich <jbeulich@suse.com>
2113
2114 * i386-gen.c (opcode_modifiers): Delete FloatD.
2115 * i386-opc.h (FloatD): Delete.
2116 (struct i386_opcode_modifier): Delete floatd.
2117 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2118 FloatD by D.
2119 * i386-tlb.h: Re-generate.
2120
d53e6b98
JB		 21212018-03-08 Jan Beulich <jbeulich@suse.com>
2122
2123 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2124
2907c2f5
JB		 21252018-03-08 Jan Beulich <jbeulich@suse.com>
2126
2127 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2128 * i386-tlb.h: Re-generate.
2129
73053c1f
JB		 21302018-03-08 Jan Beulich <jbeulich@suse.com>
2131
2132 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2133 forms.
2134 * i386-tlb.h: Re-generate.
2135
52fe4420
AM		 21362018-03-07 Alan Modra <amodra@gmail.com>
2137
2138 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2139 bfd_arch_rs6000.
2140 * disassemble.h (print_insn_rs6000): Delete.
2141 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2142 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2143 (print_insn_rs6000): Delete.
2144
a6743a54
AM		 21452018-03-03 Alan Modra <amodra@gmail.com>
2146
2147 * sysdep.h (opcodes_error_handler): Define.
2148 (_bfd_error_handler): Declare.
2149 * Makefile.am: Remove stray #.
2150 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2151 EDIT" comment.
2152 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2153 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2154 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2155 opcodes_error_handler to print errors. Standardize error messages.
2156 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2157 and include opintl.h.
2158 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2159 * i386-gen.c: Standardize error messages.
2160 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2161 * Makefile.in: Regenerate.
2162 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2163 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2164 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2165 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2166 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2167 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2168 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2169 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2170 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2171 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2172 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2173 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2174 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2175
8305403a
L		 21762018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2177
2178 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2179 vpsub[bwdq] instructions.
2180 * i386-tbl.h: Regenerated.
2181
e184813f
AM		 21822018-03-01 Alan Modra <amodra@gmail.com>
2183
2184 * configure.ac (ALL_LINGUAS): Sort.
2185 * configure: Regenerate.
2186
5b616bef
TP		 21872018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2188
2189 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2190 macro by assignements.
2191
b6f8c7c4
L		 21922018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2193
2194 PR gas/22871
2195 * i386-gen.c (opcode_modifiers): Add Optimize.
2196 * i386-opc.h (Optimize): New enum.
2197 (i386_opcode_modifier): Add optimize.
2198 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2199 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2200 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2201 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2202 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2203 vpxord and vpxorq.
2204 * i386-tbl.h: Regenerated.
2205
e95b887f
AM		 22062018-02-26 Alan Modra <amodra@gmail.com>
2207
2208 * crx-dis.c (getregliststring): Allocate a large enough buffer
2209 to silence false positive gcc8 warning.
2210
0bccfb29
JW		 22112018-02-22 Shea Levy <shea@shealevy.com>
2212
2213 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2214
6b6b6807
L		 22152018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2216
2217 * i386-opc.tbl: Add {rex},
2218 * i386-tbl.h: Regenerated.
2219
75f31665
MR		 22202018-02-20 Maciej W. Rozycki <macro@mips.com>
2221
2222 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2223 (mips16_opcodes): Replace `M' with `m' for "restore".
2224
e207bc53
TP		 22252018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2226
2227 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2228
87993319
MR		 22292018-02-13 Maciej W. Rozycki <macro@mips.com>
2230
2231 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2232 variable to `function_index'.
2233
68d20676
NC		 22342018-02-13 Nick Clifton <nickc@redhat.com>
2235
2236 PR 22823
2237 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2238 about truncation of printing.
2239
d2159fdc
HW		 22402018-02-12 Henry Wong <henry@stuffedcow.net>
2241
2242 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2243
f174ef9f
NC		 22442018-02-05 Nick Clifton <nickc@redhat.com>
2245
2246 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2247
be3a8dca
IT		 22482018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2249
2250 * i386-dis.c (enum): Add pconfig.
2251 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2252 (cpu_flags): Add CpuPCONFIG.
2253 * i386-opc.h (enum): Add CpuPCONFIG.
2254 (i386_cpu_flags): Add cpupconfig.
2255 * i386-opc.tbl: Add PCONFIG instruction.
2256 * i386-init.h: Regenerate.
2257 * i386-tbl.h: Likewise.
2258
3233d7d0
IT		 22592018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2260
2261 * i386-dis.c (enum): Add PREFIX_0F09.
2262 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2263 (cpu_flags): Add CpuWBNOINVD.
2264 * i386-opc.h (enum): Add CpuWBNOINVD.
2265 (i386_cpu_flags): Add cpuwbnoinvd.
2266 * i386-opc.tbl: Add WBNOINVD instruction.
2267 * i386-init.h: Regenerate.
2268 * i386-tbl.h: Likewise.
2269
e925c834
JW		 22702018-01-17 Jim Wilson <jimw@sifive.com>
2271
2272 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2273
d777820b
IT		 22742018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2275
2276 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2277 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2278 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2279 (cpu_flags): Add CpuIBT, CpuSHSTK.
2280 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2281 (i386_cpu_flags): Add cpuibt, cpushstk.
2282 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2283 * i386-init.h: Regenerate.
2284 * i386-tbl.h: Likewise.
2285
f6efed01
NC		 22862018-01-16 Nick Clifton <nickc@redhat.com>
2287
2288 * po/pt_BR.po: Updated Brazilian Portugese translation.
2289 * po/de.po: Updated German translation.
2290
2721d702
JW		 22912018-01-15 Jim Wilson <jimw@sifive.com>
2292
2293 * riscv-opc.c (match_c_nop): New.
2294 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2295
616dcb87
NC		 22962018-01-15 Nick Clifton <nickc@redhat.com>
2297
2298 * po/uk.po: Updated Ukranian translation.
2299
3957a496
NC		 23002018-01-13 Nick Clifton <nickc@redhat.com>
2301
2302 * po/opcodes.pot: Regenerated.
2303
769c7ea5
NC		 23042018-01-13 Nick Clifton <nickc@redhat.com>
2305
2306 * configure: Regenerate.
2307
faf766e3
NC		 23082018-01-13 Nick Clifton <nickc@redhat.com>
2309
2310 2.30 branch created.
2311
888a89da
IT		 23122018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2313
2314 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2315 * i386-tbl.h: Regenerate.
2316
cbda583a
JB		 23172018-01-10 Jan Beulich <jbeulich@suse.com>
2318
2319 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2320 * i386-tbl.h: Re-generate.
2321
c9e92278
JB		 23222018-01-10 Jan Beulich <jbeulich@suse.com>
2323
2324 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2325 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2326 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2327 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2328 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2329 Disp8MemShift of AVX512VL forms.
2330 * i386-tbl.h: Re-generate.
2331
35fd2b2b
JW		 23322018-01-09 Jim Wilson <jimw@sifive.com>
2333
2334 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2335 then the hi_addr value is zero.
2336
91d8b670
JG		 23372018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2338
2339 * arm-dis.c (arm_opcodes): Add csdb.
2340 (thumb32_opcodes): Add csdb.
2341
be2e7d95
JG		 23422018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2343
2344 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2345 * aarch64-asm-2.c: Regenerate.
2346 * aarch64-dis-2.c: Regenerate.
2347 * aarch64-opc-2.c: Regenerate.
2348
704a705d
L		 23492018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2350
2351 PR gas/22681
2352 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2353 Remove AVX512 vmovd with 64-bit operands.
2354 * i386-tbl.h: Regenerated.
2355
35eeb78f
JW		 23562018-01-05 Jim Wilson <jimw@sifive.com>
2357
2358 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2359 jalr.
2360
219d1afa
AM		 23612018-01-03 Alan Modra <amodra@gmail.com>
2362
2363 Update year range in copyright notice of all files.
2364
1508bbf5
JB		 23652018-01-02 Jan Beulich <jbeulich@suse.com>
2366
2367 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2368 and OPERAND_TYPE_REGZMM entries.
2369
1e563868 2370For older changes see ChangeLog-2017
3499769a 2371\f
1e563868 2372Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 2373
2374Copying and distribution of this file, with or without modification,
2375are permitted in any medium without royalty provided the copyright
2376notice and this notice are preserved.
2377
2378Local Variables:
2379mode: change-log
2380left-margin: 8
2381fill-column: 74
2382version-control: never
2383End:
GDB Binutils - Deliverables
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