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20c2a615
L		 12015-07-22 Alexander Fomin <alexander.fomin@intel.com>
2
3 PR binutils/18631
4 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
5 "EXEvexHalfBcstXmmq" for the second operand.
6 (EVEX_W_0F79_P_2): Likewise.
7 (EVEX_W_0F7A_P_2): Likewise.
8 (EVEX_W_0F7B_P_2): Likewise.
9
6f1c2142
AM		 102015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
11
12 * arm-dis.c (print_insn_coprocessor): Added support for quarter
13 float bitfield format.
14 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
15 quarter float bitfield format.
16
8a643cc3
L		 172015-07-14 H.J. Lu <hongjiu.lu@intel.com>
18
19 * configure: Regenerated.
20
ef5a96d5
AM		 212015-07-03 Alan Modra <amodra@gmail.com>
22
23 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
24 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
25 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
26
c8c8175b
SL		 272015-07-01 Sandra Loosemore <sandra@codesourcery.com>
28 Cesar Philippidis <cesar@codesourcery.com>
29
30 * nios2-dis.c (nios2_extract_opcode): New.
31 (nios2_disassembler_state): New.
32 (nios2_find_opcode_hash): Use mach parameter to select correct
33 disassembler state.
34 (nios2_print_insn_arg): Extend to support new R2 argument letters
35 and formats.
36 (print_insn_nios2): Check for 16-bit instruction at end of memory.
37 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
38 (NIOS2_NUM_OPCODES): Rename to...
39 (NIOS2_NUM_R1_OPCODES): This.
40 (nios2_r2_opcodes): New.
41 (NIOS2_NUM_R2_OPCODES): New.
42 (nios2_num_r2_opcodes): New.
43 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
44 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
45 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
46 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
47 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
48
9916071f
AP		 492015-06-30 Amit Pawar <Amit.Pawar@amd.com>
50
51 * i386-dis.c (OP_Mwaitx): New.
52 (rm_table): Add monitorx/mwaitx.
53 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
54 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
55 (operand_type_init): Add CpuMWAITX.
56 * i386-opc.h (CpuMWAITX): New.
57 (i386_cpu_flags): Add cpumwaitx.
58 * i386-opc.tbl: Add monitorx and mwaitx.
59 * i386-init.h: Regenerated.
60 * i386-tbl.h: Likewise.
61
7b934113
PB		 622015-06-22 Peter Bergner <bergner@vnet.ibm.com>
63
64 * ppc-opc.c (insert_ls): Test for invalid LS operands.
65 (insert_esync): New function.
66 (LS, WC): Use insert_ls.
67 (ESYNC): Use insert_esync.
68
bdc4de1b
NC		 692015-06-22 Nick Clifton <nickc@redhat.com>
70
71 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
72 requested region lies beyond it.
73 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
74 looking for 32-bit insns.
75 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
76 data.
77 * sh-dis.c (print_insn_sh): Likewise.
78 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
79 blocks of instructions.
80 * vax-dis.c (print_insn_vax): Check that the requested address
81 does not clash with the stop_vma.
82
11a0cf2e
PB		 832015-06-19 Peter Bergner <bergner@vnet.ibm.com>
84
85 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
86 * ppc-opc.c (FXM4): Add non-zero optional value.
87 (TBR): Likewise.
88 (SXL): Likewise.
89 (insert_fxm): Handle new default operand value.
90 (extract_fxm): Likewise.
91 (insert_tbr): Likewise.
92 (extract_tbr): Likewise.
93
bdfa8b95
MW		 942015-06-16 Matthew Wahab <matthew.wahab@arm.com>
95
96 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
97
24b4cf66
SN		 982015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
99
100 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
101
99a2c561
PB		 1022015-06-12 Peter Bergner <bergner@vnet.ibm.com>
103
104 * ppc-opc.c: Add comment accidentally removed by old commit.
105 (MTMSRD_L): Delete.
106
40f77f82
AM		 1072015-06-04 Peter Bergner <bergner@vnet.ibm.com>
108
109 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
110
13be46a2
NC		 1112015-06-04 Nick Clifton <nickc@redhat.com>
112
113 PR 18474
114 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
115
ddfded2f
MW		 1162015-06-02 Matthew Wahab <matthew.wahab@arm.com>
117
118 * arm-dis.c (arm_opcodes): Add "setpan".
119 (thumb_opcodes): Add "setpan".
120
1af1dd51
MW		 1212015-06-02 Matthew Wahab <matthew.wahab@arm.com>
122
123 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
124 macros.
125
9e1f0fa7
MW		 1262015-06-02 Matthew Wahab <matthew.wahab@arm.com>
127
128 * aarch64-tbl.h (aarch64_feature_rdma): New.
129 (RDMA): New.
130 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
131 * aarch64-asm-2.c: Regenerate.
132 * aarch64-dis-2.c: Regenerate.
133 * aarch64-opc-2.c: Regenerate.
134
290806fd
MW		 1352015-06-02 Matthew Wahab <matthew.wahab@arm.com>
136
137 * aarch64-tbl.h (aarch64_feature_lor): New.
138 (LOR): New.
139 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
140 "stllrb", "stllrh".
141 * aarch64-asm-2.c: Regenerate.
142 * aarch64-dis-2.c: Regenerate.
143 * aarch64-opc-2.c: Regenerate.
144
f21cce2c
MW		 1452015-06-01 Matthew Wahab <matthew.wahab@arm.com>
146
147 * aarch64-opc.c (F_ARCHEXT): New.
148 (aarch64_sys_regs): Add "pan".
149 (aarch64_sys_reg_supported_p): New.
150 (aarch64_pstatefields): Add "pan".
151 (aarch64_pstatefield_supported_p): New.
152
d194d186
JB		 1532015-06-01 Jan Beulich <jbeulich@suse.com>
154
155 * i386-tbl.h: Regenerate.
156
3a8547d2
JB		 1572015-06-01 Jan Beulich <jbeulich@suse.com>
158
159 * i386-dis.c (print_insn): Swap rounding mode specifier and
160 general purpose register in Intel mode.
161
015c54d5
JB		 1622015-06-01 Jan Beulich <jbeulich@suse.com>
163
164 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
165 * i386-tbl.h: Regenerate.
166
071f0063
L		 1672015-05-18 H.J. Lu <hongjiu.lu@intel.com>
168
169 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
170 * i386-init.h: Regenerated.
171
5db04b09
L		 1722015-05-15 H.J. Lu <hongjiu.lu@intel.com>
173
174 PR binutis/18386
175 * i386-dis.c: Add comments for '@'.
176 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
177 (enum x86_64_isa): New.
178 (isa64): Likewise.
179 (print_i386_disassembler_options): Add amd64 and intel64.
180 (print_insn): Handle amd64 and intel64.
181 (putop): Handle '@'.
182 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
183 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
184 * i386-opc.h (AMD64): New.
185 (CpuIntel64): Likewise.
186 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
187 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
188 Mark direct call/jmp without Disp16|Disp32 as Intel64.
189 * i386-init.h: Regenerated.
190 * i386-tbl.h: Likewise.
191
4bc0608a
PB		 1922015-05-14 Peter Bergner <bergner@vnet.ibm.com>
193
194 * ppc-opc.c (IH) New define.
195 (powerpc_opcodes) <wait>: Do not enable for POWER7.
196 <tlbie>: Add RS operand for POWER7.
197 <slbia>: Add IH operand for POWER6.
198
70cead07
L		 1992015-05-11 H.J. Lu <hongjiu.lu@intel.com>
200
201 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
202 direct branch.
203 (jmp): Likewise.
204 * i386-tbl.h: Regenerated.
205
7b6d09fb
L		 2062015-05-11 H.J. Lu <hongjiu.lu@intel.com>
207
208 * configure.ac: Support bfd_iamcu_arch.
209 * disassemble.c (disassembler): Support bfd_iamcu_arch.
210 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
211 CPU_IAMCU_COMPAT_FLAGS.
212 (cpu_flags): Add CpuIAMCU.
213 * i386-opc.h (CpuIAMCU): New.
214 (i386_cpu_flags): Add cpuiamcu.
215 * configure: Regenerated.
216 * i386-init.h: Likewise.
217 * i386-tbl.h: Likewise.
218
31955f99
L		 2192015-05-08 H.J. Lu <hongjiu.lu@intel.com>
220
221 PR binutis/18386
222 * i386-dis.c (X86_64_E8): New.
223 (X86_64_E9): Likewise.
224 Update comments on 'T', 'U', 'V'. Add comments for '^'.
225 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
226 (x86_64_table): Add X86_64_E8 and X86_64_E9.
227 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
228 (putop): Handle '^'.
229 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
230 REX_W.
231
0952813b
DD		 2322015-04-30 DJ Delorie <dj@redhat.com>
233
234 * disassemble.c (disassembler): Choose suitable disassembler based
235 on E_ABI.
236 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
237 it to decode mul/div insns.
238 * rl78-decode.c: Regenerate.
239 * rl78-dis.c (print_insn_rl78): Rename to...
240 (print_insn_rl78_common): ...this, take ISA parameter.
241 (print_insn_rl78): New.
242 (print_insn_rl78_g10): New.
243 (print_insn_rl78_g13): New.
244 (print_insn_rl78_g14): New.
245 (rl78_get_disassembler): New.
246
f9d3ecaa
NC		 2472015-04-29 Nick Clifton <nickc@redhat.com>
248
249 * po/fr.po: Updated French translation.
250
4fff86c5
PB		 2512015-04-27 Peter Bergner <bergner@vnet.ibm.com>
252
253 * ppc-opc.c (DCBT_EO): New define.
254 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
255 <lharx>: Likewise.
256 <stbcx.>: Likewise.
257 <sthcx.>: Likewise.
258 <waitrsv>: Do not enable for POWER7 and later.
259 <waitimpl>: Likewise.
260 <dcbt>: Default to the two operand form of the instruction for all
261 "old" cpus. For "new" cpus, use the operand ordering that matches
262 whether the cpu is server or embedded.
263 <dcbtst>: Likewise.
264
3b78cfe1
AK		 2652015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
266
267 * s390-opc.c: New instruction type VV0UU2.
268 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
269 and WFC.
270
04d824a4
JB		 2712015-04-23 Jan Beulich <jbeulich@suse.com>
272
273 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
274 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
275 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
276 (vfpclasspd, vfpclassps): Add %XZ.
277
09708981
L		 2782015-04-15 H.J. Lu <hongjiu.lu@intel.com>
279
280 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
281 (PREFIX_UD_REPZ): Likewise.
282 (PREFIX_UD_REPNZ): Likewise.
283 (PREFIX_UD_DATA): Likewise.
284 (PREFIX_UD_ADDR): Likewise.
285 (PREFIX_UD_LOCK): Likewise.
286
3888916d
L		 2872015-04-15 H.J. Lu <hongjiu.lu@intel.com>
288
289 * i386-dis.c (prefix_requirement): Removed.
290 (print_insn): Don't set prefix_requirement. Check
291 dp->prefix_requirement instead of prefix_requirement.
292
f24bcbaa
L		 2932015-04-15 H.J. Lu <hongjiu.lu@intel.com>
294
295 PR binutils/17898
296 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
297 (PREFIX_MOD_0_0FC7_REG_6): This.
298 (PREFIX_MOD_3_0FC7_REG_6): New.
299 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
300 (prefix_table): Replace PREFIX_0FC7_REG_6 with
301 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
302 PREFIX_MOD_3_0FC7_REG_7.
303 (mod_table): Replace PREFIX_0FC7_REG_6 with
304 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
305 PREFIX_MOD_3_0FC7_REG_7.
306
507bd325
L		 3072015-04-15 H.J. Lu <hongjiu.lu@intel.com>
308
309 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
310 (PREFIX_MANDATORY_REPNZ): Likewise.
311 (PREFIX_MANDATORY_DATA): Likewise.
312 (PREFIX_MANDATORY_ADDR): Likewise.
313 (PREFIX_MANDATORY_LOCK): Likewise.
314 (PREFIX_MANDATORY): Likewise.
315 (PREFIX_UD_SHIFT): Set to 8
316 (PREFIX_UD_REPZ): Updated.
317 (PREFIX_UD_REPNZ): Likewise.
318 (PREFIX_UD_DATA): Likewise.
319 (PREFIX_UD_ADDR): Likewise.
320 (PREFIX_UD_LOCK): Likewise.
321 (PREFIX_IGNORED_SHIFT): New.
322 (PREFIX_IGNORED_REPZ): Likewise.
323 (PREFIX_IGNORED_REPNZ): Likewise.
324 (PREFIX_IGNORED_DATA): Likewise.
325 (PREFIX_IGNORED_ADDR): Likewise.
326 (PREFIX_IGNORED_LOCK): Likewise.
327 (PREFIX_OPCODE): Likewise.
328 (PREFIX_IGNORED): Likewise.
329 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
330 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
331 (three_byte_table): Likewise.
332 (mod_table): Likewise.
333 (mandatory_prefix): Renamed to ...
334 (prefix_requirement): This.
335 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
336 Update PREFIX_90 entry.
337 (get_valid_dis386): Check prefix_requirement to see if a prefix
338 should be ignored.
339 (print_insn): Replace mandatory_prefix with prefix_requirement.
340
f0fba320
RL		 3412015-04-15 Renlin Li <renlin.li@arm.com>
342
343 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
344 use it for ssat and ssat16.
345 (print_insn_thumb32): Add handle case for 'D' control code.
346
bf890a93
IT		 3472015-04-06 Ilya Tocar <ilya.tocar@intel.com>
348 H.J. Lu <hongjiu.lu@intel.com>
349
350 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
351 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
352 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
353 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
354 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
355 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
356 Fill prefix_requirement field.
357 (struct dis386): Add prefix_requirement field.
358 (dis386): Fill prefix_requirement field.
359 (dis386_twobyte): Ditto.
360 (twobyte_has_mandatory_prefix_: Remove.
361 (reg_table): Fill prefix_requirement field.
362 (prefix_table): Ditto.
363 (x86_64_table): Ditto.
364 (three_byte_table): Ditto.
365 (xop_table): Ditto.
366 (vex_table): Ditto.
367 (vex_len_table): Ditto.
368 (vex_w_table): Ditto.
369 (mod_table): Ditto.
370 (bad_opcode): Ditto.
371 (print_insn): Use prefix_requirement.
372 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
373 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
374 (float_reg): Ditto.
375
2f783c1f
MF		 3762015-03-30 Mike Frysinger <vapier@gentoo.org>
377
378 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
379
b9d94d62
L		 3802015-03-29 H.J. Lu <hongjiu.lu@intel.com>
381
382 * Makefile.in: Regenerated.
383
27c49e9a
AB		 3842015-03-25 Anton Blanchard <anton@samba.org>
385
386 * ppc-dis.c (disassemble_init_powerpc): Only initialise
387 powerpc_opcd_indices and vle_opcd_indices once.
388
c4e676f1
AB		 3892015-03-25 Anton Blanchard <anton@samba.org>
390
391 * ppc-opc.c (powerpc_opcodes): Add slbfee.
392
823d2571
TG		 3932015-03-24 Terry Guo <terry.guo@arm.com>
394
395 * arm-dis.c (opcode32): Updated to use new arm feature struct.
396 (opcode16): Likewise.
397 (coprocessor_opcodes): Replace bit with feature struct.
398 (neon_opcodes): Likewise.
399 (arm_opcodes): Likewise.
400 (thumb_opcodes): Likewise.
401 (thumb32_opcodes): Likewise.
402 (print_insn_coprocessor): Likewise.
403 (print_insn_arm): Likewise.
404 (select_arm_features): Follow new feature struct.
405
029f3522
GG		 4062015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
407
408 * i386-dis.c (rm_table): Add clzero.
409 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
410 Add CPU_CLZERO_FLAGS.
411 (cpu_flags): Add CpuCLZERO.
412 * i386-opc.h: Add CpuCLZERO.
413 * i386-opc.tbl: Add clzero.
414 * i386-init.h: Re-generated.
415 * i386-tbl.h: Re-generated.
416
6914869a
AB		 4172015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
418
419 * mips-opc.c (decode_mips_operand): Fix constraint issues
420 with u and y operands.
421
21e20815
AB		 4222015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
423
424 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
425
6b1d7593
AK		 4262015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
427
428 * s390-opc.c: Add new IBM z13 instructions.
429 * s390-opc.txt: Likewise.
430
c8f89a34
JW		 4312015-03-10 Renlin Li <renlin.li@arm.com>
432
433 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
434 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
435 related alias.
436 * aarch64-asm-2.c: Regenerate.
437 * aarch64-dis-2.c: Likewise.
438 * aarch64-opc-2.c: Likewise.
439
d8282f0e
JW		 4402015-03-03 Jiong Wang <jiong.wang@arm.com>
441
442 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
443
ac994365
OE		 4442015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
445
446 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
447 arch_sh_up.
448 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
449 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
450
fd63f640
V		 4512015-02-23 Vinay <Vinay.G@kpit.com>
452
453 * rl78-decode.opc (MOV): Added space between two operands for
454 'mov' instruction in index addressing mode.
455 * rl78-decode.c: Regenerate.
456
f63c1776
PA		 4572015-02-19 Pedro Alves <palves@redhat.com>
458
459 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
460
07774fcc
PA		 4612015-02-10 Pedro Alves <palves@redhat.com>
462 Tom Tromey <tromey@redhat.com>
463
464 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
465 microblaze_and, microblaze_xor.
466 * microblaze-opc.h (opcodes): Adjust.
467
3f8107ab
AM		 4682015-01-28 James Bowman <james.bowman@ftdichip.com>
469
470 * Makefile.am: Add FT32 files.
471 * configure.ac: Handle FT32.
472 * disassemble.c (disassembler): Call print_insn_ft32.
473 * ft32-dis.c: New file.
474 * ft32-opc.c: New file.
475 * Makefile.in: Regenerate.
476 * configure: Regenerate.
477 * po/POTFILES.in: Regenerate.
478
e5fe4957
KLC		 4792015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
480
481 * nds32-asm.c (keyword_sr): Add new system registers.
482
1e2e8c52
AK		 4832015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
484
485 * s390-dis.c (s390_extract_operand): Support vector register
486 operands.
487 (s390_print_insn_with_opcode): Support new operands types and add
488 new handling of optional operands.
489 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
490 and include opcode/s390.h instead.
491 (struct op_struct): New field `flags'.
492 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
493 (dumpTable): Dump flags.
494 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
495 string.
496 * s390-opc.c: Add new operands types, instruction formats, and
497 instruction masks.
498 (s390_opformats): Add new formats for .insn.
499 * s390-opc.txt: Add new instructions.
500
b90efa5b 5012015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 502
b90efa5b 503 Update year range in copyright notice of all files.
bffb6004 504
b90efa5b 505For older changes see ChangeLog-2014
252b5132 506\f
b90efa5b 507Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 508
509Copying and distribution of this file, with or without modification,
510are permitted in any medium without royalty provided the copyright
511notice and this notice are preserved.
512
252b5132 513Local Variables:
2f6d2f85
NC		 514mode: change-log
515left-margin: 8
516fill-column: 74
252b5132
RH		 517version-control: never
518End:
GDB Binutils - Deliverables
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