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PR 6585
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c8187e15
PB		 12008-06-25 Peter Bergner <bergner@vnet.ibm.com>
2
3 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
4 (print_ppc_disassembler_options): Likewise.
5 * ppc-opc.c (PPC464): Define.
6 (powerpc_opcodes): Add mfdcrux and mtdcrux.
7
7a283e07
RW		 82008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
9
10 * configure: Regenerate.
11
fa452fa6
PB		 122008-06-13 Peter Bergner <bergner@vnet.ibm.com>
13
14 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
15 ppc_cpu_t typedef.
16 (struct dis_private): New.
17 (POWERPC_DIALECT): New define.
18 (powerpc_dialect): Renamed to...
19 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
20 struct dis_private.
21 (print_insn_big_powerpc): Update for using structure in
22 info->private_data.
23 (print_insn_little_powerpc): Likewise.
24 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
25 (skip_optional_operands): Likewise.
26 (print_insn_powerpc): Likewise. Remove initialization of dialect.
27 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
28 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
29 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
30 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
31 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
32 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
33 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
34 param to be of type ppc_cpu_t. Update prototype.
35
bb35fb24
NC		 362008-06-12 Adam Nemet <anemet@caviumnetworks.com>
37
38 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
39 +s, +S.
40 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
41 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
42 syncw, syncws, vm3mulu, vm0 and vmulu.
43
dd3cbb7e
NC		 44 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
45 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
46 seqi, sne and snei.
47
a5dabbb0
L		 482008-05-30 H.J. Lu <hongjiu.lu@intel.com>
49
50 * i386-opc.tbl: Add vmovd with 64bit operand.
51 * i386-tbl.h: Regenerated.
52
725a9891
MS		 532008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
54
55 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
56
cbc80391
L		 572008-05-22 H.J. Lu <hongjiu.lu@intel.com>
58
59 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
60 * i386-tbl.h: Regenerated.
61
116615c5
L		 622008-05-22 H.J. Lu <hongjiu.lu@intel.com>
63
64 PR gas/6517
65 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
66 into 32bit and 64bit. Remove Reg64|Qword and add
67 IgnoreSize|No_qSuf on 32bit version.
68 * i386-tbl.h: Regenerated.
69
d9479f2d
L		 702008-05-21 H.J. Lu <hongjiu.lu@intel.com>
71
72 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
73 * i386-tbl.h: Regenerated.
74
3ce6fddb
NC		 752008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
76
77 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
78
8944f3c2
AM		 792008-05-14 Alan Modra <amodra@bigpond.net.au>
80
81 * Makefile.am: Run "make dep-am".
82 * Makefile.in: Regenerate.
83
f1f8f695
L		 842008-05-02 H.J. Lu <hongjiu.lu@intel.com>
85
86 * i386-dis.c (MOVBE_Fixup): New.
87 (Mo): Likewise.
88 (PREFIX_0F3880): Likewise.
89 (PREFIX_0F3881): Likewise.
90 (PREFIX_0F38F0): Updated.
91 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
92 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
93 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
94
95 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
96 CPU_EPT_FLAGS.
97 (cpu_flags): Add CpuMovbe and CpuEPT.
98
99 * i386-opc.h (CpuMovbe): New.
100 (CpuEPT): Likewise.
101 (CpuLM): Updated.
102 (i386_cpu_flags): Add cpumovbe and cpuept.
103
104 * i386-opc.tbl: Add entries for movbe and EPT instructions.
105 * i386-init.h: Regenerated.
106 * i386-tbl.h: Likewise.
107
89aa3097
AN		 1082008-04-29 Adam Nemet <anemet@caviumnetworks.com>
109
110 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
111 the two drem and the two dremu macros.
112
39c5c168
AN		 1132008-04-28 Adam Nemet <anemet@caviumnetworks.com>
114
115 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
116 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
117 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
118 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
119
f04d18b7
DM		 1202008-04-25 David S. Miller <davem@davemloft.net>
121
122 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
123 instead of %sys_tick_cmpr, as suggested in architecture manuals.
124
6194aaab
L		 1252008-04-23 Paolo Bonzini <bonzini@gnu.org>
126
127 * aclocal.m4: Regenerate.
128 * configure: Regenerate.
129
1a6b486f
DM		 1302008-04-23 David S. Miller <davem@davemloft.net>
131
132 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
133 extended values.
134 (prefetch_table): Add missing values.
135
81f8a913
L		 1362008-04-22 H.J. Lu <hongjiu.lu@intel.com>
137
138 * i386-gen.c (opcode_modifiers): Add NoAVX.
139
140 * i386-opc.h (NoAVX): New.
141 (OldGcc): Updated.
142 (i386_opcode_modifier): Add noavx.
143
144 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
145 instructions which don't have AVX equivalent.
146 * i386-tbl.h: Regenerated.
147
dae39acc
L		 1482008-04-18 H.J. Lu <hongjiu.lu@intel.com>
149
150 * i386-dis.c (OP_VEX_FMA): New.
151 (OP_EX_VexImmW): Likewise.
152 (VexFMA): Likewise.
153 (Vex128FMA): Likewise.
154 (EXVexImmW): Likewise.
155 (get_vex_imm8): Likewise.
156 (OP_EX_VexReg): Likewise.
157 (vex_i4_done): Renamed to ...
158 (vex_w_done): This.
159 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
160 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
161 FMA instructions.
162 (print_insn): Updated.
163 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
164 (OP_REG_VexI4): Check invalid high registers.
165
ce886ab1
DR		 1662008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
167 Michael Meissner <michael.meissner@amd.com>
168
169 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
170 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 171
19a6653c
AM		 1722008-04-14 Edmar Wienskoski <edmar@freescale.com>
173
174 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
175 accept Power E500MC instructions.
176 (print_ppc_disassembler_options): Document -Me500mc.
177 * ppc-opc.c (DUIS, DUI, T): New.
178 (XRT, XRTRA): Likewise.
179 (E500MC): Likewise.
180 (powerpc_opcodes): Add new Power E500MC instructions.
181
112b7c50
AK		 1822008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
183
184 * s390-dis.c (init_disasm): Evaluate disassembler_options.
185 (print_s390_disassembler_options): New function.
186 * disassemble.c (disassembler_usage): Invoke
187 print_s390_disassembler_options.
188
7ff42648
AK		 1892008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
190
191 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
192 of local variables used for mnemonic parsing: prefix, suffix and
193 number.
194
45a5551e
AK		 1952008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
196
197 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
198 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
199 (s390_crb_extensions): New extensions table.
200 (insertExpandedMnemonic): Handle '$' tag.
201 * s390-opc.txt: Remove conditional jump variants which can now
202 be expanded automatically.
203 Replace '*' tag with '$' in the compare and branch instructions.
204
06c8514a
L		 2052008-04-07 H.J. Lu <hongjiu.lu@intel.com>
206
207 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
208 (PREFIX_VEX_3AXX): Likewis.
209
b122c285
L		 2102008-04-07 H.J. Lu <hongjiu.lu@intel.com>
211
212 * i386-opc.tbl: Remove 4 extra blank lines.
213
594ab6a3
L		 2142008-04-04 H.J. Lu <hongjiu.lu@intel.com>
215
216 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
217 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
218 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
219 * i386-opc.tbl: Likewise.
220
221 * i386-opc.h (CpuCLMUL): Renamed to ...
222 (CpuPCLMUL): This.
223 (CpuFMA): Updated.
224 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
225
226 * i386-init.h: Regenerated.
227
c0f3af97
L		 2282008-04-03 H.J. Lu <hongjiu.lu@intel.com>
229
230 * i386-dis.c (OP_E_register): New.
231 (OP_E_memory): Likewise.
232 (OP_VEX): Likewise.
233 (OP_EX_Vex): Likewise.
234 (OP_EX_VexW): Likewise.
235 (OP_XMM_Vex): Likewise.
236 (OP_XMM_VexW): Likewise.
237 (OP_REG_VexI4): Likewise.
238 (PCLMUL_Fixup): Likewise.
239 (VEXI4_Fixup): Likewise.
240 (VZERO_Fixup): Likewise.
241 (VCMP_Fixup): Likewise.
242 (VPERMIL2_Fixup): Likewise.
243 (rex_original): Likewise.
244 (rex_ignored): Likewise.
245 (Mxmm): Likewise.
246 (XMM): Likewise.
247 (EXxmm): Likewise.
248 (EXxmmq): Likewise.
249 (EXymmq): Likewise.
250 (Vex): Likewise.
251 (Vex128): Likewise.
252 (Vex256): Likewise.
253 (VexI4): Likewise.
254 (EXdVex): Likewise.
255 (EXqVex): Likewise.
256 (EXVexW): Likewise.
257 (EXdVexW): Likewise.
258 (EXqVexW): Likewise.
259 (XMVex): Likewise.
260 (XMVexW): Likewise.
261 (XMVexI4): Likewise.
262 (PCLMUL): Likewise.
263 (VZERO): Likewise.
264 (VCMP): Likewise.
265 (VPERMIL2): Likewise.
266 (xmm_mode): Likewise.
267 (xmmq_mode): Likewise.
268 (ymmq_mode): Likewise.
269 (vex_mode): Likewise.
270 (vex128_mode): Likewise.
271 (vex256_mode): Likewise.
272 (USE_VEX_C4_TABLE): Likewise.
273 (USE_VEX_C5_TABLE): Likewise.
274 (USE_VEX_LEN_TABLE): Likewise.
275 (VEX_C4_TABLE): Likewise.
276 (VEX_C5_TABLE): Likewise.
277 (VEX_LEN_TABLE): Likewise.
278 (REG_VEX_XX): Likewise.
279 (MOD_VEX_XXX): Likewise.
280 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
281 (PREFIX_0F3A44): Likewise.
282 (PREFIX_0F3ADF): Likewise.
283 (PREFIX_VEX_XXX): Likewise.
284 (VEX_OF): Likewise.
285 (VEX_OF38): Likewise.
286 (VEX_OF3A): Likewise.
287 (VEX_LEN_XXX): Likewise.
288 (vex): Likewise.
289 (need_vex): Likewise.
290 (need_vex_reg): Likewise.
291 (vex_i4_done): Likewise.
292 (vex_table): Likewise.
293 (vex_len_table): Likewise.
294 (OP_REG_VexI4): Likewise.
295 (vex_cmp_op): Likewise.
296 (pclmul_op): Likewise.
297 (vpermil2_op): Likewise.
298 (m_mode): Updated.
299 (es_reg): Likewise.
300 (PREFIX_0F38F0): Likewise.
301 (PREFIX_0F3A60): Likewise.
302 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
303 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
304 and PREFIX_VEX_XXX entries.
305 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
306 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
307 PREFIX_0F3ADF.
308 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
309 Add MOD_VEX_XXX entries.
310 (ckprefix): Initialize rex_original and rex_ignored. Store the
311 REX byte in rex_original.
312 (get_valid_dis386): Handle the implicit prefix in VEX prefix
313 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
314 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
315 calling get_valid_dis386. Use rex_original and rex_ignored when
316 printing out REX.
317 (putop): Handle "XY".
318 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
319 ymmq_mode.
320 (OP_E_extended): Updated to use OP_E_register and
321 OP_E_memory.
322 (OP_XMM): Handle VEX.
323 (OP_EX): Likewise.
324 (XMM_Fixup): Likewise.
325 (CMP_Fixup): Use ARRAY_SIZE.
326
327 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
328 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
329 (operand_type_init): Add OPERAND_TYPE_REGYMM and
330 OPERAND_TYPE_VEX_IMM4.
331 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
332 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
333 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
334 VexImmExt and SSE2AVX.
335 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
336
337 * i386-opc.h (CpuAVX): New.
338 (CpuAES): Likewise.
339 (CpuCLMUL): Likewise.
340 (CpuFMA): Likewise.
341 (Vex): Likewise.
342 (Vex256): Likewise.
343 (VexNDS): Likewise.
344 (VexNDD): Likewise.
345 (VexW0): Likewise.
346 (VexW1): Likewise.
347 (Vex0F): Likewise.
348 (Vex0F38): Likewise.
349 (Vex0F3A): Likewise.
350 (Vex3Sources): Likewise.
351 (VexImmExt): Likewise.
352 (SSE2AVX): Likewise.
353 (RegYMM): Likewise.
354 (Ymmword): Likewise.
355 (Vex_Imm4): Likewise.
356 (Implicit1stXmm0): Likewise.
357 (CpuXsave): Updated.
358 (CpuLM): Likewise.
359 (ByteOkIntel): Likewise.
360 (OldGcc): Likewise.
361 (Control): Likewise.
362 (Unspecified): Likewise.
363 (OTMax): Likewise.
364 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
365 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
366 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
367 vex3sources, veximmext and sse2avx.
368 (i386_operand_type): Add regymm, ymmword and vex_imm4.
369
370 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
371
372 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
373
374 * i386-init.h: Regenerated.
375 * i386-tbl.h: Likewise.
376
b21c9cb4
BS		 3772008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
378
379 From Robin Getz <robin.getz@analog.com>
380 * bfin-dis.c (bu32): Typedef.
381 (enum const_forms_t): Add c_uimm32 and c_huimm32.
382 (constant_formats[]): Add uimm32 and huimm16.
383 (fmtconst_val): New.
384 (uimm32): Define.
385 (huimm32): Define.
386 (imm16_val): Define.
387 (luimm16_val): Define.
388 (struct saved_state): Define.
389 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
390 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
391 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
392 (get_allreg): New.
393 (decode_LDIMMhalf_0): Print out the whole register value.
394
ee171c8f
BS		 395 From Jie Zhang <jie.zhang@analog.com>
396 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
397 multiply and multiply-accumulate to data register instruction.
398
086134ec
BS		 399 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
400 c_imm32, c_huimm32e): Define.
401 (constant_formats): Add flags for printing decimal, leading spaces, and
402 exact symbols.
403 (comment, parallel): Add global flags in all disassembly.
404 (fmtconst): Take advantage of new flags, and print default in hex.
405 (fmtconst_val): Likewise.
406 (decode_macfunc): Be consistant with spaces, tabs, comments,
407 capitalization in disassembly, fix minor coding style issues.
408 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
409 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
410 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
411 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
412 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
413 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
414 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
415 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
416 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
417 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
418 _print_insn_bfin, print_insn_bfin): Likewise.
419
58c85be7
RW		 4202008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
421
422 * aclocal.m4: Regenerate.
423 * configure: Likewise.
424 * Makefile.in: Likewise.
425
50e7d84b
AM		 4262008-03-13 Alan Modra <amodra@bigpond.net.au>
427
428 * Makefile.am: Run "make dep-am".
429 * Makefile.in: Regenerate.
430 * configure: Regenerate.
431
de866fcc
AM		 4322008-03-07 Alan Modra <amodra@bigpond.net.au>
433
434 * ppc-opc.c (powerpc_opcodes): Order and format.
435
28dbc079
L		 4362008-03-01 H.J. Lu <hongjiu.lu@intel.com>
437
438 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
439 * i386-tbl.h: Regenerated.
440
849830bd
L		 4412008-02-23 H.J. Lu <hongjiu.lu@intel.com>
442
443 * i386-opc.tbl: Disallow 16-bit near indirect branches for
444 x86-64.
445 * i386-tbl.h: Regenerated.
446
743ddb6b
JB		 4472008-02-21 Jan Beulich <jbeulich@novell.com>
448
449 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
450 and Fword for far indirect jmp. Allow Reg16 and Word for near
451 indirect jmp on x86-64. Disallow Fword for lcall.
452 * i386-tbl.h: Re-generate.
453
796d5313
NC		 4542008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
455
456 * cr16-opc.c (cr16_num_optab): Defined
457
65da13b5
L		 4582008-02-16 H.J. Lu <hongjiu.lu@intel.com>
459
460 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
461 * i386-init.h: Regenerated.
462
0e336180
NC		 4632008-02-14 Nick Clifton <nickc@redhat.com>
464
465 PR binutils/5524
466 * configure.in (SHARED_LIBADD): Select the correct host specific
467 file extension for shared libraries.
468 * configure: Regenerate.
469
b7240065
JB		 4702008-02-13 Jan Beulich <jbeulich@novell.com>
471
472 * i386-opc.h (RegFlat): New.
473 * i386-reg.tbl (flat): Add.
474 * i386-tbl.h: Re-generate.
475
34b772a6
JB		 4762008-02-13 Jan Beulich <jbeulich@novell.com>
477
478 * i386-dis.c (a_mode): New.
479 (cond_jump_mode): Adjust.
480 (Ma): Change to a_mode.
481 (intel_operand_size): Handle a_mode.
482 * i386-opc.tbl: Allow Dword and Qword for bound.
483 * i386-tbl.h: Re-generate.
484
a60de03c
JB		 4852008-02-13 Jan Beulich <jbeulich@novell.com>
486
487 * i386-gen.c (process_i386_registers): Process new fields.
488 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
489 unsigned char. Add dw2_regnum and Dw2Inval.
490 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
491 register names.
492 * i386-tbl.h: Re-generate.
493
f03fe4c1
L		 4942008-02-11 H.J. Lu <hongjiu.lu@intel.com>
495
4b6bc8eb 496 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 497 * i386-init.h: Updated.
498
475a2301
L		 4992008-02-11 H.J. Lu <hongjiu.lu@intel.com>
500
501 * i386-gen.c (cpu_flags): Add CpuXsave.
502
503 * i386-opc.h (CpuXsave): New.
4b6bc8eb 504 (CpuLM): Updated.
475a2301
L		 505 (i386_cpu_flags): Add cpuxsave.
506
507 * i386-dis.c (MOD_0FAE_REG_4): New.
508 (RM_0F01_REG_2): Likewise.
509 (MOD_0FAE_REG_5): Updated.
510 (RM_0F01_REG_3): Likewise.
511 (reg_table): Use MOD_0FAE_REG_4.
512 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
513 for xrstor.
514 (rm_table): Add RM_0F01_REG_2.
515
516 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
517 * i386-init.h: Regenerated.
518 * i386-tbl.h: Likewise.
519
595785c6 5202008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 521
595785c6
JB		 522 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
523 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
524 * i386-tbl.h: Re-generate.
525
bb8541b9
L		 5262008-02-04 H.J. Lu <hongjiu.lu@intel.com>
527
528 PR 5715
529 * configure: Regenerated.
530
57b592a3
AN		 5312008-02-04 Adam Nemet <anemet@caviumnetworks.com>
532
533 * mips-dis.c: Update copyright.
534 (mips_arch_choices): Add Octeon.
535 * mips-opc.c: Update copyright.
536 (IOCT): New macro.
537 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
538
930bb4cf
AM		 5392008-01-29 Alan Modra <amodra@bigpond.net.au>
540
541 * ppc-opc.c: Support optional L form mtmsr.
542
82c18208
L		 5432008-01-24 H.J. Lu <hongjiu.lu@intel.com>
544
545 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
546
599121aa
L		 5472008-01-23 H.J. Lu <hongjiu.lu@intel.com>
548
549 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
550 * i386-init.h: Regenerated.
551
80098f51
TG		 5522008-01-23 Tristan Gingold <gingold@adacore.com>
553
554 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
555 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
556
115c7c25
L		 5572008-01-22 H.J. Lu <hongjiu.lu@intel.com>
558
559 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
560 (cpu_flags): Likewise.
561
562 * i386-opc.h (CpuMMX2): Removed.
563 (CpuSSE): Updated.
564
565 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
566 * i386-init.h: Regenerated.
567 * i386-tbl.h: Likewise.
568
6305a203
L		 5692008-01-22 H.J. Lu <hongjiu.lu@intel.com>
570
571 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
572 CPU_SMX_FLAGS.
573 * i386-init.h: Regenerated.
574
fd07a1c8
L		 5752008-01-15 H.J. Lu <hongjiu.lu@intel.com>
576
577 * i386-opc.tbl: Use Qword on movddup.
578 * i386-tbl.h: Regenerated.
579
321fd21e
L		 5802008-01-15 H.J. Lu <hongjiu.lu@intel.com>
581
582 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
583 * i386-tbl.h: Regenerated.
584
4ee52178
L		 5852008-01-15 H.J. Lu <hongjiu.lu@intel.com>
586
587 * i386-dis.c (Mx): New.
588 (PREFIX_0FC3): Likewise.
589 (PREFIX_0FC7_REG_6): Updated.
590 (dis386_twobyte): Use PREFIX_0FC3.
591 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
592 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
593 movntss.
594
5c07affc
L		 5952008-01-14 H.J. Lu <hongjiu.lu@intel.com>
596
597 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
598 (operand_types): Add Mem.
599
600 * i386-opc.h (IntelSyntax): New.
601 * i386-opc.h (Mem): New.
602 (Byte): Updated.
603 (Opcode_Modifier_Max): Updated.
604 (i386_opcode_modifier): Add intelsyntax.
605 (i386_operand_type): Add mem.
606
607 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
608 instructions.
609
610 * i386-reg.tbl: Add size for accumulator.
611
612 * i386-init.h: Regenerated.
613 * i386-tbl.h: Likewise.
614
0d6a2f58
L		 6152008-01-13 H.J. Lu <hongjiu.lu@intel.com>
616
617 * i386-opc.h (Byte): Fix a typo.
618
7d5e4556
L		 6192008-01-12 H.J. Lu <hongjiu.lu@intel.com>
620
621 PR gas/5534
622 * i386-gen.c (operand_type_init): Add Dword to
623 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
624 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
625 Qword and Xmmword.
626 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
627 Xmmword, Unspecified and Anysize.
628 (set_bitfield): Make Mmword an alias of Qword. Make Oword
629 an alias of Xmmword.
630
631 * i386-opc.h (CheckSize): Removed.
632 (Byte): Updated.
633 (Word): Likewise.
634 (Dword): Likewise.
635 (Qword): Likewise.
636 (Xmmword): Likewise.
637 (FWait): Updated.
638 (OTMax): Likewise.
639 (i386_opcode_modifier): Remove checksize, byte, word, dword,
640 qword and xmmword.
641 (Fword): New.
642 (TBYTE): Likewise.
643 (Unspecified): Likewise.
644 (Anysize): Likewise.
645 (i386_operand_type): Add byte, word, dword, fword, qword,
646 tbyte xmmword, unspecified and anysize.
647
648 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
649 Tbyte, Xmmword, Unspecified and Anysize.
650
651 * i386-reg.tbl: Add size for accumulator.
652
653 * i386-init.h: Regenerated.
654 * i386-tbl.h: Likewise.
655
b5b1fc4f
L		 6562008-01-10 H.J. Lu <hongjiu.lu@intel.com>
657
658 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
659 (REG_0F18): Updated.
660 (reg_table): Updated.
661 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
662 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
663
50e8458f
L		 6642008-01-08 H.J. Lu <hongjiu.lu@intel.com>
665
666 * i386-gen.c (set_bitfield): Use fail () on error.
667
3d4d5afa
L		 6682008-01-08 H.J. Lu <hongjiu.lu@intel.com>
669
670 * i386-gen.c (lineno): New.
671 (filename): Likewise.
672 (set_bitfield): Report filename and line numer on error.
673 (process_i386_opcodes): Set filename and update lineno.
674 (process_i386_registers): Likewise.
675
e1d4d893
L		 6762008-01-05 H.J. Lu <hongjiu.lu@intel.com>
677
678 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
679 ATTSyntax.
680
681 * i386-opc.h (IntelMnemonic): Renamed to ..
682 (ATTSyntax): This
683 (Opcode_Modifier_Max): Updated.
684 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
685 and intelsyntax.
686
8944f3c2 687 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 688 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
689 * i386-tbl.h: Regenerated.
690
6f143e4d
L		 6912008-01-04 H.J. Lu <hongjiu.lu@intel.com>
692
693 * i386-gen.c: Update copyright to 2008.
694 * i386-opc.h: Likewise.
695 * i386-opc.tbl: Likewise.
696
697 * i386-init.h: Regenerated.
698 * i386-tbl.h: Likewise.
699
c6add537
L		 7002008-01-04 H.J. Lu <hongjiu.lu@intel.com>
701
702 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
703 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
704 * i386-tbl.h: Regenerated.
705
3629bb00
L		 7062008-01-03 H.J. Lu <hongjiu.lu@intel.com>
707
708 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
709 CpuSSE4_2_Or_ABM.
710 (cpu_flags): Likewise.
711
712 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
713 (CpuSSE4_2_Or_ABM): Likewise.
714 (CpuLM): Updated.
715 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
716
717 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
718 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
719 and CpuPadLock, respectively.
720 * i386-init.h: Regenerated.
721 * i386-tbl.h: Likewise.
722
24995bd6
L		 7232008-01-03 H.J. Lu <hongjiu.lu@intel.com>
724
725 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
726
727 * i386-opc.h (No_xSuf): Removed.
728 (CheckSize): Updated.
729
730 * i386-tbl.h: Regenerated.
731
e0329a22
L		 7322008-01-02 H.J. Lu <hongjiu.lu@intel.com>
733
734 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
735 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
736 CPU_SSE5_FLAGS.
737 (cpu_flags): Add CpuSSE4_2_Or_ABM.
738
739 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
740 (CpuLM): Updated.
741 (i386_cpu_flags): Add cpusse4_2_or_abm.
742
743 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
744 CpuABM|CpuSSE4_2 on popcnt.
745 * i386-init.h: Regenerated.
746 * i386-tbl.h: Likewise.
747
f2a9c676
L		 7482008-01-02 H.J. Lu <hongjiu.lu@intel.com>
749
750 * i386-opc.h: Update comments.
751
d978b5be
L		 7522008-01-02 H.J. Lu <hongjiu.lu@intel.com>
753
754 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
755 * i386-opc.h: Likewise.
756 * i386-opc.tbl: Likewise.
757
582d5edd
L		 7582008-01-02 H.J. Lu <hongjiu.lu@intel.com>
759
760 PR gas/5534
761 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
762 Byte, Word, Dword, QWord and Xmmword.
763
764 * i386-opc.h (No_xSuf): New.
765 (CheckSize): Likewise.
766 (Byte): Likewise.
767 (Word): Likewise.
768 (Dword): Likewise.
769 (QWord): Likewise.
770 (Xmmword): Likewise.
771 (FWait): Updated.
772 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
773 Dword, QWord and Xmmword.
774
775 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
776 used.
777 * i386-tbl.h: Regenerated.
778
3fe15143
MK		 7792008-01-02 Mark Kettenis <kettenis@gnu.org>
780
781 * m88k-dis.c (instructions): Fix fcvt.* instructions.
782 From Miod Vallat.
783
6c7ac64e 784For older changes see ChangeLog-2007
252b5132
RH		 785\f
786Local Variables:
2f6d2f85
NC		 787mode: change-log
788left-margin: 8
789fill-column: 74
252b5132
RH		 790version-control: never
791End:
GDB Binutils - Deliverables
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