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Tweak MBIND ld test for ARM.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
62ecb94c
PC		 12017-04-06 Pip Cet <pipcet@gmail.com>
2
3 * Makefile.am: Add wasm32-dis.c.
4 * configure.ac: Add wasm32-dis.c to wasm32 target.
5 * disassemble.c: Add wasm32 disassembler code.
6 * wasm32-dis.c: New file.
7 * Makefile.in: Regenerate.
8 * configure: Regenerate.
9 * po/POTFILES.in: Regenerate.
10 * po/opcodes.pot: Regenerate.
11
f995bbe8
PA		 122017-04-05 Pedro Alves <palves@redhat.com>
13
14 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
15 * arm-dis.c (parse_arm_disassembler_options): Constify.
16 * ppc-dis.c (powerpc_init_dialect): Constify local.
17 * vax-dis.c (parse_disassembler_options): Constify.
18
b5292032
PD		 192017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
20
21 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
22 RISCV_GP_SYMBOL.
23
f96bd6c2
PC		 242017-03-30 Pip Cet <pipcet@gmail.com>
25
26 * configure.ac: Add (empty) bfd_wasm32_arch target.
27 * configure: Regenerate
28 * po/opcodes.pot: Regenerate.
29
f7c514a3
JM		 302017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
31
32 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
33 OSA2015.
34 * opcodes/sparc-opc.c (asi_table): New ASIs.
35
52be03fd
AM		 362017-03-29 Alan Modra <amodra@gmail.com>
37
38 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
39 "raw" option.
40 (lookup_powerpc): Don't special case -1 dialect. Handle
41 PPC_OPCODE_RAW.
42 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
43 lookup_powerpc call, pass it on second.
44
9b753937
AM		 452017-03-27 Alan Modra <amodra@gmail.com>
46
47 PR 21303
48 * ppc-dis.c (struct ppc_mopt): Comment.
49 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
50
c0c31e91
RZ		 512017-03-27 Rinat Zelig <rinat@mellanox.com>
52
53 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
54 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
55 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
56 (insert_nps_misc_imm_offset): New function.
57 (extract_nps_misc imm_offset): New function.
58 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
59 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
60
2253c8f0
AK		 612017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
62
63 * s390-mkopc.c (main): Remove vx2 check.
64 * s390-opc.txt: Remove vx2 instruction flags.
65
645d3342
RZ		 662017-03-21 Rinat Zelig <rinat@mellanox.com>
67
68 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
69 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
70 (insert_nps_imm_offset): New function.
71 (extract_nps_imm_offset): New function.
72 (insert_nps_imm_entry): New function.
73 (extract_nps_imm_entry): New function.
74
4b94dd2d
AM		 752017-03-17 Alan Modra <amodra@gmail.com>
76
77 PR 21248
78 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
79 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
80 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
81
b416fe87
KC		 822017-03-14 Kito Cheng <kito.cheng@gmail.com>
83
84 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
85 <c.andi>: Likewise.
86 <c.addiw> Likewise.
87
03b039a5
KC		 882017-03-14 Kito Cheng <kito.cheng@gmail.com>
89
90 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
91
2c232b83
AW		 922017-03-13 Andrew Waterman <andrew@sifive.com>
93
94 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
95 <srl> Likewise.
96 <srai> Likewise.
97 <sra> Likewise.
98
86fa6981
L		 992017-03-09 H.J. Lu <hongjiu.lu@intel.com>
100
101 * i386-gen.c (opcode_modifiers): Replace S with Load.
102 * i386-opc.h (S): Removed.
103 (Load): New.
104 (i386_opcode_modifier): Replace s with load.
105 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
106 and {evex}. Replace S with Load.
107 * i386-tbl.h: Regenerated.
108
c1fe188b
L		 1092017-03-09 H.J. Lu <hongjiu.lu@intel.com>
110
111 * i386-opc.tbl: Use CpuCET on rdsspq.
112 * i386-tbl.h: Regenerated.
113
4b8b687e
PB		 1142017-03-08 Peter Bergner <bergner@vnet.ibm.com>
115
116 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
117 <vsx>: Do not use PPC_OPCODE_VSX3;
118
1437d063
PB		 1192017-03-08 Peter Bergner <bergner@vnet.ibm.com>
120
121 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
122
603555e5
L		 1232017-03-06 H.J. Lu <hongjiu.lu@intel.com>
124
125 * i386-dis.c (REG_0F1E_MOD_3): New enum.
126 (MOD_0F1E_PREFIX_1): Likewise.
127 (MOD_0F38F5_PREFIX_2): Likewise.
128 (MOD_0F38F6_PREFIX_0): Likewise.
129 (RM_0F1E_MOD_3_REG_7): Likewise.
130 (PREFIX_MOD_0_0F01_REG_5): Likewise.
131 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
132 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
133 (PREFIX_0F1E): Likewise.
134 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
135 (PREFIX_0F38F5): Likewise.
136 (dis386_twobyte): Use PREFIX_0F1E.
137 (reg_table): Add REG_0F1E_MOD_3.
138 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
139 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
140 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
141 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
142 (three_byte_table): Use PREFIX_0F38F5.
143 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
144 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
145 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
146 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
147 PREFIX_MOD_3_0F01_REG_5_RM_2.
148 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
149 (cpu_flags): Add CpuCET.
150 * i386-opc.h (CpuCET): New enum.
151 (CpuUnused): Commented out.
152 (i386_cpu_flags): Add cpucet.
153 * i386-opc.tbl: Add Intel CET instructions.
154 * i386-init.h: Regenerated.
155 * i386-tbl.h: Likewise.
156
73f07bff
AM		 1572017-03-06 Alan Modra <amodra@gmail.com>
158
159 PR 21124
160 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
161 (extract_raq, extract_ras, extract_rbx): New functions.
162 (powerpc_operands): Use opposite corresponding insert function.
163 (Q_MASK): Define.
164 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
165 register restriction.
166
65b48a81
PB		 1672017-02-28 Peter Bergner <bergner@vnet.ibm.com>
168
169 * disassemble.c Include "safe-ctype.h".
170 (disassemble_init_for_target): Handle s390 init.
171 (remove_whitespace_and_extra_commas): New function.
172 (disassembler_options_cmp): Likewise.
173 * arm-dis.c: Include "libiberty.h".
174 (NUM_ELEM): Delete.
175 (regnames): Use long disassembler style names.
176 Add force-thumb and no-force-thumb options.
177 (NUM_ARM_REGNAMES): Rename from this...
178 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
179 (get_arm_regname_num_options): Delete.
180 (set_arm_regname_option): Likewise.
181 (get_arm_regnames): Likewise.
182 (parse_disassembler_options): Likewise.
183 (parse_arm_disassembler_option): Rename from this...
184 (parse_arm_disassembler_options): ...to this. Make static.
185 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
186 (print_insn): Use parse_arm_disassembler_options.
187 (disassembler_options_arm): New function.
188 (print_arm_disassembler_options): Handle updated regnames.
189 * ppc-dis.c: Include "libiberty.h".
190 (ppc_opts): Add "32" and "64" entries.
191 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
192 (powerpc_init_dialect): Add break to switch statement.
193 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
194 (disassembler_options_powerpc): New function.
195 (print_ppc_disassembler_options): Use ARRAY_SIZE.
196 Remove printing of "32" and "64".
197 * s390-dis.c: Include "libiberty.h".
198 (init_flag): Remove unneeded variable.
199 (struct s390_options_t): New structure type.
200 (options): New structure.
201 (init_disasm): Rename from this...
202 (disassemble_init_s390): ...to this. Add initializations for
203 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
204 (print_insn_s390): Delete call to init_disasm.
205 (disassembler_options_s390): New function.
206 (print_s390_disassembler_options): Print using information from
207 struct 'options'.
208 * po/opcodes.pot: Regenerate.
209
15c7c1d8
JB		 2102017-02-28 Jan Beulich <jbeulich@suse.com>
211
212 * i386-dis.c (PCMPESTR_Fixup): New.
213 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
214 (prefix_table): Use PCMPESTR_Fixup.
215 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
216 PCMPESTR_Fixup.
217 (vex_w_table): Delete VPCMPESTR{I,M} entries.
218 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
219 Split 64-bit and non-64-bit variants.
220 * opcodes/i386-tbl.h: Re-generate.
221
582e12bf
RS		 2222017-02-24 Richard Sandiford <richard.sandiford@arm.com>
223
224 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
225 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
226 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
227 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
228 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
229 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
230 (OP_SVE_V_HSD): New macros.
231 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
232 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
233 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
234 (aarch64_opcode_table): Add new SVE instructions.
235 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
236 for rotation operands. Add new SVE operands.
237 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
238 (ins_sve_quad_index): Likewise.
239 (ins_imm_rotate): Split into...
240 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
241 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
242 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
243 functions.
244 (aarch64_ins_sve_addr_ri_s4): New function.
245 (aarch64_ins_sve_quad_index): Likewise.
246 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
247 * aarch64-asm-2.c: Regenerate.
248 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
249 (ext_sve_quad_index): Likewise.
250 (ext_imm_rotate): Split into...
251 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
252 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
253 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
254 functions.
255 (aarch64_ext_sve_addr_ri_s4): New function.
256 (aarch64_ext_sve_quad_index): Likewise.
257 (aarch64_ext_sve_index): Allow quad indices.
258 (do_misc_decoding): Likewise.
259 * aarch64-dis-2.c: Regenerate.
260 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
261 aarch64_field_kinds.
262 (OPD_F_OD_MASK): Widen by one bit.
263 (OPD_F_NO_ZR): Bump accordingly.
264 (get_operand_field_width): New function.
265 * aarch64-opc.c (fields): Add new SVE fields.
266 (operand_general_constraint_met_p): Handle new SVE operands.
267 (aarch64_print_operand): Likewise.
268 * aarch64-opc-2.c: Regenerate.
269
f482d304
RS		 2702017-02-24 Richard Sandiford <richard.sandiford@arm.com>
271
272 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
273 (aarch64_feature_compnum): ...this.
274 (SIMD_V8_3): Replace with...
275 (COMPNUM): ...this.
276 (CNUM_INSN): New macro.
277 (aarch64_opcode_table): Use it for the complex number instructions.
278
7db2c588
JB		 2792017-02-24 Jan Beulich <jbeulich@suse.com>
280
281 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
282
1e9d41d4
SL		 2832017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
284
285 Add support for associating SPARC ASIs with an architecture level.
286 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
287 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
288 decoding of SPARC ASIs.
289
53c4d625
JB		 2902017-02-23 Jan Beulich <jbeulich@suse.com>
291
292 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
293 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
294
11648de5
JB		 2952017-02-21 Jan Beulich <jbeulich@suse.com>
296
297 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
298 1 (instead of to itself). Correct typo.
299
f98d33be
AW		 3002017-02-14 Andrew Waterman <andrew@sifive.com>
301
302 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
303 pseudoinstructions.
304
773fb663
RS		 3052017-02-15 Richard Sandiford <richard.sandiford@arm.com>
306
307 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
308 (aarch64_sys_reg_supported_p): Handle them.
309
cc07cda6
CZ		 3102017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
311
312 * arc-opc.c (UIMM6_20R): Define.
313 (SIMM12_20): Use above.
314 (SIMM12_20R): Define.
315 (SIMM3_5_S): Use above.
316 (UIMM7_A32_11R_S): Define.
317 (UIMM7_9_S): Use above.
318 (UIMM3_13R_S): Define.
319 (SIMM11_A32_7_S): Use above.
320 (SIMM9_8R): Define.
321 (UIMM10_A32_8_S): Use above.
322 (UIMM8_8R_S): Define.
323 (W6): Use above.
324 (arc_relax_opcodes): Use all above defines.
325
66a5a740
VG		 3262017-02-15 Vineet Gupta <vgupta@synopsys.com>
327
328 * arc-regs.h: Distinguish some of the registers different on
329 ARC700 and HS38 cpus.
330
7e0de605
AM		 3312017-02-14 Alan Modra <amodra@gmail.com>
332
333 PR 21118
334 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
335 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
336
54064fdb
AM		 3372017-02-11 Stafford Horne <shorne@gmail.com>
338 Alan Modra <amodra@gmail.com>
339
340 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
341 Use insn_bytes_value and insn_int_value directly instead. Don't
342 free allocated memory until function exit.
343
dce75bf9
NP		 3442017-02-10 Nicholas Piggin <npiggin@gmail.com>
345
346 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
347
1b7e3d2f
NC		 3482017-02-03 Nick Clifton <nickc@redhat.com>
349
350 PR 21096
351 * aarch64-opc.c (print_register_list): Ensure that the register
352 list index will fir into the tb buffer.
353 (print_register_offset_address): Likewise.
354 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
355
8ec5cf65
AD		 3562017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
357
358 PR 21056
359 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
360 instructions when the previous fetch packet ends with a 32-bit
361 instruction.
362
a1aa5e81
DD		 3632017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
364
365 * pru-opc.c: Remove vague reference to a future GDB port.
366
add3afb2
NC		 3672017-01-20 Nick Clifton <nickc@redhat.com>
368
369 * po/ga.po: Updated Irish translation.
370
c13a63b0
SN		 3712017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
372
373 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
374
9608051a
YQ		 3752017-01-13 Yao Qi <yao.qi@linaro.org>
376
377 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
378 if FETCH_DATA returns 0.
379 (m68k_scan_mask): Likewise.
380 (print_insn_m68k): Update code to handle -1 return value.
381
f622ea96
YQ		 3822017-01-13 Yao Qi <yao.qi@linaro.org>
383
384 * m68k-dis.c (enum print_insn_arg_error): New.
385 (NEXTBYTE): Replace -3 with
386 PRINT_INSN_ARG_MEMORY_ERROR.
387 (NEXTULONG): Likewise.
388 (NEXTSINGLE): Likewise.
389 (NEXTDOUBLE): Likewise.
390 (NEXTDOUBLE): Likewise.
391 (NEXTPACKED): Likewise.
392 (FETCH_ARG): Likewise.
393 (FETCH_DATA): Update comments.
394 (print_insn_arg): Update comments. Replace magic numbers with
395 enum.
396 (match_insn_m68k): Likewise.
397
620214f7
IT		 3982017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
399
400 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
401 * i386-dis-evex.h (evex_table): Updated.
402 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
403 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
404 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
405 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
406 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
407 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
408 * i386-init.h: Regenerate.
409 * i386-tbl.h: Ditto.
410
d95014a2
YQ		 4112017-01-12 Yao Qi <yao.qi@linaro.org>
412
413 * msp430-dis.c (msp430_singleoperand): Return -1 if
414 msp430dis_opcode_signed returns false.
415 (msp430_doubleoperand): Likewise.
416 (msp430_branchinstr): Return -1 if
417 msp430dis_opcode_unsigned returns false.
418 (msp430x_calla_instr): Likewise.
419 (print_insn_msp430): Likewise.
420
0ae60c3e
NC		 4212017-01-05 Nick Clifton <nickc@redhat.com>
422
423 PR 20946
424 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
425 could not be matched.
426 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
427 NULL.
428
d74d4880
SN		 4292017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
430
431 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
432 (aarch64_opcode_table): Use RCPC_INSN.
433
cc917fd9
KC		 4342017-01-03 Kito Cheng <kito.cheng@gmail.com>
435
436 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
437 extension.
438 * riscv-opcodes/all-opcodes: Likewise.
439
b52d3cfc
DP		 4402017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
441
442 * riscv-dis.c (print_insn_args): Add fall through comment.
443
f90c58d5
NC		 4442017-01-03 Nick Clifton <nickc@redhat.com>
445
446 * po/sr.po: New Serbian translation.
447 * configure.ac (ALL_LINGUAS): Add sr.
448 * configure: Regenerate.
449
f47b0d4a
AM		 4502017-01-02 Alan Modra <amodra@gmail.com>
451
452 * epiphany-desc.h: Regenerate.
453 * epiphany-opc.h: Regenerate.
454 * fr30-desc.h: Regenerate.
455 * fr30-opc.h: Regenerate.
456 * frv-desc.h: Regenerate.
457 * frv-opc.h: Regenerate.
458 * ip2k-desc.h: Regenerate.
459 * ip2k-opc.h: Regenerate.
460 * iq2000-desc.h: Regenerate.
461 * iq2000-opc.h: Regenerate.
462 * lm32-desc.h: Regenerate.
463 * lm32-opc.h: Regenerate.
464 * m32c-desc.h: Regenerate.
465 * m32c-opc.h: Regenerate.
466 * m32r-desc.h: Regenerate.
467 * m32r-opc.h: Regenerate.
468 * mep-desc.h: Regenerate.
469 * mep-opc.h: Regenerate.
470 * mt-desc.h: Regenerate.
471 * mt-opc.h: Regenerate.
472 * or1k-desc.h: Regenerate.
473 * or1k-opc.h: Regenerate.
474 * xc16x-desc.h: Regenerate.
475 * xc16x-opc.h: Regenerate.
476 * xstormy16-desc.h: Regenerate.
477 * xstormy16-opc.h: Regenerate.
478
2571583a
AM		 4792017-01-02 Alan Modra <amodra@gmail.com>
480
481 Update year range in copyright notice of all files.
482
5c1ad6b5 483For older changes see ChangeLog-2016
3499769a 484\f
5c1ad6b5 485Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 486
487Copying and distribution of this file, with or without modification,
488are permitted in any medium without royalty provided the copyright
489notice and this notice are preserved.
490
491Local Variables:
492mode: change-log
493left-margin: 8
494fill-column: 74
495version-control: never
496End:
GDB Binutils - Deliverables
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